1 /*
2 * SPDX-FileCopyrightText: 2016 STMicroelectronics
3 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
4 *
5 * SPDX-License-Identifier: BSD-3-Clause AND Apache-2.0
6 */
7
8 #include "bf0_hal.h"
9
10 /** @addtogroup BF0_HAL_Driver
11 * @{
12 */
13
14 /** @defgroup ADC Analog Digital Converter
15 * @brief ADC HAL module driver
16 * @{
17 */
18
19 #ifdef HAL_ADC_MODULE_ENABLED
20
21
22
23 /* Private typedef -----------------------------------------------------------*/
24 /* Private define ------------------------------------------------------------*/
25 /** @defgroup ADC_Private_Constants ADC Private Constants
26 * @{
27 */
28
29
30 /**
31 * @}
32 */
33
34 /* Private macro -------------------------------------------------------------*/
35 /* Private variables ---------------------------------------------------------*/
36 /* Private function prototypes -----------------------------------------------*/
37 /** @defgroup ADC_Private_Functions ADC Private Functions
38 * @{
39 */
40
41
42 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
43 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
44
45 /**
46 * @}
47 */
48
49 /* Exported functions ---------------------------------------------------------*/
50
51 /** @defgroup ADC_Exported_Functions ADC Exported Functions
52 * @{
53 */
54
55 /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
56 * @brief Initialization and Configuration functions
57 *
58 @verbatim
59 ===============================================================================
60 ##### Initialization and de-initialization functions #####
61 ===============================================================================
62 [..] This section provides functions allowing to:
63 (+) Initialize and configure the ADC.
64 (+) De-initialize the ADC
65 @endverbatim
66 * @{
67 */
68
69 /**
70 * @brief Initializes the ADC peripheral and regular group according to
71 * parameters specified in structure "ADC_InitTypeDef".
72 * @note As prerequisite, ADC clock must be configured at RCC top level
73 * depending on both possible clock sources: APB clock of HSI clock.
74 * @note Possibility to update parameters on the fly:
75 * The setting of these parameters is conditioned to ADC state.
76 * For parameters constraints, see comments of structure
77 * "ADC_InitTypeDef".
78 * @note This function configures the ADC within 2 scopes: scope of entire
79 * ADC and scope of regular group. For parameters details, see comments
80 * of structure "ADC_InitTypeDef".
81 * @param hadc ADC handle
82 * @retval HAL status
83 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)84 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
85 {
86 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
87 uint32_t i;
88
89 /* Check ADC handle */
90 if (hadc == NULL)
91 {
92 return HAL_ERROR;
93 }
94
95 /* Actions performed only if ADC is coming from state reset: */
96 /* - ADC voltage regulator enable */
97 if (hadc->State == HAL_ADC_STATE_RESET)
98 {
99 /* Initialize ADC error code */
100 ADC_CLEAR_ERRORCODE(hadc);
101
102 /* Allocate lock resource and initialize it */
103 hadc->Lock = HAL_UNLOCKED;
104 }
105
106 /* Initial ADC Msp */
107 HAL_ADC_MspInit(hadc);
108
109 /* Configuration of ADC parameters if previous preliminary actions are */
110 /* correctly completed. */
111 /* and if there is no conversion on going on regular group (ADC can be */
112 /* enabled anyway, in case of call of this function to update a parameter */
113 /* on the fly). */
114 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
115 (tmp_hal_status == HAL_OK))
116 {
117 /* Set ADC state */
118 ADC_STATE_CLR_SET(hadc->State,
119 HAL_ADC_STATE_REG_BUSY,
120 HAL_ADC_STATE_BUSY_INTERNAL);
121
122 /* TODO , Init ADC configure register for analog */
123 //hadc->Instance->ADC_CFG_REG1 = ;
124
125 /* Set single channel */
126 hadc->Instance->ADC_CFG_REG1 |= GPADC_ADC_CFG_REG1_ANAU_GPADC_SE;
127
128 i = hadc->Instance->ADC_CTRL_REG;
129 // disable all triger mode by default
130 i &= (~(GPADC_ADC_CTRL_REG_GPIO_TRIG_EN | GPADC_ADC_CTRL_REG_TIMER_TRIG_EN | GPADC_ADC_CTRL_REG_INIT_TIME));
131 // set init time to max
132 #if (GPADC_CALIB_FLOW_VERSION == 1)
133 i |= GPADC_ADC_CTRL_REG_INIT_TIME;
134 #else
135 i |= (8 << GPADC_ADC_CTRL_REG_INIT_TIME_Pos);
136 #endif
137 hadc->Instance->ADC_CTRL_REG = i;
138 #if (GPADC_CALIB_FLOW_VERSION != 1)
139 __HAL_ADC_SET_SAMPLE_WIDTH(hadc, hadc->Init.sample_width);
140 __HAL_ADC_SET_CONV_WIDTH(hadc, hadc->Init.conv_width);
141 __HAL_ADC_SET_DATA_DELAY(hadc, hadc->Init.data_samp_delay);
142 // TODO: Add for Range
143 #else
144 /* Set ADC clock, clk = 12/(div+1) */
145 __HAL_ADC_SET_CLOCK_DIV(hadc, hadc->Init.clk_div);
146 // set range
147 if (hadc->Init.atten3) //enable 3X mode
148 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_ATTN3X);
149 else //disable 3X mode
150 hadc->Instance->ADC_CFG_REG1 &= (~GPADC_ADC_CFG_REG1_ANAU_GPADC_ATTN3X);
151 #endif
152
153
154 /* Disable all slot at initial */
155 for (i = 0; i < 8; i++)
156 HAL_ADC_EnableSlot(hadc, i, 0);
157
158 // set LDOCORE and LDOREF enable
159 #if (GPADC_CALIB_FLOW_VERSION != 1)
160 // TODO:
161 uint32_t value;
162 value = hadc->Instance->ADC_CFG_REG1;
163 // register default setting from hardware sample code
164 #if (GPADC_CALIB_FLOW_VERSION == 3)
165 value &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_VSP | GPADC_ADC_CFG_REG1_ANAU_GPADC_CMM | GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_V18);
166
167 if (hadc->Init.avdd_v18_en)
168 value |= (0x8 << GPADC_ADC_CFG_REG1_ANAU_GPADC_CMM_Pos) | GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_V18;
169 else
170 #else
171 value &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_VSP | GPADC_ADC_CFG_REG1_ANAU_GPADC_CMM);
172 #endif
173 value |= ((2 << GPADC_ADC_CFG_REG1_ANAU_GPADC_VSP_Pos) | (0x10 << GPADC_ADC_CFG_REG1_ANAU_GPADC_CMM_Pos));
174 hadc->Instance->ADC_CFG_REG1 = value;
175
176 #if (GPADC_CALIB_FLOW_VERSION == 3)
177 hwp_hpsys_cfg->ANAU_CR |= (HPSYS_CFG_ANAU_CR_EN_BG);
178 #endif /* (GPADC_CALIB_FLOW_VERSION == 3) */
179
180 #else // (GPADC_CALIB_FLOW_VERSION == 1)
181 hwp_tsen->BGR |= TSEN_BGR_EN;
182 hwp_tsen->ANAU_ANA_TP |= TSEN_ANAU_ANA_TP_ANAU_IARY_EN;
183 #endif
184
185 }
186 else
187 {
188 /* Update ADC state machine to error */
189 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
190
191 tmp_hal_status = HAL_ERROR;
192 }
193
194 /* Return function status */
195 return tmp_hal_status;
196 }
197
198
199 /**
200 * @brief Deinitialize the ADC peripheral registers to their default reset
201 * values, with deinitialization of the ADC MSP.
202 * @note For devices with several ADCs: reset of ADC common registers is done
203 * only if all ADCs sharing the same common group are disabled.
204 * If this is not the case, reset of these common parameters reset is
205 * bypassed without error reporting: it can be the intended behaviour in
206 * case of reset of a single ADC while the other ADCs sharing the same
207 * common group is still running.
208 * @param hadc ADC handle
209 * @retval HAL status
210 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)211 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
212 {
213 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
214
215 /* Check ADC handle */
216 if (hadc == NULL)
217 {
218 return HAL_ERROR;
219 }
220
221 /* Set ADC state */
222 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
223
224 /* Disable ADC peripheral if conversions are effectively stopped */
225 if (tmp_hal_status == HAL_OK)
226 {
227 // reset LDOCORE and LDOREF enable
228 //hadc->Instance->ADC_CFG_REG1 &= (~(GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN|GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN));
229
230 /* Check if ADC is effectively disabled */
231 if (tmp_hal_status != HAL_ERROR)
232 {
233 /* Change ADC state */
234 hadc->State = HAL_ADC_STATE_READY;
235 }
236 }
237
238
239 /* Configuration of ADC parameters if previous preliminary actions are */
240 /* correctly completed. */
241 if (tmp_hal_status != HAL_ERROR)
242 {
243 /* Set ADC error code to none */
244 ADC_CLEAR_ERRORCODE(hadc);
245
246 /* Set ADC state */
247 hadc->State = HAL_ADC_STATE_RESET;
248 }
249
250 /* Deinitial ADC Msp */
251 HAL_ADC_MspDeInit(hadc);
252
253 /* Process unlocked */
254 __HAL_UNLOCK(hadc);
255
256 /* Return function status */
257 return tmp_hal_status;
258 }
259
HAL_ADC_HwInit(bool cold_boot)260 void HAL_ADC_HwInit(bool cold_boot)
261 {
262 #if defined(SF32LB55X) || defined(SF32LB56X) || defined(SF32LB58X) || defined(SF32LB52X)
263 #ifdef SOC_BF0_HCPU
264 if (cold_boot)
265 {
266 /* init adc by HCPU when cold boot */
267 hwp_gpadc1->ADC_CTRL_REG &= ~GPADC_ADC_CTRL_REG_TIMER_TRIG_EN;
268 }
269 #ifdef SF32LB52X
270 else
271 {
272 /* gpadc1 is by HPSYS side on SF32LB52X */
273 hwp_gpadc1->ADC_CTRL_REG &= ~GPADC_ADC_CTRL_REG_TIMER_TRIG_EN;
274 }
275 #endif /* SF32LB52X */
276 #else
277 #ifndef SF32LB52X
278 if (!cold_boot)
279 {
280 /* init adc by LCPU for non-cold boot as gpadc1 is in LPSYS except SF32LB52X,
281 */
282 hwp_gpadc1->ADC_CTRL_REG &= ~GPADC_ADC_CTRL_REG_TIMER_TRIG_EN;
283 }
284 #endif /* !SF32LB52X */
285 #endif /* SOC_BF0_HCPU */
286 #endif /* SF32LB55X || SF32LB56X || SF32LB58X || SF32LB52X */
287 }
288
289 /**
290 * @}
291 */
292
293 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
294 * @brief IO operation functions
295 *
296 @verbatim
297 ===============================================================================
298 ##### IO operation functions #####
299 ===============================================================================
300 [..] This section provides functions allowing to:
301 (+) Start conversion of regular group.
302 (+) Stop conversion of regular group.
303 (+) Poll for conversion complete on regular group.
304 (+) Poll for conversion event.
305 (+) Get result of regular channel conversion.
306 (+) Start conversion of regular group and enable interruptions.
307 (+) Stop conversion of regular group and disable interruptions.
308 (+) Handle ADC interrupt request
309 (+) Start conversion of regular group and enable DMA transfer.
310 (+) Stop conversion of regular group and disable ADC DMA transfer.
311 @endverbatim
312 * @{
313 */
314
315 /**
316 * @brief Prepare ADC setting before start triger.
317 * @param hadc ADC handle
318 * @retval HAL status
319 */
HAL_ADC_Prepare(ADC_HandleTypeDef * hadc)320 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Prepare(ADC_HandleTypeDef *hadc)
321 {
322 if (hadc == NULL)
323 return HAL_ERROR;
324
325 #if (GPADC_CALIB_FLOW_VERSION != 1)
326 #if (GPADC_CALIB_FLOW_VERSION == 3)
327 // enable analog
328 hwp_hpsys_cfg->ANAU_CR |= (HPSYS_CFG_ANAU_CR_EN_VBAT_MON);
329 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
330 #else /* GPADC_CALIB_FLOW_VERSION == 2 */
331 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_BG | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
332 #endif /* GPADC_CALIB_FLOW_VERSION == 3 */
333 ADC_SET_UNMUTE(hadc);
334
335 #else /* (GPADC_CALIB_FLOW_VERSION == 1) */
336 // set LDOCORE and LDOREF enable
337 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
338 #endif
339
340 HAL_Delay_us(200);
341 hadc->Instance->ADC_CTRL_REG |= (GPADC_ADC_CTRL_REG_FRC_EN_ADC);
342
343 // TODO: force set to single end, if use differential mode later, add new interface or paramter
344 __HAL_ADC_SINGLE_END(hadc);
345
346 /* Process locked */
347 __HAL_LOCK(hadc);
348
349 /* Start conversion if ADC is effectively enabled */
350
351 /* Set ADC state */
352 /* - Clear state bitfield related to regular group conversion results */
353 /* - Set state bitfield related to regular operation */
354 ADC_STATE_CLR_SET(hadc->State,
355 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_START_IRQ_DONE,
356 HAL_ADC_STATE_REG_BUSY);
357
358 /* Reset ADC all error code fields */
359 ADC_CLEAR_ERRORCODE(hadc);
360 #if (GPADC_CALIB_FLOW_VERSION != 1)
361 HAL_Delay_us(200);
362 #else
363 HAL_Delay_us(50);
364 #endif
365 /* Process unlocked */
366 /* Unlock before starting ADC conversions: in case of potential */
367 /* interruption, to let the process to ADC IRQ Handler. */
368 __HAL_UNLOCK(hadc);
369
370 /* Return function status */
371 return HAL_OK;
372 }
373
374 /**
375 * @brief Enables ADC, starts conversion of regular group.
376 * Interruptions enabled in this function: None.
377 * @param hadc ADC handle
378 * @retval HAL status
379 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)380 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
381 {
382 HAL_StatusTypeDef res = HAL_OK;
383
384 /* Perform ADC enable and conversion start if no conversion is on going */
385 res = HAL_ADC_Prepare(hadc);
386 if (res == HAL_OK)
387 __HAL_ADC_START_CONV(hadc);
388
389 return res;
390 }
391
392 /**
393 * @brief Stop ADC conversion of regular group, disable ADC peripheral.
394 * @param hadc ADC handle
395 * @retval HAL status.
396 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)397 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
398 {
399 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
400
401 /* Process locked */
402 __HAL_LOCK(hadc);
403
404 if (hadc->Init.op_mode != 0)
405 hadc->Instance->ADC_CTRL_REG |= GPADC_ADC_CTRL_REG_ADC_STOP;
406
407 /* Set ADC state */
408 ADC_STATE_CLR_SET(hadc->State,
409 HAL_ADC_STATE_REG_BUSY,
410 HAL_ADC_STATE_READY);
411
412 // reset LDOCORE and LDOREF enable
413 #if (GPADC_CALIB_FLOW_VERSION != 1)
414 #if (GPADC_CALIB_FLOW_VERSION == 3)
415 hadc->Instance->ADC_CFG_REG1 &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
416 hwp_hpsys_cfg->ANAU_CR &= (~HPSYS_CFG_ANAU_CR_EN_VBAT_MON);
417 #else /* (GPADC_CALIB_FLOW_VERSION == 2) */
418 // TODO
419 hadc->Instance->ADC_CFG_REG1 &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_BG | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
420 #endif /* (GPADC_CALIB_FLOW_VERSION == 3) */
421 ADC_SET_MUTE(hadc);
422
423 #else /* (GPADC_CALIB_FLOW_VERSION == 1) */
424 hadc->Instance->ADC_CFG_REG1 &= (~(GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN));
425 hadc->Instance->ADC_CTRL_REG &= (~GPADC_ADC_CTRL_REG_FRC_EN_ADC);
426 #endif
427
428 /* Process unlocked */
429 __HAL_UNLOCK(hadc);
430
431 /* Return function status */
432 return tmp_hal_status;
433 }
434
435 /**
436 * @brief Wait for regular group conversion to be completed.
437 * @param hadc ADC handle
438 * @param Timeout Timeout value in millisecond.
439 * @retval HAL status
440 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)441 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
442 {
443 uint32_t tickstart;
444
445 /* Check ADC handle */
446 if (hadc == NULL)
447 {
448 return HAL_ERROR;
449 }
450
451 /* Get tick count */
452 tickstart = HAL_GetTick();
453
454 /* Wait until End of Conversion flag is raised */
455 while (HAL_IS_BIT_CLR(hadc->Instance->GPADC_IRQ, GPADC_GPADC_IRQ_GPADC_IRSR))
456 {
457 /* Check if timeout is disabled (set to infinite wait) */
458 if (Timeout != HAL_MAX_DELAY)
459 {
460 if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
461 {
462 /* Update ADC state machine to timeout */
463 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
464
465 /* Process unlocked */
466 __HAL_UNLOCK(hadc);
467
468 return HAL_TIMEOUT;
469 }
470 }
471 }
472
473 /* Clear ISR */
474 __HAL_ADC_CLEAR_FLAG(hadc, GPADC_GPADC_IRQ_GPADC_ICR);
475
476 /* Update ADC state machine */
477 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
478
479 return HAL_OK;
480 }
481
482 /**
483 * @brief Enables ADC, starts conversion of regular group with interruption.
484 * Interruptions enabled in this function:
485 * - EOC (end of conversion of regular group) or EOS (end of
486 * sequence of regular group) depending on ADC initialization
487 * parameter "EOCSelection"
488 * - overrun (if available)
489 * Each of these interruptions has its dedicated callback function.
490 * @param hadc ADC handle
491 * @retval HAL status
492 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)493 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
494 {
495 HAL_StatusTypeDef res = HAL_OK;
496
497 /* Check ADC handle */
498 if (hadc == NULL)
499 {
500 return HAL_ERROR;
501 }
502
503 res = HAL_ADC_Prepare(hadc);
504 if (res == HAL_OK)
505 {
506 __HAL_ADC_ENABLE_IRQ(hadc, GPADC_GPADC_IRQ_GPADC_IMR);
507 __HAL_ADC_START_CONV(hadc);
508 }
509
510 /* Return function status */
511 return res;
512 }
513
514
515 /**
516 * @brief Stop ADC conversion of regular group, disable interruption of
517 * end-of-conversion, disable ADC peripheral.
518 * @param hadc ADC handle
519 * @retval HAL status.
520 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)521 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
522 {
523 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
524
525 /* Process locked */
526 __HAL_LOCK(hadc);
527
528 if (hadc->Init.op_mode != 0)
529 __HAL_ADC_STOP_CONV(hadc);
530
531 __HAL_ADC_DISABLE_IRQ(hadc, GPADC_GPADC_IRQ_GPADC_IMR);
532
533 /* Process unlocked */
534 __HAL_UNLOCK(hadc);
535
536 /* Return function status */
537 return tmp_hal_status;
538 }
539
540 /**
541 * @brief Enables ADC, starts conversion of regular group and transfers result
542 * through DMA.
543 * Interruptions enabled in this function:
544 * - DMA transfer complete
545 * - DMA half transfer
546 * - overrun
547 * Each of these interruptions has its dedicated callback function.
548 * @param hadc ADC handle
549 * @param pData The destination Buffer address.
550 * @param Length The length of data to be transferred from ADC peripheral to memory.
551 * @retval None
552 */
HAL_ADC_DMA_PREPARE(ADC_HandleTypeDef * hadc)553 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_DMA_PREPARE(ADC_HandleTypeDef *hadc)
554 {
555 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
556
557 /* Perform ADC enable and conversion start if no conversion is on going */
558 #if 1
559 {
560 #if (GPADC_CALIB_FLOW_VERSION != 1)
561 #if (GPADC_CALIB_FLOW_VERSION == 3)
562 // TODO
563 hwp_hpsys_cfg->ANAU_CR |= (HPSYS_CFG_ANAU_CR_EN_VBAT_MON);
564 //hwp_hpsys_cfg->ANAU_CR |= (HPSYS_CFG_ANAU_CR_EN_BG);
565 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
566 #else
567 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_BG | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
568 #endif
569
570 #else //(GPADC_CALIB_FLOW_VERSION == 1)
571 // set LDOCORE and LDOREF enable
572 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
573 #endif
574
575 hadc->Instance->ADC_CTRL_REG |= (GPADC_ADC_CTRL_REG_FRC_EN_ADC);
576 /* Process locked */
577 __HAL_LOCK(hadc);
578
579 /* Start conversion if ADC is effectively enabled */
580 if (tmp_hal_status == HAL_OK)
581 {
582 /* Set ADC state */
583 /* - Clear state bitfield related to regular group conversion results */
584 /* - Set state bitfield related to regular operation */
585 ADC_STATE_CLR_SET(hadc->State,
586 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
587 HAL_ADC_STATE_REG_BUSY);
588
589 /* Reset ADC all error code fields */
590 ADC_CLEAR_ERRORCODE(hadc);
591 #if (GPADC_CALIB_FLOW_VERSION != 1)
592 HAL_Delay_us(200);
593 #else
594 HAL_Delay_us(50);
595 #endif
596 /* Process unlocked */
597 /* Unlock before starting ADC conversions: in case of potential */
598 /* interruption, to let the process to ADC IRQ Handler. */
599 __HAL_UNLOCK(hadc);
600
601 }
602 }
603 #endif
604
605 /* Check ADC handle */
606 if (hadc == NULL || hadc->DMA_Handle == NULL)
607 {
608 return HAL_ERROR;
609 }
610
611 /* Init DMA configure*/
612 //hadc->DMA_Handle->Instance = GPADC_DMA_INSTANCE;
613 //hadc->DMA_Handle->Init.Request = GPADC_DMA_REQUEST;
614 //hadc->DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
615 //hadc->DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
616 //hadc->DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
617 //hadc->DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
618 //hadc->DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
619 //hadc->DMA_Handle->Init.Mode = DMA_NORMAL;
620 //hadc->DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
621 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
622 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
623
624 tmp_hal_status = HAL_DMA_Init(hadc->DMA_Handle);
625 if (tmp_hal_status != HAL_OK)
626 return tmp_hal_status;
627
628 return tmp_hal_status;
629 }
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)630 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
631 {
632 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
633
634 /* Perform ADC enable and conversion start if no conversion is on going */
635 #if 0
636 {
637 #ifndef SF32LB55X
638 #ifdef SF32LB52X
639 // TODO
640 hwp_hpsys_cfg->ANAU_CR |= (HPSYS_CFG_ANAU_CR_EN_VBAT_MON);
641 //hwp_hpsys_cfg->ANAU_CR |= (HPSYS_CFG_ANAU_CR_EN_BG);
642 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
643 #else
644 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_BG | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
645 #endif /* SF32LB52X */
646
647 #else
648 // set LDOCORE and LDOREF enable
649 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
650 #endif
651
652 hadc->Instance->ADC_CTRL_REG |= (GPADC_ADC_CTRL_REG_FRC_EN_ADC);
653 /* Process locked */
654 __HAL_LOCK(hadc);
655
656 /* Start conversion if ADC is effectively enabled */
657 if (tmp_hal_status == HAL_OK)
658 {
659 /* Set ADC state */
660 /* - Clear state bitfield related to regular group conversion results */
661 /* - Set state bitfield related to regular operation */
662 ADC_STATE_CLR_SET(hadc->State,
663 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
664 HAL_ADC_STATE_REG_BUSY);
665
666 /* Reset ADC all error code fields */
667 ADC_CLEAR_ERRORCODE(hadc);
668 #ifndef SF32LB55X
669 HAL_Delay_us(200);
670 #else
671 HAL_Delay_us(50);
672 #endif
673 /* Process unlocked */
674 /* Unlock before starting ADC conversions: in case of potential */
675 /* interruption, to let the process to ADC IRQ Handler. */
676 __HAL_UNLOCK(hadc);
677 * /
678
679 }
680 }
681 #endif
682
683 /* Check ADC handle */
684 if (hadc == NULL || hadc->DMA_Handle == NULL)
685 {
686 return HAL_ERROR;
687 }
688 #if 0
689 /* Init DMA configure*/
690 hadc->DMA_Handle->Instance = GPADC_DMA_INSTANCE;
691 hadc->DMA_Handle->Init.Request = GPADC_DMA_REQUEST;
692 hadc->DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
693 hadc->DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
694 hadc->DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
695 hadc->DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
696 hadc->DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
697 hadc->DMA_Handle->Init.Mode = DMA_NORMAL;
698 hadc->DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
699 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
700 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
701
702
703 tmp_hal_status = HAL_DMA_Init(hadc->DMA_Handle);
704 if (tmp_hal_status != HAL_OK)
705 return tmp_hal_status;
706 #endif
707 ADC_DMA_ENABLE(hadc);
708 tmp_hal_status = HAL_DMA_Start(hadc->DMA_Handle, (uint32_t)(&hadc->Instance->ADC_DMA_RDATA), (uint32_t)pData, Length);
709 hadc->Instance->ADC_CTRL_REG |= GPADC_ADC_CTRL_REG_ADC_START;
710
711 /* Return function status */
712 return tmp_hal_status;
713 }
714
715 /**
716 * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
717 * ADC peripheral.
718 * Each of these interruptions has its dedicated callback function.
719 * @param hadc ADC handle
720 * @retval HAL status.
721 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)722 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
723 {
724 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
725
726 /* Process locked */
727 __HAL_LOCK(hadc);
728
729 ADC_DMA_DISABLE(hadc);
730
731 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
732
733 if (hadc->Init.op_mode != 0)
734 hadc->Instance->ADC_CTRL_REG |= GPADC_ADC_CTRL_REG_ADC_STOP;
735
736 /* Set ADC state */
737 ADC_STATE_CLR_SET(hadc->State,
738 HAL_ADC_STATE_REG_BUSY,
739 HAL_ADC_STATE_READY);
740
741 // reset LDOCORE and LDOREF enable
742 #if (GPADC_CALIB_FLOW_VERSION != 1)
743 #if (GPADC_CALIB_FLOW_VERSION == 3)
744 hadc->Instance->ADC_CFG_REG1 &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
745 //hwp_hpsys_cfg->ANAU_CR &= (~HPSYS_CFG_ANAU_CR_EN_BG);
746 hwp_hpsys_cfg->ANAU_CR &= (~HPSYS_CFG_ANAU_CR_EN_VBAT_MON);
747 #else
748 // TODO
749 hadc->Instance->ADC_CFG_REG1 &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_BG | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
750 #endif
751 #else
752 hadc->Instance->ADC_CFG_REG1 &= (~(GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN));
753 #endif
754 hadc->Instance->ADC_CTRL_REG &= (~GPADC_ADC_CTRL_REG_FRC_EN_ADC);
755
756
757 /* Process unlocked */
758 __HAL_UNLOCK(hadc);
759
760 /* Return function status */
761 return tmp_hal_status;
762 }
763
HAL_ADC_DMA_WAIT_DONE(ADC_HandleTypeDef * hadc,uint32_t timeout)764 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_DMA_WAIT_DONE(ADC_HandleTypeDef *hadc, uint32_t timeout)
765 {
766 HAL_StatusTypeDef res = HAL_OK;
767
768 if ((hadc == NULL) || (hadc->DMA_Handle == NULL))
769 return HAL_ERROR;
770
771 res = HAL_DMA_PollForTransfer(hadc->DMA_Handle, HAL_DMA_FULL_TRANSFER, timeout);
772
773 ADC_DMA_DISABLE(hadc);
774
775 return res;
776 }
777
778
779 /**
780 * @brief Get ADC regular group conversion result.
781 * @note Reading register DR automatically clears ADC flag EOC
782 * (ADC group regular end of unitary conversion).
783 * @note This function does not clear ADC flag EOS
784 * (ADC group regular end of sequence conversion).
785 * Occurrence of flag EOS rising:
786 * - If sequencer is composed of 1 rank, flag EOS is equivalent
787 * to flag EOC.
788 * - If sequencer is composed of several ranks, during the scan
789 * sequence flag EOC only is raised, at the end of the scan sequence
790 * both flags EOC and EOS are raised.
791 * To clear this flag, either use function:
792 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
793 * model polling: @ref HAL_ADC_PollForConversion()
794 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
795 * @param hadc ADC handle
796 * @retval ADC group regular conversion data
797 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc,uint32_t slot)798 __HAL_ROM_USED uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc, uint32_t slot)
799 {
800 uint32_t value, odd;
801 __IO uint32_t *p = &(hadc->Instance->ADC_RDATA0);
802
803 /* Check ADC handle */
804 if (hadc == NULL || slot >= 8)
805 {
806 return HAL_ERROR;
807 }
808 odd = 0;
809
810 if (hadc->Init.en_slot == 1)
811 {
812 p += slot / 2;
813 odd = slot % 2;
814 }
815 value = *p;
816
817 if (odd)
818 value = (value & GPADC_ADC_RDATA0_SLOT1_RDATA_Msk) >> GPADC_ADC_RDATA0_SLOT1_RDATA_Pos;
819 else
820 value = value & GPADC_ADC_RDATA0_SLOT0_RDATA_Msk;
821
822 /* Return ADC converted value */
823 return value;
824 }
825
HAL_ADC_Get_All(ADC_HandleTypeDef * hadc,uint32_t * buf)826 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Get_All(ADC_HandleTypeDef *hadc, uint32_t *buf)
827 {
828 int i;
829 __IO uint32_t *p = &(hadc->Instance->ADC_RDATA0);
830 uint32_t *data = (uint32_t *)buf;
831
832 /* Check ADC handle */
833 if (hadc == NULL || buf == NULL)
834 return HAL_ERROR;
835
836 for (i = 0; i < 8; i++)
837 {
838 if (i & 1)
839 {
840 *data = (*p & GPADC_ADC_RDATA0_SLOT1_RDATA_Msk) >> GPADC_ADC_RDATA0_SLOT1_RDATA_Pos;
841 p++;
842 }
843 else
844 *data = *p & GPADC_ADC_RDATA0_SLOT0_RDATA_Msk;
845 data++;
846 }
847
848 return HAL_OK;
849 }
850
851
HAL_ADC_SetSource(ADC_HandleTypeDef * hadc,HAL_ADC_SRC__T src)852 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_SetSource(ADC_HandleTypeDef *hadc, HAL_ADC_SRC__T src)
853 {
854 if (hadc == NULL || src > HAL_ADC_SRC_TIMER)
855 {
856 return HAL_ERROR;
857 }
858
859 hadc->Instance->ADC_CTRL_REG |= (src << GPADC_ADC_CTRL_REG_GPIO_TRIG_EN_Pos);
860
861 return HAL_OK;
862 }
863
HAL_ADC_SetTimer(ADC_HandleTypeDef * hadc,HAL_ADC_SRC_TIME_T src)864 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_SetTimer(ADC_HandleTypeDef *hadc, HAL_ADC_SRC_TIME_T src)
865 {
866 if (hadc == NULL || src >= HAL_ADC_SRC_TIMER_CNT)
867 {
868 return HAL_ERROR;
869 }
870
871 hadc->Instance->ADC_CTRL_REG |= (src << GPADC_ADC_CTRL_REG_TIMER_TRIG_SRC_SEL_Pos);
872
873 return HAL_OK;
874 }
875
876
877 /**
878 * @brief Handles ADC interrupt request.
879 * @param hadc ADC handle
880 * @retval None
881 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)882 __HAL_ROM_USED void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
883 {
884 if(__HAL_ADC_GET_FLAG(hadc, GPADC_GPADC_IRQ_GPADC_IRSR))
885 HAL_ADC_ConvCpltCallback(hadc);
886
887 /* Clear ISR */
888 __HAL_ADC_CLEAR_FLAG(hadc, GPADC_GPADC_IRQ_GPADC_ICR);
889
890 /* Set status */
891 SET_BIT(hadc->State, HAL_ADC_START_IRQ_DONE);
892 }
893
894 /**
895 * @brief Conversion complete callback in non blocking mode
896 * @param hadc ADC handle
897 * @retval None
898 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)899 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
900 {
901 /* Prevent unused argument(s) compilation warning */
902 UNUSED(hadc);
903
904 /* NOTE : This function should not be modified. When the callback is needed,
905 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
906 */
907 }
908
909
910 /**
911 * @}
912 */
913
914 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
915 * @brief Peripheral Control functions
916 *
917 @verbatim
918 ===============================================================================
919 ##### Peripheral Control functions #####
920 ===============================================================================
921 [..] This section provides functions allowing to:
922 (+) Configure channels on regular group
923 (+) Configure the analog watchdog
924
925 @endverbatim
926 * @{
927 */
928
929 /**
930 * @brief Configures the the selected channel to be linked to the regular
931 * group.
932 * @note In case of usage of internal measurement channels:
933 * VrefInt/Vbat/TempSensor.
934 * Sampling time constraints must be respected (sampling time can be
935 * adjusted in function of ADC clock frequency and sampling time
936 * setting).
937 * Refer to device datasheet for timings values, parameters TS_vrefint,
938 * TS_vbat, TS_temp (values rough order: 5us to 17us).
939 * These internal paths can be be disabled using function
940 * HAL_ADC_DeInit().
941 * @note Possibility to update parameters on the fly:
942 * This function initializes channel into regular group, following
943 * calls to this function can be used to reconfigure some parameters
944 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
945 * the ADC.
946 * The setting of these parameters is conditioned to ADC state.
947 * For parameters constraints, see comments of structure
948 * "ADC_ChannelConfTypeDef".
949 * @param hadc ADC handle
950 * @param sConfig Structure of ADC channel for regular group.
951 * @retval HAL status
952 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)953 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
954 {
955 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
956 uint32_t value = 0;
957 __IO uint32_t *p = &(hadc->Instance->ADC_SLOT0_REG);
958
959 /* Check ADC handle */
960 if (hadc == NULL || sConfig == NULL || sConfig->Channel >= 8)
961 {
962 return HAL_ERROR;
963 }
964
965 /* Process locked */
966 __HAL_LOCK(hadc);
967
968 if (hadc->Init.en_slot == 1)
969 p += sConfig->Channel;
970
971 value = *p;
972
973 value &= ~(GPADC_ADC_SLOT0_REG_NCHNL_SEL | GPADC_ADC_SLOT0_REG_PCHNL_SEL | GPADC_ADC_SLOT0_REG_ACC_NUM);
974 value |= ((sConfig->nchnl_sel << GPADC_ADC_SLOT0_REG_NCHNL_SEL_Pos) & GPADC_ADC_SLOT0_REG_NCHNL_SEL_Msk)
975 | ((sConfig->pchnl_sel << GPADC_ADC_SLOT0_REG_PCHNL_SEL_Pos) & GPADC_ADC_SLOT0_REG_PCHNL_SEL_Msk)
976 | ((sConfig->acc_num << GPADC_ADC_SLOT0_REG_ACC_NUM_Pos) & GPADC_ADC_SLOT0_REG_ACC_NUM_Msk);
977
978
979 if (sConfig->slot_en)
980 {
981 value |= GPADC_ADC_SLOT0_REG_SLOT_EN;
982 }
983 else
984 {
985 value &= ~GPADC_ADC_SLOT0_REG_SLOT_EN;
986 }
987
988 *p = value;
989
990 /* Process unlocked */
991 __HAL_UNLOCK(hadc);
992
993 /* Return function status */
994 return tmp_hal_status;
995 }
996
997 /**
998 * @brief Set ADC sampling frequency.
999 * @param hadc ADC handle.
1000 * @param freq frequence want to be set.
1001 * @retval actual work frequency, 0 if fail.
1002 */
HAL_ADC_SetFreq(ADC_HandleTypeDef * hadc,uint32_t freq)1003 __HAL_ROM_USED uint32_t HAL_ADC_SetFreq(ADC_HandleTypeDef *hadc, uint32_t freq)
1004 {
1005 uint32_t fpclk; // = HAL_RCC_GetPCLKFreq(CORE_ID_LCPU, 1);
1006 uint32_t div; // = fpclk / freq;
1007
1008 if (freq == 0)
1009 return 0;
1010
1011 //extern void rt_kprintf(const char *fmt, ...);
1012 #if (GPADC_CALIB_FLOW_VERSION != 3)
1013 fpclk = HAL_RCC_GetPCLKFreq(CORE_ID_LCPU, 1);
1014 div = fpclk / freq;
1015 #else
1016 fpclk = HAL_RCC_GetPCLKFreq(CORE_ID_HCPU, 1);
1017 div = fpclk / freq;
1018 #endif
1019 //for single triger mode, init time will effect adc frequency, init time only work once after strt
1020 //int init_time = (hadc->Instance->ADC_CTRL_REG & GPADC_ADC_CTRL_REG_INIT_TIME_Msk)>>GPADC_ADC_CTRL_REG_INIT_TIME_Pos;
1021 //div = fpclk / (freq * (1+init_time));
1022 #if (GPADC_CALIB_FLOW_VERSION != 1)
1023 uint32_t min_conv, min_samp, data_dly;
1024 uint32_t max_conv, max_samp;
1025
1026 max_conv = GPADC_ADC_CTRL_REG2_CONV_WIDTH >> GPADC_ADC_CTRL_REG2_CONV_WIDTH_Pos;
1027 max_samp = GPADC_ADC_CTRL_REG2_SAMP_WIDTH >> GPADC_ADC_CTRL_REG2_SAMP_WIDTH_Pos;
1028 #if (GPADC_CALIB_FLOW_VERSION == 3)
1029 uint32_t std_conv, std_samp, std_dly, std_freq;
1030 std_conv = 76;
1031 std_samp = 74;
1032 std_dly = 2;
1033 std_freq = 36000000; // same to ATE
1034 std_freq /= 1000; // to avoid over range for u32
1035 fpclk /= 1000; // to avoid over range for u32
1036 min_conv = (std_conv * fpclk + std_freq / 2) / std_freq - 1;
1037 data_dly = (std_dly * fpclk + std_freq / 2) / std_freq;
1038 min_samp = (std_samp * fpclk + std_freq / 2) / std_freq - data_dly - 1;
1039 if ((min_conv > max_conv) || (min_samp > max_samp)) // over rage
1040 HAL_ASSERT(0);
1041 #else
1042 min_conv = 24;
1043 min_samp = 22;
1044 data_dly = 2;
1045
1046 //cnt = min_conv + min_samp + data_dly + 2;
1047 if ((div <= max_conv * 2) && (div <= max_samp * 2)) // have enough clock
1048 {
1049 min_conv = div / 2;
1050 data_dly = 2;
1051 min_samp = min_conv - data_dly - 2;
1052 }
1053 else // not support
1054 return 0;
1055 #endif
1056
1057 //sampel rate too high, not support, set to max freq
1058 hadc->Init.data_samp_delay = data_dly;
1059 hadc->Init.conv_width = min_conv;
1060 hadc->Init.sample_width = min_samp;
1061
1062 __HAL_ADC_SET_SAMPLE_WIDTH(hadc, hadc->Init.sample_width);
1063 __HAL_ADC_SET_CONV_WIDTH(hadc, hadc->Init.conv_width);
1064 __HAL_ADC_SET_DATA_DELAY(hadc, hadc->Init.data_samp_delay);
1065 //rt_kprintf("src freq %d, div %d, data_samp_delay %d, conv_width %d, sample_width %d\n", fpclk, div, data_dly, min_conv, min_samp);
1066 #else
1067 uint32_t maxdiv;
1068 maxdiv = GPADC_ADC_CTRL_REG_ADC_CLK_DIV >> GPADC_ADC_CTRL_REG_ADC_CLK_DIV_Pos;
1069 maxdiv = maxdiv + 1; // divider + 1
1070
1071 if (div > maxdiv)
1072 div = maxdiv;
1073 if (div < 1)
1074 div = 1;
1075 hadc->Init.clk_div = div - 1;
1076 __HAL_ADC_SET_CLOCK_DIV(hadc, hadc->Init.clk_div);
1077 #endif
1078 return fpclk / div;
1079 }
1080
HAL_ADC_EnableSlot(ADC_HandleTypeDef * hadc,uint32_t slot,uint8_t en)1081 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_EnableSlot(ADC_HandleTypeDef *hadc, uint32_t slot, uint8_t en)
1082 {
1083 __IO uint32_t *p = &(hadc->Instance->ADC_SLOT0_REG);
1084
1085 /* Check ADC handle */
1086 if (hadc == NULL || slot >= 8)
1087 {
1088 return HAL_ERROR;
1089 }
1090 if (hadc->Init.en_slot == 1)
1091 p += slot;
1092
1093 // Clear these bit, disable
1094 //*p &= (~GPADC_ADC_SLOT0_REG_SLOT_EN);
1095 //*p &= (~GPADC_ADC_SLOT0_REG_ACC_NUM);
1096
1097 if (en != 0)
1098 {
1099 *p |= GPADC_ADC_SLOT0_REG_SLOT_EN;
1100 //*p |= (3 << GPADC_ADC_SLOT0_REG_ACC_NUM_Pos);
1101 }
1102 else
1103 {
1104 *p &= (~GPADC_ADC_SLOT0_REG_SLOT_EN);
1105 }
1106
1107 return HAL_OK;
1108 }
1109
HAL_ADC_Set_MultiMode(ADC_HandleTypeDef * hadc,uint8_t multi_mode)1110 __HAL_ROM_USED HAL_StatusTypeDef HAL_ADC_Set_MultiMode(ADC_HandleTypeDef *hadc, uint8_t multi_mode)
1111 {
1112 if (hadc == NULL)
1113 return HAL_ERROR;
1114
1115 if (multi_mode)
1116 hadc->Init.en_slot = 1;
1117 else
1118 hadc->Init.en_slot = 0;
1119
1120 return HAL_OK;
1121 }
1122
1123
HAL_ADC_Get_Offset(ADC_HandleTypeDef * hadc)1124 __HAL_ROM_USED int HAL_ADC_Get_Offset(ADC_HandleTypeDef *hadc)
1125 {
1126 int offset;
1127
1128 #if (GPADC_CALIB_FLOW_VERSION != 1)
1129 #if (GPADC_CALIB_FLOW_VERSION == 3)
1130 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
1131 #else
1132 // TODO
1133 hadc->Instance->ADC_CFG_REG1 |= (GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_BG | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
1134 #endif
1135 #else
1136
1137 hadc->Instance->ADC_CFG_REG1 |= GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN;
1138
1139 hadc->Instance->ADC_CFG_REG1 |= GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN;
1140 #endif
1141 //hadc->Instance->ADC_CFG_REG1 |= GPADC_ADC_CFG_REG1_ANAU_GPADC_SE;
1142 hadc->Instance->ADC_CFG_REG1 |= GPADC_ADC_CFG_REG1_ANAU_GPADC_MUTE;
1143
1144 hadc->Instance->ADC_SLOT0_REG &= (~GPADC_ADC_SLOT0_REG_ACC_NUM);
1145 hadc->Instance->ADC_SLOT0_REG |= (3 << GPADC_ADC_SLOT0_REG_ACC_NUM_Pos);
1146
1147 HAL_Delay_us(50);
1148 hadc->Instance->ADC_CTRL_REG |= GPADC_ADC_CTRL_REG_ADC_START;
1149 while (!(hadc->Instance->GPADC_IRQ & GPADC_GPADC_IRQ_GPADC_IRSR_Msk));
1150
1151 offset = hadc->Instance->ADC_RDATA0 & GPADC_ADC_RDATA0_SLOT0_RDATA_Msk;
1152
1153 hadc->Instance->GPADC_IRQ |= GPADC_GPADC_IRQ_GPADC_ICR;
1154
1155
1156 #if (GPADC_CALIB_FLOW_VERSION != 1)
1157 #if (GPADC_CALIB_FLOW_VERSION == 3)
1158 hadc->Instance->ADC_CFG_REG1 &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
1159 #else
1160 // TODO
1161 hadc->Instance->ADC_CFG_REG1 &= ~(GPADC_ADC_CFG_REG1_ANAU_GPADC_EN_BG | GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN);
1162 #endif
1163 #else
1164 hadc->Instance->ADC_CFG_REG1 &= ~GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOREF_EN;
1165 hadc->Instance->ADC_CFG_REG1 &= ~GPADC_ADC_CFG_REG1_ANAU_GPADC_LDOCORE_EN;
1166 #endif
1167 hadc->Instance->ADC_CFG_REG1 &= ~GPADC_ADC_CFG_REG1_ANAU_GPADC_MUTE;
1168
1169 return offset - 512;
1170 }
1171
1172 /**
1173 * @}
1174 */
1175
1176
1177 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
1178 * @brief Peripheral State functions
1179 *
1180 @verbatim
1181 ===============================================================================
1182 ##### Peripheral State and Errors functions #####
1183 ===============================================================================
1184 [..]
1185 This subsection provides functions to get in run-time the status of the
1186 peripheral.
1187 (+) Check the ADC state
1188 (+) Check the ADC error code
1189
1190 @endverbatim
1191 * @{
1192 */
1193
1194 /**
1195 * @brief Return the ADC state
1196 * @note ADC state machine is managed by bitfields, ADC status must be
1197 * compared with states bits.
1198 * For example:
1199 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
1200 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
1201 * @param hadc ADC handle
1202 * @retval HAL state
1203 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)1204 __HAL_ROM_USED uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
1205 {
1206 /* Return ADC state */
1207 return hadc->State;
1208 }
1209
1210 /**
1211 * @brief Return the ADC error code
1212 * @param hadc ADC handle
1213 * @retval ADC Error Code
1214 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)1215 __HAL_ROM_USED uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1216 {
1217 return hadc->ErrorCode;
1218 }
1219
1220 /**
1221 * @brief Initialize the ADC MSP.
1222 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1223 * the configuration information for ADC module.
1224 * @retval None
1225 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)1226 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
1227 {
1228 /* Prevent unused argument(s) compilation warning */
1229 UNUSED(hadc);
1230
1231 /* NOTE : This function should not be modified, when the callback is needed,
1232 the HAL_ADC_MspInit should be implemented in the user file
1233 */
1234 }
1235
1236 /**
1237 * @brief De-Initialize the ADC MSP.
1238 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1239 * the configuration information for ADC module.
1240 * @retval None
1241 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)1242 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
1243 {
1244 /* Prevent unused argument(s) compilation warning */
1245 UNUSED(hadc);
1246
1247 /* NOTE : This function should not be modified, when the callback is needed,
1248 the HAL_ADC_MspDeInit should be implemented in the user file
1249 */
1250 }
1251
1252 /**
1253 * @}
1254 */
1255
1256 /**
1257 * @}
1258 */
1259
1260 /** @defgroup ADC_Private_Functions ADC Private Functions
1261 * @{
1262 */
1263
1264
1265 /**
1266 * @brief DMA transfer complete callback.
1267 * @param hdma pointer to DMA handle.
1268 * @retval None
1269 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)1270 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1271 {
1272 /* Retrieve ADC handle corresponding to current DMA handle */
1273 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1274
1275 /* Update state machine on conversion status if not in error state */
1276 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
1277 {
1278 /* Set ADC state */
1279 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1280
1281 /* Conversion complete callback */
1282 HAL_ADC_ConvCpltCallback(hadc);
1283 }
1284 else
1285 {
1286 /* Call DMA error callback */
1287 hadc->DMA_Handle->XferErrorCallback(hdma);
1288 }
1289
1290 }
1291
1292 /**
1293 * @brief DMA error callback
1294 * @param hdma pointer to DMA handle.
1295 * @retval None
1296 */
ADC_DMAError(DMA_HandleTypeDef * hdma)1297 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
1298 {
1299 /* Retrieve ADC handle corresponding to current DMA handle */
1300 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1301
1302 /* Set ADC state */
1303 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1304
1305 /* Set ADC error code to DMA error */
1306 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
1307
1308 }
1309
1310 /**
1311 * @}
1312 */
1313
1314 #endif /* HAL_ADC_MODULE_ENABLED */
1315 /**
1316 * @}
1317 */
1318
1319 /**
1320 * @}
1321 */
