1 /* 2 * SPDX-FileCopyrightText: 2016 STMicroelectronics 3 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd 4 * 5 * SPDX-License-Identifier: BSD-3-Clause AND Apache-2.0 6 */ 7 8 #ifndef __BF0_HAL_GPT_H 9 #define __BF0_HAL_GPT_H 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /* Includes ------------------------------------------------------------------*/ 16 #include "bf0_hal_def.h" 17 18 /** @addtogroup BF0_HAL_Driver 19 * @{ 20 */ 21 22 /** @addtogroup TIM Hardware Timer 23 * @{ 24 */ 25 26 /* Exported types ------------------------------------------------------------*/ 27 /** @defgroup GPT_Exported_Types TIM Exported Types 28 * @{ 29 */ 30 31 /** 32 * @brief TIM Time base Configuration Structure definition 33 */ 34 typedef struct 35 { 36 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 37 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ 38 39 uint32_t CounterMode; /*!< Specifies the counter mode. 40 This parameter can be a value of @ref GPT_Counter_Mode */ 41 42 uint32_t Period; /*!< Specifies the period value to be loaded into the active 43 Auto-Reload Register at the next update event. 44 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */ 45 46 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 47 reaches zero, an update event is generated and counting restarts 48 from the RCR value (N). 49 This means in PWM mode that (N+1) corresponds to: 50 - the number of PWM periods in edge-aligned mode 51 - the number of half PWM period in center-aligned mode 52 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 53 @note This parameter is valid only for TIM1 and TIM8. */ 54 } GPT_Base_InitTypeDef; 55 56 /** 57 * @brief TIM Output Compare Configuration Structure definition 58 */ 59 60 typedef struct 61 { 62 uint32_t OCMode; /*!< Specifies the TIM mode. 63 This parameter can be a value of @ref GPT_Output_Compare_and_PWM_modes */ 64 65 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 66 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ 67 68 uint32_t OCPolarity; /*!< Specifies the output polarity. 69 This parameter can be a value of @ref GPT_Output_Compare_Polarity */ 70 71 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 72 This parameter can be a value of @ref GPT_Output_Compare_N_Polarity 73 @note This parameter is valid only for TIM1 and TIM8. */ 74 75 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 76 This parameter can be a value of @ref GPT_Output_Fast_State 77 @note This parameter is valid only in PWM1 and PWM2 mode. */ 78 79 80 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 81 This parameter can be a value of @ref GPT_Output_Compare_Idle_State 82 @note This parameter is valid only for TIM1 and TIM8. */ 83 84 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 85 This parameter can be a value of @ref GPT_Output_Compare_N_Idle_State 86 @note This parameter is valid only for TIM1 and TIM8. */ 87 } GPT_OC_InitTypeDef; 88 89 /** 90 * @brief TIM One Pulse Mode Configuration Structure definition 91 */ 92 typedef struct 93 { 94 uint32_t OCMode; /*!< Specifies the TIM mode. 95 This parameter can be a value of @ref GPT_Output_Compare_and_PWM_modes */ 96 97 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 98 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ 99 100 uint32_t OCPolarity; /*!< Specifies the output polarity. 101 This parameter can be a value of @ref GPT_Output_Compare_Polarity */ 102 103 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 104 This parameter can be a value of @ref GPT_Output_Compare_N_Polarity 105 @note This parameter is valid only for TIM1 and TIM8. */ 106 107 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 108 This parameter can be a value of @ref GPT_Output_Compare_Idle_State 109 @note This parameter is valid only for TIM1 and TIM8. */ 110 111 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 112 This parameter can be a value of @ref GPT_Output_Compare_N_Idle_State 113 @note This parameter is valid only for TIM1 and TIM8. */ 114 115 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 116 This parameter can be a value of @ref GPT_Input_Capture_Polarity */ 117 118 uint32_t ICSelection; /*!< Specifies the input. 119 This parameter can be a value of @ref GPT_Input_Capture_Selection */ 120 121 uint32_t ICFilter; /*!< Specifies the input capture filter. 122 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 123 } GPT_OnePulse_InitTypeDef; 124 125 126 /** 127 * @brief TIM Input Capture Configuration Structure definition 128 */ 129 130 typedef struct 131 { 132 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 133 This parameter can be a value of @ref GPT_Input_Capture_Polarity */ 134 135 uint32_t ICSelection; /*!< Specifies the input. 136 This parameter can be a value of @ref GPT_Input_Capture_Selection */ 137 138 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 139 This parameter can be a value of @ref GPT_Input_Capture_Prescaler */ 140 141 uint32_t ICFilter; /*!< Specifies the input capture filter. 142 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 143 } GPT_IC_InitTypeDef; 144 145 /** 146 * @brief TIM Encoder Configuration Structure definition 147 */ 148 149 typedef struct 150 { 151 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 152 This parameter can be a value of @ref GPT_Encoder_Mode */ 153 154 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 155 This parameter can be a value of @ref GPT_Input_Capture_Polarity */ 156 157 uint32_t IC1Selection; /*!< Specifies the input. 158 This parameter can be a value of @ref GPT_Input_Capture_Selection */ 159 160 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 161 This parameter can be a value of @ref GPT_Input_Capture_Prescaler */ 162 163 uint32_t IC1Filter; /*!< Specifies the input capture filter. 164 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 165 166 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 167 This parameter can be a value of @ref GPT_Input_Capture_Polarity */ 168 169 uint32_t IC2Selection; /*!< Specifies the input. 170 This parameter can be a value of @ref GPT_Input_Capture_Selection */ 171 172 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 173 This parameter can be a value of @ref GPT_Input_Capture_Prescaler */ 174 175 uint32_t IC2Filter; /*!< Specifies the input capture filter. 176 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 177 } GPT_Encoder_InitTypeDef; 178 179 /** 180 * @brief Clock Configuration Handle Structure definition 181 */ 182 typedef struct 183 { 184 uint32_t ClockSource; /*!< TIM clock sources. 185 This parameter can be a value of @ref GPT_Clock_Source */ 186 uint32_t ClockPolarity; /*!< TIM clock polarity. 187 This parameter can be a value of @ref GPT_Clock_Polarity */ 188 uint32_t ClockPrescaler; /*!< TIM clock prescaler. 189 This parameter can be a value of @ref GPT_Clock_Prescaler */ 190 uint32_t ClockFilter; /*!< TIM clock filter. 191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 192 } GPT_ClockConfigTypeDef; 193 194 /** 195 * @brief Clear Input Configuration Handle Structure definition 196 */ 197 typedef struct 198 { 199 uint32_t ClearInputState; /*!< TIM clear Input state. 200 This parameter can be ENABLE or DISABLE */ 201 uint32_t ClearInputSource; /*!< TIM clear Input sources. 202 This parameter can be a value of @ref GPT_ClearInput_Source */ 203 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. 204 This parameter can be a value of @ref GPT_ClearInput_Polarity */ 205 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. 206 This parameter can be a value of @ref GPT_ClearInput_Prescaler */ 207 uint32_t ClearInputFilter; /*!< TIM Clear Input filter. 208 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 209 } GPT_ClearInputConfigTypeDef; 210 211 /** 212 * @brief TIM Slave configuration Structure definition 213 */ 214 typedef struct 215 { 216 uint32_t SlaveMode; /*!< Slave mode selection 217 This parameter can be a value of @ref GPT_Slave_Mode */ 218 uint32_t InputTrigger; /*!< Input Trigger source 219 This parameter can be a value of @ref GPT_Trigger_Selection */ 220 uint32_t TriggerPolarity; /*!< Input Trigger polarity 221 This parameter can be a value of @ref GPT_Trigger_Polarity */ 222 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 223 This parameter can be a value of @ref GPT_Trigger_Prescaler */ 224 uint32_t TriggerFilter; /*!< Input trigger filter 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 226 227 } GPT_SlaveConfigTypeDef; 228 229 /** 230 * @brief HAL State structures definition 231 */ 232 typedef enum 233 { 234 HAL_GPT_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 235 HAL_GPT_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 236 HAL_GPT_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 237 HAL_GPT_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 238 HAL_GPT_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 239 } HAL_GPT_StateTypeDef; 240 241 /** 242 * @brief HAL Active channel structures definition 243 */ 244 typedef enum 245 { 246 HAL_GPT_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 247 HAL_GPT_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 248 HAL_GPT_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 249 HAL_GPT_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 250 HAL_GPT_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 251 } HAL_GPT_ActiveChannel; 252 253 254 /** 255 * @brief DMA Burst States definition 256 */ 257 typedef enum 258 { 259 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 260 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 261 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 262 } HAL_GPT_DMABurstStateTypeDef; 263 264 /** 265 * @brief TIM Channel States definition 266 */ 267 typedef enum 268 { 269 HAL_GPT_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 270 HAL_GPT_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 271 HAL_GPT_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 272 } HAL_GPT_ChannelStateTypeDef; 273 274 /** 275 * @brief TIM Time Base Handle Structure definition 276 */ 277 typedef struct 278 { 279 GPT_TypeDef *Instance; /*!< Register base address */ 280 GPT_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 281 HAL_GPT_ActiveChannel Channel; /*!< Active channel */ 282 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 283 This array is accessed by a @ref DMA_Handle_index */ 284 HAL_LockTypeDef Lock; /*!< Locking object */ 285 uint8_t core; /*!< Clock source from which core*/ 286 __IO HAL_GPT_StateTypeDef State; /*!< TIM operation state */ 287 #ifdef HAL_ATIM_MODULE_ENABLED 288 __IO HAL_GPT_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 289 __IO HAL_GPT_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 290 __IO HAL_GPT_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 291 #endif 292 } GPT_HandleTypeDef; 293 294 295 /** 296 * @} 297 */ 298 299 /* Exported constants --------------------------------------------------------*/ 300 /** @defgroup GPT_Exported_Constants TIM Exported Constants 301 * @{ 302 */ 303 304 /** @defgroup GPT_Input_Channel_Polarity TIM Input Channel Polarity 305 * @{ 306 */ 307 #define GPT_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 308 #define GPT_INPUTCHANNELPOLARITY_FALLING (GPT_CCER_CC1P) /*!< Polarity for TIx source */ 309 #define GPT_INPUTCHANNELPOLARITY_BOTHEDGE (GPT_CCER_CC1P | GPT_CCER_CC1NP) /*!< Polarity for TIx source */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup GPT_ETR_Polarity TIM ETR Polarity 315 * @{ 316 */ 317 #define GPT_ETRPOLARITY_INVERTED (GPT_SMCR_ETP) /*!< Polarity for ETR source */ 318 #define GPT_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 319 /** 320 * @} 321 */ 322 323 /** @defgroup GPT_ETR_Prescaler TIM ETR Prescaler 324 * @{ 325 */ 326 #define GPT_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 327 #define GPT_ETRPRESCALER_DIV2 (GPT_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ 328 #define GPT_ETRPRESCALER_DIV4 (GPT_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ 329 #define GPT_ETRPRESCALER_DIV8 (GPT_SMCR_ETPS) /*!< ETR input source is divided by 8 */ 330 /** 331 * @} 332 */ 333 334 /** @defgroup GPT_Counter_Mode TIM Counter Mode 335 * @{ 336 */ 337 #define GPT_COUNTERMODE_UP 0x00000000U 338 #define GPT_COUNTERMODE_DOWN GPT_CR1_DIR 339 #define GPT_COUNTERMODE_CENTERALIGNED3 GPT_CR1_CMS 340 /** 341 * @} 342 */ 343 344 345 /** @defgroup GPT_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes 346 * @{ 347 */ 348 #define GPT_OCMODE_TIMING 0x00000000U 349 #define GPT_OCMODE_ACTIVE (GPT_CCMR1_OC1M_0) 350 #define GPT_OCMODE_INACTIVE (GPT_CCMR1_OC1M_1) 351 #define GPT_OCMODE_TOGGLE (GPT_CCMR1_OC1M_0 | GPT_CCMR1_OC1M_1) 352 #define GPT_OCMODE_PWM1 (GPT_CCMR1_OC1M_1 | GPT_CCMR1_OC1M_2) 353 #define GPT_OCMODE_PWM2 (GPT_CCMR1_OC1M) 354 #define GPT_OCMODE_FORCED_ACTIVE (GPT_CCMR1_OC1M_0 | GPT_CCMR1_OC1M_2) 355 #define GPT_OCMODE_FORCED_INACTIVE (GPT_CCMR1_OC1M_2) 356 357 /** 358 * @} 359 */ 360 361 /** @defgroup TIM_Channel TIM Channel 362 * @{ 363 */ 364 #define TIM_CHANNEL_1 0x00000000U 365 #define TIM_CHANNEL_2 0x00000004U 366 #define TIM_CHANNEL_3 0x00000008U 367 #define TIM_CHANNEL_4 0x0000000CU 368 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 369 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 370 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 371 /** 372 * @} 373 */ 374 375 376 /** @defgroup GPT_Output_Fast_State TIM Output Fast State 377 * @{ 378 */ 379 #define GPT_OCFAST_DISABLE 0x00000000U 380 #define GPT_OCFAST_ENABLE (GPT_CCMR1_OC1FE) 381 /** 382 * @} 383 */ 384 385 /** @defgroup GPT_Output_Compare_Polarity TIM Output Compare Polarity 386 * @{ 387 */ 388 #define GPT_OCPOLARITY_HIGH 0x00000000U 389 #define GPT_OCPOLARITY_LOW (GPT_CCER_CC1P) 390 /** 391 * @} 392 */ 393 394 /** @defgroup GPT_Output_Compare_N_Polarity TIM Output CompareN Polarity 395 * @{ 396 */ 397 #define GPT_OCNPOLARITY_HIGH 0x00000000U 398 #define GPT_OCNPOLARITY_LOW (GPT_CCER_CC1NP) 399 /** 400 * @} 401 */ 402 403 /** @defgroup GPT_Output_Compare_Idle_State TIM Output Compare Idle State 404 * @{ 405 */ 406 #define GPT_OCIDLESTATE_SET (GPT_CR2_OIS1) 407 #define GPT_OCIDLESTATE_RESET 0x00000000U 408 /** 409 * @} 410 */ 411 412 /** @defgroup GPT_Output_Compare_N_Idle_State TIM Output Compare N Idle State 413 * @{ 414 */ 415 #define GPT_OCNIDLESTATE_SET (GPT_CR2_OIS1N) 416 #define GPT_OCNIDLESTATE_RESET 0x00000000U 417 /** 418 * @} 419 */ 420 421 422 /** @defgroup GPT_Channel TIM Channel 423 * @{ 424 */ 425 #define GPT_CHANNEL_1 0x00000000U 426 #define GPT_CHANNEL_2 0x00000004U 427 #define GPT_CHANNEL_3 0x00000008U 428 #define GPT_CHANNEL_4 0x0000000CU 429 #define GPT_CHANNEL_ALL 0x00000018U 430 431 /** 432 * @} 433 */ 434 435 /** @defgroup GPT_Input_Capture_Polarity TIM Input Capture Polarity 436 * @{ 437 */ 438 #define GPT_ICPOLARITY_RISING GPT_INPUTCHANNELPOLARITY_RISING 439 #define GPT_ICPOLARITY_FALLING GPT_INPUTCHANNELPOLARITY_FALLING 440 #define GPT_ICPOLARITY_BOTHEDGE GPT_INPUTCHANNELPOLARITY_BOTHEDGE 441 /** 442 * @} 443 */ 444 445 /** @defgroup GPT_Input_Capture_Selection TIM Input Capture Selection 446 * @{ 447 */ 448 #define GPT_ICSELECTION_DIRECTTI (GPT_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be 449 connected to IC1, IC2, IC3 or IC4, respectively */ 450 #define GPT_ICSELECTION_INDIRECTTI (GPT_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be 451 connected to IC2, IC1, IC4 or IC3, respectively */ 452 #define GPT_ICSELECTION_TRC (GPT_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 453 454 /** 455 * @} 456 */ 457 458 /** @defgroup GPT_Input_Capture_Prescaler TIM Input Capture Prescaler 459 * @{ 460 */ 461 #define GPT_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 462 #define GPT_ICPSC_DIV2 (1<<GPT_CCMR1_IC1PSC_Pos) /*!< Capture performed once every 2 events */ 463 #define GPT_ICPSC_DIV4 (2<<GPT_CCMR1_IC1PSC_Pos) /*!< Capture performed once every 4 events */ 464 #define GPT_ICPSC_DIV8 (GPT_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ 465 /** 466 * @} 467 */ 468 469 /** @defgroup GPT_One_Pulse_Mode TIM One Pulse Mode 470 * @{ 471 */ 472 #define GPT_OPMODE_SINGLE (GPT_CR1_OPM) 473 #define GPT_OPMODE_REPETITIVE 0x00000000U 474 /** 475 * @} 476 */ 477 478 /** @defgroup GPT_Encoder_Mode TIM Encoder Mode 479 * @{ 480 */ 481 #define GPT_ENCODERMODE_TI1 (1 << GPT_SMCR_SMS_Pos) 482 #define GPT_ENCODERMODE_TI2 (2 << GPT_SMCR_SMS_Pos) 483 #define GPT_ENCODERMODE_TI3 (3 << GPT_SMCR_SMS_Pos) 484 485 486 /** 487 * @} 488 */ 489 490 /** @defgroup GPT_Interrupt_definition TIM Interrupt definition 491 * @{ 492 */ 493 #define GPT_IT_UPDATE (GPT_DIER_UIE) 494 #define GPT_IT_CC1 (GPT_DIER_CC1IE) 495 #define GPT_IT_CC2 (GPT_DIER_CC2IE) 496 #define GPT_IT_CC3 (GPT_DIER_CC3IE) 497 #define GPT_IT_CC4 (GPT_DIER_CC4IE) 498 #define GPT_IT_COM (GPT_DIER_COMIE) 499 #define GPT_IT_TRIGGER (GPT_DIER_TIE) 500 #define GPT_IT_BREAK (GPT_DIER_BIE) 501 /** 502 * @} 503 */ 504 505 /** @defgroup GPT_Commutation_Source TIM Commutation Source 506 * @{ 507 */ 508 #define GPT_COMMUTATION_TRGI (GPT_CR2_CCUS) 509 #define GPT_COMMUTATION_SOFTWARE 0x00000000U 510 /** 511 * @} 512 */ 513 514 /** @defgroup GPT_DMA_sources TIM DMA sources 515 * @{ 516 */ 517 #define GPT_DMA_UPDATE (GPT_DIER_UDE) 518 #define GPT_DMA_CC1 (GPT_DIER_CC1DE) 519 #define GPT_DMA_CC2 (GPT_DIER_CC2DE) 520 #define GPT_DMA_CC3 (GPT_DIER_CC3DE) 521 #define GPT_DMA_CC4 (GPT_DIER_CC4DE) 522 #define GPT_DMA_COM (GPT_DIER_COMDE) 523 #define GPT_DMA_TRIGGER (GPT_DIER_TDE) 524 /** 525 * @} 526 */ 527 528 /** @defgroup GPT_Event_Source TIM Event Source 529 * @{ 530 */ 531 #define GPT_EVENTSOURCE_UPDATE GPT_EGR_UG 532 #define GPT_EVENTSOURCE_CC1 GPT_EGR_CC1G 533 #define GPT_EVENTSOURCE_CC2 GPT_EGR_CC2G 534 #define GPT_EVENTSOURCE_CC3 GPT_EGR_CC3G 535 #define GPT_EVENTSOURCE_CC4 GPT_EGR_CC4G 536 #define GPT_EVENTSOURCE_COM GPT_EGR_COMG 537 #define GPT_EVENTSOURCE_TRIGGER GPT_EGR_TG 538 #define GPT_EVENTSOURCE_BREAK GPT_EGR_BG 539 540 /** 541 * @} 542 */ 543 544 /** @defgroup GPT_Flag_definition TIM Flag definition 545 * @{ 546 */ 547 #define GPT_FLAG_UPDATE (GPT_SR_UIF) 548 #define GPT_FLAG_CC1 (GPT_SR_CC1IF) 549 #define GPT_FLAG_CC2 (GPT_SR_CC2IF) 550 #define GPT_FLAG_CC3 (GPT_SR_CC3IF) 551 #define GPT_FLAG_CC4 (GPT_SR_CC4IF) 552 #define GPT_FLAG_COM (GPT_SR_COMIF) 553 #define GPT_FLAG_TRIGGER (GPT_SR_TIF) 554 #define GPT_FLAG_BREAK (GPT_SR_BIF) 555 #define GPT_FLAG_CC1OF (GPT_SR_CC1OF) 556 #define GPT_FLAG_CC2OF (GPT_SR_CC2OF) 557 #define GPT_FLAG_CC3OF (GPT_SR_CC3OF) 558 #define GPT_FLAG_CC4OF (GPT_SR_CC4OF) 559 /** 560 * @} 561 */ 562 563 /** @defgroup GPT_Clock_Source TIM Clock Source 564 * @{ 565 */ 566 #define GPT_CLOCKSOURCE_ETRMODE2 (GPT_SMCR_ETPS_1) 567 #define GPT_CLOCKSOURCE_INTERNAL (GPT_SMCR_ETPS_0) 568 #define GPT_CLOCKSOURCE_ITR0 0x00000000U 569 #define GPT_CLOCKSOURCE_ITR1 (GPT_SMCR_TS_0) 570 #define GPT_CLOCKSOURCE_ITR2 (GPT_SMCR_TS_1) 571 #define GPT_CLOCKSOURCE_ITR3 (GPT_SMCR_TS_0 | GPT_SMCR_TS_1) 572 #define GPT_CLOCKSOURCE_TI1ED (GPT_SMCR_TS_2) 573 #define GPT_CLOCKSOURCE_TI1 (GPT_SMCR_TS_0 | GPT_SMCR_TS_2) 574 #define GPT_CLOCKSOURCE_TI2 (GPT_SMCR_TS_1 | GPT_SMCR_TS_2) 575 #define GPT_CLOCKSOURCE_ETRMODE1 (GPT_SMCR_TS) 576 /** 577 * @} 578 */ 579 580 /** @defgroup GPT_Clock_Polarity TIM Clock Polarity 581 * @{ 582 */ 583 #define GPT_CLOCKPOLARITY_INVERTED GPT_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 584 #define GPT_CLOCKPOLARITY_NONINVERTED GPT_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 585 #define GPT_CLOCKPOLARITY_RISING GPT_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 586 #define GPT_CLOCKPOLARITY_FALLING GPT_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 587 #define GPT_CLOCKPOLARITY_BOTHEDGE GPT_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup GPT_Clock_Prescaler TIM Clock Prescaler 593 * @{ 594 */ 595 #define GPT_CLOCKPRESCALER_DIV1 GPT_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 596 #define GPT_CLOCKPRESCALER_DIV2 GPT_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 597 #define GPT_CLOCKPRESCALER_DIV4 GPT_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 598 #define GPT_CLOCKPRESCALER_DIV8 GPT_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup GPT_ClearInput_Source TIM Clear Input Source 604 * @{ 605 */ 606 #define GPT_CLEARINPUTSOURCE_ETR 0x00000001U 607 #define GPT_CLEARINPUTSOURCE_NONE 0x00000000U 608 /** 609 * @} 610 */ 611 612 /** @defgroup GPT_ClearInput_Polarity TIM Clear Input Polarity 613 * @{ 614 */ 615 #define GPT_CLEARINPUTPOLARITY_INVERTED GPT_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 616 #define GPT_CLEARINPUTPOLARITY_NONINVERTED GPT_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 617 /** 618 * @} 619 */ 620 621 /** @defgroup GPT_ClearInput_Prescaler TIM Clear Input Prescaler 622 * @{ 623 */ 624 #define GPT_CLEARINPUTPRESCALER_DIV1 GPT_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 625 #define GPT_CLEARINPUTPRESCALER_DIV2 GPT_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 626 #define GPT_CLEARINPUTPRESCALER_DIV4 GPT_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 627 #define GPT_CLEARINPUTPRESCALER_DIV8 GPT_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup GPT_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 633 * @{ 634 */ 635 #define GPT_OSSR_ENABLE (GPT_BDTR_OSSR) 636 #define GPT_OSSR_DISABLE 0x00000000U 637 /** 638 * @} 639 */ 640 641 /** @defgroup GPT_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 642 * @{ 643 */ 644 #define GPT_OSSI_ENABLE (GPT_BDTR_OSSI) 645 #define GPT_OSSI_DISABLE 0x00000000U 646 /** 647 * @} 648 */ 649 650 /** @defgroup GPT_Lock_level TIM Lock level 651 * @{ 652 */ 653 #define GPT_LOCKLEVEL_OFF 0x00000000U 654 #define GPT_LOCKLEVEL_1 (GPT_BDTR_LOCK_0) 655 #define GPT_LOCKLEVEL_2 (GPT_BDTR_LOCK_1) 656 #define GPT_LOCKLEVEL_3 (GPT_BDTR_LOCK) 657 /** 658 * @} 659 */ 660 /** @defgroup GPT_Break_Input_enable_disable TIM Break Input State 661 * @{ 662 */ 663 #define GPT_BREAK_ENABLE (GPT_BDTR_BKE) 664 #define GPT_BREAK_DISABLE 0x00000000U 665 /** 666 * @} 667 */ 668 669 /** @defgroup GPT_Break_Polarity TIM Break Polarity 670 * @{ 671 */ 672 #define GPT_BREAKPOLARITY_LOW 0x00000000U 673 #define GPT_BREAKPOLARITY_HIGH (GPT_BDTR_BKP) 674 /** 675 * @} 676 */ 677 678 /** @defgroup GPT_AOE_Bit_Set_Reset TIM AOE Bit State 679 * @{ 680 */ 681 #define GPT_AUTOMATICOUTPUT_ENABLE (GPT_BDTR_AOE) 682 #define GPT_AUTOMATICOUTPUT_DISABLE 0x00000000U 683 /** 684 * @} 685 */ 686 687 /** @defgroup GPT_Master_Mode_Selection TIM Master Mode Selection 688 * @{ 689 */ 690 #define GPT_CR2_MMS_0 (1<<ATIM_CR2_MMS_Pos) 691 #define GPT_CR2_MMS_1 (2<<ATIM_CR2_MMS_Pos) 692 #define GPT_CR2_MMS_2 (4<<ATIM_CR2_MMS_Pos) 693 694 #define GPT_TRGO_RESET 0x00000000U 695 #define GPT_TRGO_ENABLE (GPT_CR2_MMS_0) 696 #define GPT_TRGO_UPDATE (GPT_CR2_MMS_1) 697 #define GPT_TRGO_OC1 ((GPT_CR2_MMS_1 | GPT_CR2_MMS_0)) 698 #define GPT_TRGO_OC1REF (GPT_CR2_MMS_2) 699 #define GPT_TRGO_OC2REF ((GPT_CR2_MMS_2 | GPT_CR2_MMS_0)) 700 #define GPT_TRGO_OC3REF ((GPT_CR2_MMS_2 | GPT_CR2_MMS_1)) 701 #define GPT_TRGO_OC4REF ((GPT_CR2_MMS_2 | GPT_CR2_MMS_1 | GPT_CR2_MMS_0)) 702 /** 703 * @} 704 */ 705 706 /** @defgroup GPT_Slave_Mode TIM Slave Mode 707 * @{ 708 */ 709 #define GPT_SLAVEMODE_DISABLE 0x00000000U 710 #define GPT_SLAVEMODE_RESET 0x00000004U 711 #define GPT_SLAVEMODE_GATED 0x00000005U 712 #define GPT_SLAVEMODE_TRIGGER 0x00000006U 713 #define GPT_SLAVEMODE_EXTERNAL1 0x00000007U 714 /** 715 * @} 716 */ 717 718 /** @defgroup GPT_Master_Slave_Mode TIM Master Slave Mode 719 * @{ 720 */ 721 #define GPT_MASTERSLAVEMODE_ENABLE 0x00000080U 722 #define GPT_MASTERSLAVEMODE_DISABLE 0x00000000U 723 /** 724 * @} 725 */ 726 727 /** @defgroup GPT_Trigger_Selection TIM Trigger Selection 728 * @{ 729 */ 730 #define GPT_TS_ITR0 0x00000000U 731 #define GPT_TS_ITR1 0x00000010U 732 #define GPT_TS_ITR2 0x00000020U 733 #define GPT_TS_ITR3 0x00000030U 734 #define GPT_TS_TI1F_ED 0x00000040U 735 #define GPT_TS_TI1FP1 0x00000050U 736 #define GPT_TS_TI2FP2 0x00000060U 737 #define GPT_TS_ETRF 0x00000070U 738 #define GPT_TS_NONE 0x0000FFFFU 739 /** 740 * @} 741 */ 742 743 /** @defgroup GPT_Trigger_Polarity TIM Trigger Polarity 744 * @{ 745 */ 746 #define GPT_TRIGGERPOLARITY_INVERTED GPT_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 747 #define GPT_TRIGGERPOLARITY_NONINVERTED GPT_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 748 #define GPT_TRIGGERPOLARITY_RISING GPT_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 749 #define GPT_TRIGGERPOLARITY_FALLING GPT_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 750 #define GPT_TRIGGERPOLARITY_BOTHEDGE GPT_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 751 /** 752 * @} 753 */ 754 755 /** @defgroup GPT_Trigger_Prescaler TIM Trigger Prescaler 756 * @{ 757 */ 758 #define GPT_TRIGGERPRESCALER_DIV1 GPT_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 759 #define GPT_TRIGGERPRESCALER_DIV2 GPT_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 760 #define GPT_TRIGGERPRESCALER_DIV4 GPT_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 761 #define GPT_TRIGGERPRESCALER_DIV8 GPT_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 762 /** 763 * @} 764 */ 765 766 767 /** @defgroup GPT_TI1_Selection TIM TI1 Selection 768 * @{ 769 */ 770 #define GPT_TI1SELECTION_CH1 0x00000000U 771 #define GPT_TI1SELECTION_XORCOMBINATION (GPT_CR2_TI1S) 772 /** 773 * @} 774 */ 775 776 /** @defgroup GPT_DMA_Base_address TIM DMA Base address 777 * @{ 778 */ 779 #define GPT_DMABASE_CR1 0x00000000U 780 #define GPT_DMABASE_CR2 0x00000001U 781 #define GPT_DMABASE_SMCR 0x00000002U 782 #define GPT_DMABASE_DIER 0x00000003U 783 #define GPT_DMABASE_SR 0x00000004U 784 #define GPT_DMABASE_EGR 0x00000005U 785 #define GPT_DMABASE_CCMR1 0x00000006U 786 #define GPT_DMABASE_CCMR2 0x00000007U 787 #define GPT_DMABASE_CCER 0x00000008U 788 #define GPT_DMABASE_CNT 0x00000009U 789 #define GPT_DMABASE_PSC 0x0000000AU 790 #define GPT_DMABASE_ARR 0x0000000BU 791 #define GPT_DMABASE_RCR 0x0000000CU 792 #define GPT_DMABASE_CCR1 0x0000000DU 793 #define GPT_DMABASE_CCR2 0x0000000EU 794 #define GPT_DMABASE_CCR3 0x0000000FU 795 #define GPT_DMABASE_CCR4 0x00000010U 796 #define GPT_DMABASE_BDTR 0x00000011U 797 #define GPT_DMABASE_DCR 0x00000012U 798 #define GPT_DMABASE_OR 0x00000013U 799 /** 800 * @} 801 */ 802 803 /** @defgroup GPT_DMA_Burst_Length TIM DMA Burst Length 804 * @{ 805 */ 806 #define GPT_DMABURSTLENGTH_1TRANSFER 0x00000000U 807 #define GPT_DMABURSTLENGTH_2TRANSFERS 0x00000100U 808 #define GPT_DMABURSTLENGTH_3TRANSFERS 0x00000200U 809 #define GPT_DMABURSTLENGTH_4TRANSFERS 0x00000300U 810 #define GPT_DMABURSTLENGTH_5TRANSFERS 0x00000400U 811 #define GPT_DMABURSTLENGTH_6TRANSFERS 0x00000500U 812 #define GPT_DMABURSTLENGTH_7TRANSFERS 0x00000600U 813 #define GPT_DMABURSTLENGTH_8TRANSFERS 0x00000700U 814 #define GPT_DMABURSTLENGTH_9TRANSFERS 0x00000800U 815 #define GPT_DMABURSTLENGTH_10TRANSFERS 0x00000900U 816 #define GPT_DMABURSTLENGTH_11TRANSFERS 0x00000A00U 817 #define GPT_DMABURSTLENGTH_12TRANSFERS 0x00000B00U 818 #define GPT_DMABURSTLENGTH_13TRANSFERS 0x00000C00U 819 #define GPT_DMABURSTLENGTH_14TRANSFERS 0x00000D00U 820 #define GPT_DMABURSTLENGTH_15TRANSFERS 0x00000E00U 821 #define GPT_DMABURSTLENGTH_16TRANSFERS 0x00000F00U 822 #define GPT_DMABURSTLENGTH_17TRANSFERS 0x00001000U 823 #define GPT_DMABURSTLENGTH_18TRANSFERS 0x00001100U 824 /** 825 * @} 826 */ 827 828 /** @defgroup DMA_Handle_index DMA Handle index 829 * @{ 830 */ 831 #define GPT_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 832 #define GPT_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 833 #define GPT_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 834 #define GPT_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 835 #define GPT_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 836 #define GPT_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 837 #define GPT_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 838 /** 839 * @} 840 */ 841 842 /** @defgroup Channel_CC_State Channel CC State 843 * @{ 844 */ 845 #define GPT_CCx_ENABLE 0x00000001U 846 #define GPT_CCx_DISABLE 0x00000000U 847 #define GPT_CCxN_ENABLE 0x00000004U 848 #define GPT_CCxN_DISABLE 0x00000000U 849 /** 850 * @} 851 */ 852 853 /** 854 * @} 855 */ 856 857 /* Exported macro ------------------------------------------------------------*/ 858 /** @defgroup GPT_Exported_Macros TIM Exported Macros 859 * @{ 860 */ 861 /** @brief Reset TIM handle state 862 * @param \__HANDLE__ TIM handle 863 * @retval None 864 */ 865 #define __HAL_GPT_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPT_STATE_RESET) 866 867 /** 868 * @brief Enable the TIM peripheral. 869 * @param \__HANDLE__ TIM handle 870 * @retval None 871 */ 872 #define __HAL_GPT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(GPT_CR1_CEN)) 873 874 875 #define __HAL_GPT_IS_ENABLED(__INSTANCE__) ((__INSTANCE__)->CR1 & (GPT_CR1_CEN)) 876 877 /** 878 * @brief Enable the TIM main Output. 879 * @param \__HANDLE__ TIM handle 880 * @retval None 881 */ 882 #ifdef hwp_atim1 883 #define __HAL_GPT_MOE_ENABLE(__HANDLE__) (((ATIM_TypeDef*)((__HANDLE__)->Instance))->BDTR|=(ATIM_BDTR_MOE)) 884 #else 885 #define __HAL_GPT_MOE_ENABLE(__HANDLE__) 886 #endif 887 888 /** 889 * @brief Disable the TIM peripheral. 890 * @param \__HANDLE__ TIM handle 891 * @retval None 892 */ 893 #define __HAL_GPT_DISABLE(__HANDLE__) \ 894 do { \ 895 if (((__HANDLE__)->Instance->CCER & GPT_CCER_CCxE_MASK) == 0U) \ 896 { \ 897 if(((__HANDLE__)->Instance->CCER & GPT_CCER_CCxNE_MASK) == 0U) \ 898 { \ 899 (__HANDLE__)->Instance->CR1 &= ~(GPT_CR1_CEN); \ 900 } \ 901 } \ 902 } while(0U) 903 904 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN 905 channels have been disabled */ 906 /** 907 * @brief Disable the TIM main Output. 908 * @param \__HANDLE__ TIM handle 909 * @retval None 910 */ 911 #ifdef hwp_atim1 912 #define __HAL_GPT_MOE_DISABLE(__HANDLE__) \ 913 do { \ 914 if (((__HANDLE__)->Instance->CCER & GPT_CCER_CCxE_MASK) == 0U) \ 915 { \ 916 if(((__HANDLE__)->Instance->CCER & GPT_CCER_CCxNE_MASK) == 0U) \ 917 { \ 918 ((ATIM_TypeDef*)((__HANDLE__)->Instance))->BDTR &= ~(ATIM_BDTR_MOE); \ 919 } \ 920 } \ 921 } while(0U) 922 #else 923 #define __HAL_GPT_MOE_DISABLE(__HANDLE__) 924 #endif 925 /** 926 * @brief Disable the TIM main Output. 927 * @param \__HANDLE__ TIM handle 928 * @retval None 929 * @note The Main Output Enable of a timer instance is disabled unconditionally 930 */ 931 #define __HAL_GPT_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(GPT_BDTR_MOE) 932 933 /** @brief Enable the specified TIM interrupt. 934 * @param \__HANDLE__ specifies the TIM Handle. 935 * @param \__INTERRUPT__ specifies the TIM interrupt source to enable. 936 * This parameter can be one of the following values: 937 * @arg GPT_IT_UPDATE: Update interrupt 938 * @arg GPT_IT_CC1: Capture/Compare 1 interrupt 939 * @arg GPT_IT_CC2: Capture/Compare 2 interrupt 940 * @arg GPT_IT_CC3: Capture/Compare 3 interrupt 941 * @arg GPT_IT_CC4: Capture/Compare 4 interrupt 942 * @arg GPT_IT_COM: Commutation interrupt 943 * @arg GPT_IT_TRIGGER: Trigger interrupt 944 * @arg GPT_IT_BREAK: Break interrupt 945 * @retval None 946 */ 947 #define __HAL_GPT_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 948 949 950 /** @brief Disable the specified TIM interrupt. 951 * @param \__HANDLE__ specifies the TIM Handle. 952 * @param \__INTERRUPT__ specifies the TIM interrupt source to disable. 953 * This parameter can be one of the following values: 954 * @arg GPT_IT_UPDATE: Update interrupt 955 * @arg GPT_IT_CC1: Capture/Compare 1 interrupt 956 * @arg GPT_IT_CC2: Capture/Compare 2 interrupt 957 * @arg GPT_IT_CC3: Capture/Compare 3 interrupt 958 * @arg GPT_IT_CC4: Capture/Compare 4 interrupt 959 * @arg GPT_IT_COM: Commutation interrupt 960 * @arg GPT_IT_TRIGGER: Trigger interrupt 961 * @arg GPT_IT_BREAK: Break interrupt 962 * @retval None 963 */ 964 #define __HAL_GPT_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 965 966 /** @brief Enable the specified DMA request. 967 * @param \__HANDLE__ specifies the TIM Handle. 968 * @param \__DMA__ specifies the TIM DMA request to enable. 969 * This parameter can be one of the following values: 970 * @arg GPT_DMA_UPDATE: Update DMA request 971 * @arg GPT_DMA_CC1: Capture/Compare 1 DMA request 972 * @arg GPT_DMA_CC2: Capture/Compare 2 DMA request 973 * @arg GPT_DMA_CC3: Capture/Compare 3 DMA request 974 * @arg GPT_DMA_CC4: Capture/Compare 4 DMA request 975 * @arg GPT_DMA_COM: Commutation DMA request 976 * @arg GPT_DMA_TRIGGER: Trigger DMA request 977 * @retval None 978 */ 979 #define __HAL_GPT_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 980 981 /** @brief Disable the specified DMA request. 982 * @param \__HANDLE__ specifies the TIM Handle. 983 * @param \__DMA__ specifies the TIM DMA request to disable. 984 * This parameter can be one of the following values: 985 * @arg GPT_DMA_UPDATE: Update DMA request 986 * @arg GPT_DMA_CC1: Capture/Compare 1 DMA request 987 * @arg GPT_DMA_CC2: Capture/Compare 2 DMA request 988 * @arg GPT_DMA_CC3: Capture/Compare 3 DMA request 989 * @arg GPT_DMA_CC4: Capture/Compare 4 DMA request 990 * @arg GPT_DMA_COM: Commutation DMA request 991 * @arg GPT_DMA_TRIGGER: Trigger DMA request 992 * @retval None 993 */ 994 #define __HAL_GPT_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 995 996 /** @brief Check whether the specified TIM interrupt flag is set or not. 997 * @param \__HANDLE__ specifies the TIM Handle. 998 * @param \__FLAG__ specifies the TIM interrupt flag to check. 999 * This parameter can be one of the following values: 1000 * @arg GPT_FLAG_UPDATE: Update interrupt flag 1001 * @arg GPT_FLAG_CC1: Capture/Compare 1 interrupt flag 1002 * @arg GPT_FLAG_CC2: Capture/Compare 2 interrupt flag 1003 * @arg GPT_FLAG_CC3: Capture/Compare 3 interrupt flag 1004 * @arg GPT_FLAG_CC4: Capture/Compare 4 interrupt flag 1005 * @arg GPT_FLAG_CC5: Compare 5 interrupt flag 1006 * @arg GPT_FLAG_CC6: Compare 6 interrupt flag 1007 * @arg GPT_FLAG_COM: Commutation interrupt flag 1008 * @arg GPT_FLAG_TRIGGER: Trigger interrupt flag 1009 * @arg GPT_FLAG_BREAK: Break interrupt flag 1010 * @arg GPT_FLAG_BREAK2: Break 2 interrupt flag 1011 * @arg GPT_FLAG_SYSTEM_BREAK: System Break interrupt flag 1012 * @arg GPT_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1013 * @arg GPT_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1014 * @arg GPT_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1015 * @arg GPT_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1016 * @retval The new state of __FLAG__ (TRUE or FALSE). 1017 */ 1018 #define __HAL_GPT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1019 1020 /** @brief Clear the specified TIM interrupt flag. 1021 * @param \__HANDLE__ specifies the TIM Handle. 1022 * @param \__FLAG__ specifies the TIM interrupt flag to clear. 1023 * This parameter can be one of the following values: 1024 * @arg GPT_FLAG_UPDATE: Update interrupt flag 1025 * @arg GPT_FLAG_CC1: Capture/Compare 1 interrupt flag 1026 * @arg GPT_FLAG_CC2: Capture/Compare 2 interrupt flag 1027 * @arg GPT_FLAG_CC3: Capture/Compare 3 interrupt flag 1028 * @arg GPT_FLAG_CC4: Capture/Compare 4 interrupt flag 1029 * @arg GPT_FLAG_CC5: Compare 5 interrupt flag 1030 * @arg GPT_FLAG_CC6: Compare 6 interrupt flag 1031 * @arg GPT_FLAG_COM: Commutation interrupt flag 1032 * @arg GPT_FLAG_TRIGGER: Trigger interrupt flag 1033 * @arg GPT_FLAG_BREAK: Break interrupt flag 1034 * @arg GPT_FLAG_BREAK2: Break 2 interrupt flag 1035 * @arg GPT_FLAG_SYSTEM_BREAK: System Break interrupt flag 1036 * @arg GPT_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1037 * @arg GPT_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1038 * @arg GPT_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1039 * @arg GPT_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1040 * @retval The new state of __FLAG__ (TRUE or FALSE). 1041 */ 1042 #define __HAL_GPT_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1043 1044 /** 1045 * @brief Check whether the specified TIM interrupt source is enabled or not. 1046 * @param \__HANDLE__ TIM handle 1047 * @param \__INTERRUPT__ specifies the TIM interrupt source to check. 1048 * This parameter can be one of the following values: 1049 * @arg GPT_IT_UPDATE: Update interrupt 1050 * @arg GPT_IT_CC1: Capture/Compare 1 interrupt 1051 * @arg GPT_IT_CC2: Capture/Compare 2 interrupt 1052 * @arg GPT_IT_CC3: Capture/Compare 3 interrupt 1053 * @arg GPT_IT_CC4: Capture/Compare 4 interrupt 1054 * @arg GPT_IT_COM: Commutation interrupt 1055 * @arg GPT_IT_TRIGGER: Trigger interrupt 1056 * @arg GPT_IT_BREAK: Break interrupt 1057 * @retval The state of GPT_IT (SET or RESET). 1058 */ 1059 #define __HAL_GPT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 1060 1061 /** @brief Clear the TIM interrupt pending bits. 1062 * @param \__HANDLE__ TIM handle 1063 * @param \__INTERRUPT__ specifies the interrupt pending bit to clear. 1064 * This parameter can be one of the following values: 1065 * @arg GPT_IT_UPDATE: Update interrupt 1066 * @arg GPT_IT_CC1: Capture/Compare 1 interrupt 1067 * @arg GPT_IT_CC2: Capture/Compare 2 interrupt 1068 * @arg GPT_IT_CC3: Capture/Compare 3 interrupt 1069 * @arg GPT_IT_CC4: Capture/Compare 4 interrupt 1070 * @arg GPT_IT_COM: Commutation interrupt 1071 * @arg GPT_IT_TRIGGER: Trigger interrupt 1072 * @arg GPT_IT_BREAK: Break interrupt 1073 * @retval None 1074 */ 1075 #define __HAL_GPT_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1076 1077 /** 1078 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1079 * @param \__HANDLE__ TIM handle. 1080 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1081 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1082 mode. 1083 */ 1084 #define __HAL_GPT_IS_GPT_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(GPT_CR1_DIR)) == (GPT_CR1_DIR)) 1085 1086 /** 1087 * @brief Set the TIM Prescaler on runtime. 1088 * @param \__HANDLE__ TIM handle. 1089 * @param \__PRESC__ specifies the Prescaler new value. 1090 * @retval None 1091 */ 1092 #define __HAL_GPT_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1093 1094 /** 1095 * @brief Set the TIM single mode. 1096 * @param \__HANDLE__ TIM handle. 1097 * @param \__MODE__ GPT_OPMODE_REPETITIVE:REPETITIVE, GPT_OPMODE_SINGLE:One pulse. 1098 * @retval None 1099 */ 1100 #define __HAL_GPT_SET_MODE(__HANDLE__, __MODE__) (__MODE__?((__HANDLE__)->Instance->CR1|=__MODE__):((__HANDLE__)->Instance->CR1&=~GPT_OPMODE_SINGLE)) 1101 1102 #define GPT_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1103 (((__CHANNEL__) == GPT_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1104 ((__CHANNEL__) == GPT_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1105 ((__CHANNEL__) == GPT_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1106 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1107 1108 #define GPT_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1109 (((__CHANNEL__) == GPT_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~GPT_CCMR1_IC1PSC) :\ 1110 ((__CHANNEL__) == GPT_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~GPT_CCMR1_IC2PSC) :\ 1111 ((__CHANNEL__) == GPT_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~GPT_CCMR2_IC3PSC) :\ 1112 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~GPT_CCMR2_IC4PSC)) 1113 1114 #define GPT_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1115 (((__CHANNEL__) == GPT_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1116 ((__CHANNEL__) == GPT_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1117 ((__CHANNEL__) == GPT_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1118 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & GPT_CCER_CC4P))) 1119 1120 #define GPT_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1121 (((__CHANNEL__) == GPT_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(GPT_CCER_CC1P | GPT_CCER_CC1NP)) :\ 1122 ((__CHANNEL__) == GPT_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(GPT_CCER_CC2P | GPT_CCER_CC2NP)) :\ 1123 ((__CHANNEL__) == GPT_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(GPT_CCER_CC3P | GPT_CCER_CC3NP)) :\ 1124 ((__HANDLE__)->Instance->CCER &= (uint16_t)~GPT_CCER_CC4P)) 1125 1126 /** 1127 * @brief Sets the TIM Capture Compare Register value on runtime without 1128 * calling another time ConfigChannel function. 1129 * @param \__HANDLE__ TIM handle. 1130 * @param \__CHANNEL__ TIM Channels to be configured. 1131 * This parameter can be one of the following values: 1132 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1133 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1134 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1135 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1136 * @param \__COMPARE__ specifies the Capture Compare register new value. 1137 * @retval None 1138 */ 1139 #define __HAL_GPT_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1140 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) 1141 1142 /** 1143 * @brief Gets the TIM Capture Compare Register value on runtime. 1144 * @param \__HANDLE__ TIM handle. 1145 * @param \__CHANNEL__ TIM Channel associated with the capture compare register 1146 * This parameter can be one of the following values: 1147 * @arg GPT_CHANNEL_1: get capture/compare 1 register value 1148 * @arg GPT_CHANNEL_2: get capture/compare 2 register value 1149 * @arg GPT_CHANNEL_3: get capture/compare 3 register value 1150 * @arg GPT_CHANNEL_4: get capture/compare 4 register value 1151 * @arg GPT_CHANNEL_5: get capture/compare 5 register value 1152 * @arg GPT_CHANNEL_6: get capture/compare 6 register value 1153 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1154 */ 1155 #define __HAL_GPT_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1156 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) 1157 1158 /** 1159 * @brief Sets the TIM Counter Register value on runtime. 1160 * @param \__HANDLE__ TIM handle. 1161 * @param \__COUNTER__ specifies the Counter register new value. 1162 * @retval None 1163 */ 1164 #define __HAL_GPT_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1165 1166 /** 1167 * @brief Gets the TIM Counter Register value on runtime. 1168 * @param \__HANDLE__ TIM handle. 1169 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1170 */ 1171 #define __HAL_GPT_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1172 1173 /** 1174 * @brief Sets the TIM Autoreload Register value on runtime without calling 1175 * another time any Init function. 1176 * @param \__HANDLE__ TIM handle. 1177 * @param \__AUTORELOAD__ specifies the Counter register new value. 1178 * @retval None 1179 */ 1180 #define __HAL_GPT_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1181 do{ \ 1182 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1183 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1184 } while(0U) 1185 /** 1186 * @brief Gets the TIM Autoreload Register value on runtime. 1187 * @param \__HANDLE__ TIM handle. 1188 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1189 */ 1190 #define __HAL_GPT_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1191 1192 1193 /** 1194 * @brief Sets the TIM Input Capture prescaler on runtime without calling 1195 * another time HAL_GPT_IC_ConfigChannel() function. 1196 * @param \__HANDLE__ TIM handle. 1197 * @param \__CHANNEL__ TIM Channels to be configured. 1198 * This parameter can be one of the following values: 1199 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1200 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1201 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1202 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1203 * @param \__ICPSC__ specifies the Input Capture4 prescaler new value. 1204 * This parameter can be one of the following values: 1205 * @arg GPT_ICPSC_DIV1: no prescaler 1206 * @arg GPT_ICPSC_DIV2: capture is done once every 2 events 1207 * @arg GPT_ICPSC_DIV4: capture is done once every 4 events 1208 * @arg GPT_ICPSC_DIV8: capture is done once every 8 events 1209 * @retval None 1210 */ 1211 #define __HAL_GPT_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1212 do{ \ 1213 GPT_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1214 GPT_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1215 } while(0U) 1216 1217 /** 1218 * @brief Get the TIM Input Capture prescaler on runtime. 1219 * @param \__HANDLE__ TIM handle. 1220 * @param \__CHANNEL__ TIM Channels to be configured. 1221 * This parameter can be one of the following values: 1222 * @arg GPT_CHANNEL_1: get input capture 1 prescaler value 1223 * @arg GPT_CHANNEL_2: get input capture 2 prescaler value 1224 * @arg GPT_CHANNEL_3: get input capture 3 prescaler value 1225 * @arg GPT_CHANNEL_4: get input capture 4 prescaler value 1226 * @retval The input capture prescaler can be one of the following values: 1227 * @arg GPT_ICPSC_DIV1: no prescaler 1228 * @arg GPT_ICPSC_DIV2: capture is done once every 2 events 1229 * @arg GPT_ICPSC_DIV4: capture is done once every 4 events 1230 * @arg GPT_ICPSC_DIV8: capture is done once every 8 events 1231 */ 1232 #define __HAL_GPT_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1233 (((__CHANNEL__) == GPT_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & GPT_CCMR1_IC1PSC) :\ 1234 ((__CHANNEL__) == GPT_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & GPT_CCMR1_IC2PSC) >> 8U) :\ 1235 ((__CHANNEL__) == GPT_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & GPT_CCMR2_IC3PSC) :\ 1236 (((__HANDLE__)->Instance->CCMR2 & GPT_CCMR2_IC4PSC)) >> 8U) 1237 1238 /** 1239 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register 1240 * @param \__HANDLE__ TIM handle. 1241 * @note When the USR bit of the TIMx_CR1 register is set, only counter 1242 * overflow/underflow generates an update interrupt or DMA request (if 1243 * enabled) 1244 * @retval None 1245 */ 1246 #define __HAL_GPT_URS_ENABLE(__HANDLE__) \ 1247 ((__HANDLE__)->Instance->CR1|= (GPT_CR1_URS)) 1248 1249 /** 1250 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register 1251 * @param \__HANDLE__ TIM handle. 1252 * @note When the USR bit of the TIMx_CR1 register is reset, any of the 1253 * following events generate an update interrupt or DMA request (if 1254 * enabled): 1255 * _ Counter overflow/underflow 1256 * _ Setting the UG bit 1257 * _ Update generation through the slave mode controller 1258 * @retval None 1259 */ 1260 #define __HAL_GPT_URS_DISABLE(__HANDLE__) \ 1261 ((__HANDLE__)->Instance->CR1&=~(GPT_CR1_URS)) 1262 1263 /** 1264 * @brief Sets the TIM Capture x input polarity on runtime. 1265 * @param \__HANDLE__ TIM handle. 1266 * @param \__CHANNEL__ TIM Channels to be configured. 1267 * This parameter can be one of the following values: 1268 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1269 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1270 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1271 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1272 * @param \__POLARITY__ Polarity for TIx source 1273 * @arg GPT_INPUTCHANNELPOLARITY_RISING: Rising Edge 1274 * @arg GPT_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1275 * @arg GPT_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1276 * @note The polarity GPT_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. 1277 * @retval None 1278 */ 1279 #define __HAL_GPT_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1280 do{ \ 1281 GPT_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1282 GPT_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1283 }while(0U) 1284 /** 1285 * @} 1286 */ 1287 1288 /* Include TIM HAL Extension module */ 1289 #include "bf0_hal_tim_ex.h" 1290 1291 /* Exported functions --------------------------------------------------------*/ 1292 /** @addtogroup GPT_Exported_Functions 1293 * @{ 1294 */ 1295 1296 /** @addtogroup GPT_Exported_Functions_Group1 1297 * @{ 1298 */ 1299 1300 /* Time Base functions ********************************************************/ 1301 1302 /** 1303 * @brief Initializes the TIM Time base Unit according to the specified 1304 * parameters in the GPT_HandleTypeDef and create the associated handle. 1305 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1306 * the configuration information for TIM module. 1307 * @retval HAL status 1308 */ 1309 HAL_StatusTypeDef HAL_GPT_Base_Init(GPT_HandleTypeDef *htim); 1310 1311 /** 1312 * @brief DeInitializes the TIM Base peripheral 1313 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1314 * the configuration information for TIM module. 1315 * @retval HAL status 1316 */ 1317 HAL_StatusTypeDef HAL_GPT_Base_DeInit(GPT_HandleTypeDef *htim); 1318 1319 /** 1320 * @brief Initializes the TIM Base MSP. 1321 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1322 * the configuration information for TIM module. 1323 * @retval None 1324 */ 1325 void HAL_GPT_Base_MspInit(GPT_HandleTypeDef *htim); 1326 1327 /** 1328 * @brief DeInitializes TIM Base MSP. 1329 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1330 * the configuration information for TIM module. 1331 * @retval None 1332 */ 1333 void HAL_GPT_Base_MspDeInit(GPT_HandleTypeDef *htim); 1334 1335 /* Blocking mode: Polling */ 1336 /** 1337 * @brief Starts the TIM Base generation. 1338 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1339 * the configuration information for TIM module. 1340 * @retval HAL status 1341 */ 1342 HAL_StatusTypeDef HAL_GPT_Base_Start(GPT_HandleTypeDef *htim); 1343 1344 /** 1345 * @brief Stops the TIM Base generation. 1346 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1347 * the configuration information for TIM module. 1348 * @retval HAL status 1349 */ 1350 HAL_StatusTypeDef HAL_GPT_Base_Stop(GPT_HandleTypeDef *htim); 1351 1352 /* Non-Blocking mode: Interrupt */ 1353 /** 1354 * @brief Starts the TIM Base generation in interrupt mode. 1355 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1356 * the configuration information for TIM module. 1357 * @retval HAL status 1358 */ 1359 HAL_StatusTypeDef HAL_GPT_Base_Start_IT(GPT_HandleTypeDef *htim); 1360 1361 /** 1362 * @brief Stops the TIM Base generation in interrupt mode. 1363 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1364 * the configuration information for TIM module. 1365 * @retval HAL status 1366 */ 1367 HAL_StatusTypeDef HAL_GPT_Base_Stop_IT(GPT_HandleTypeDef *htim); 1368 1369 /* Non-Blocking mode: DMA */ 1370 /** 1371 * @brief Starts the TIM Base generation in DMA mode. 1372 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1373 * the configuration information for TIM module. 1374 * @param pData The source Buffer address. 1375 * @param Length The length of data to be transferred from memory to peripheral. 1376 * @retval HAL status 1377 */ 1378 HAL_StatusTypeDef HAL_GPT_Base_Start_DMA(GPT_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1379 1380 /** 1381 * @brief Stops the TIM Base generation in DMA mode. 1382 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1383 * the configuration information for TIM module. 1384 * @retval HAL status 1385 */ 1386 HAL_StatusTypeDef HAL_GPT_Base_Stop_DMA(GPT_HandleTypeDef *htim); 1387 /** 1388 * @} 1389 */ 1390 1391 /** @addtogroup GPT_Exported_Functions_Group2 1392 * @{ 1393 */ 1394 1395 /* Timer Output Compare functions **********************************************/ 1396 /** 1397 * @brief Initializes the TIM Output Compare according to the specified 1398 * parameters in the GPT_HandleTypeDef and create the associated handle. 1399 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1400 * the configuration information for TIM module. 1401 * @retval HAL status 1402 */ 1403 HAL_StatusTypeDef HAL_GPT_OC_Init(GPT_HandleTypeDef *htim); 1404 1405 /** 1406 * @brief DeInitializes the TIM peripheral 1407 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1408 * the configuration information for TIM module. 1409 * @retval HAL status 1410 */ 1411 HAL_StatusTypeDef HAL_GPT_OC_DeInit(GPT_HandleTypeDef *htim); 1412 1413 /** 1414 * @brief Initializes the TIM Output Compare MSP. 1415 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1416 * the configuration information for TIM module. 1417 * @retval None 1418 */ 1419 void HAL_GPT_OC_MspInit(GPT_HandleTypeDef *htim); 1420 1421 /** 1422 * @brief DeInitializes TIM Output Compare MSP. 1423 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1424 * the configuration information for TIM module. 1425 * @retval None 1426 */ 1427 void HAL_GPT_OC_MspDeInit(GPT_HandleTypeDef *htim); 1428 1429 /* Blocking mode: Polling */ 1430 /** 1431 * @brief Starts the TIM Output Compare signal generation. 1432 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1433 * the configuration information for TIM module. 1434 * @param Channel TIM Channel to be enabled. 1435 * This parameter can be one of the following values: 1436 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1437 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1438 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1439 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1440 * @retval HAL status 1441 */ 1442 HAL_StatusTypeDef HAL_GPT_OC_Start(GPT_HandleTypeDef *htim, uint32_t Channel); 1443 1444 /** 1445 * @brief Stops the TIM Output Compare signal generation. 1446 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1447 * the configuration information for TIM module. 1448 * @param Channel TIM Channel to be disabled. 1449 * This parameter can be one of the following values: 1450 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1451 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1452 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1453 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1454 * @retval HAL status 1455 */ 1456 HAL_StatusTypeDef HAL_GPT_OC_Stop(GPT_HandleTypeDef *htim, uint32_t Channel); 1457 1458 /* Non-Blocking mode: Interrupt */ 1459 /** 1460 * @brief Starts the TIM Output Compare signal generation in interrupt mode. 1461 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1462 * the configuration information for TIM module. 1463 * @param Channel TIM Channel to be enabled. 1464 * This parameter can be one of the following values: 1465 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1466 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1467 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1468 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1469 * @retval HAL status 1470 */ 1471 HAL_StatusTypeDef HAL_GPT_OC_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1472 1473 /** 1474 * @brief Stops the TIM Output Compare signal generation in interrupt mode. 1475 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1476 * the configuration information for TIM module. 1477 * @param Channel TIM Channel to be disabled. 1478 * This parameter can be one of the following values: 1479 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1480 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1481 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1482 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1483 * @retval HAL status 1484 */ 1485 HAL_StatusTypeDef HAL_GPT_OC_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1486 1487 /* Non-Blocking mode: DMA */ 1488 /** 1489 * @brief Starts the TIM Output Compare signal generation in DMA mode. 1490 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1491 * the configuration information for TIM module. 1492 * @param Channel TIM Channel to be enabled. 1493 * This parameter can be one of the following values: 1494 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1495 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1496 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1497 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1498 * @param pData The source Buffer address. 1499 * @param Length The length of data to be transferred from memory to TIM peripheral 1500 * @retval HAL status 1501 */ 1502 HAL_StatusTypeDef HAL_GPT_OC_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1503 1504 /** 1505 * @brief Stops the TIM Output Compare signal generation in DMA mode. 1506 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1507 * the configuration information for TIM module. 1508 * @param Channel TIM Channel to be disabled. 1509 * This parameter can be one of the following values: 1510 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1511 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1512 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1513 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1514 * @retval HAL status 1515 */ 1516 HAL_StatusTypeDef HAL_GPT_OC_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel); 1517 1518 /** 1519 * @} 1520 */ 1521 1522 /** @addtogroup GPT_Exported_Functions_Group3 1523 * @{ 1524 */ 1525 /* Timer PWM functions *********************************************************/ 1526 1527 /** 1528 * @brief Initializes the TIM PWM Time Base according to the specified 1529 * parameters in the GPT_HandleTypeDef and create the associated handle. 1530 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1531 * the configuration information for TIM module. 1532 * @retval HAL status 1533 */ 1534 HAL_StatusTypeDef HAL_GPT_PWM_Init(GPT_HandleTypeDef *htim); 1535 1536 /** 1537 * @brief DeInitializes the TIM peripheral 1538 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1539 * the configuration information for TIM module. 1540 * @retval HAL status 1541 */ 1542 HAL_StatusTypeDef HAL_GPT_PWM_DeInit(GPT_HandleTypeDef *htim); 1543 /** 1544 * @brief Initializes the TIM PWM MSP. 1545 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1546 * the configuration information for TIM module. 1547 * @retval None 1548 */ 1549 void HAL_GPT_PWM_MspInit(GPT_HandleTypeDef *htim); 1550 1551 /** 1552 * @brief DeInitializes TIM PWM MSP. 1553 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1554 * the configuration information for TIM module. 1555 * @retval None 1556 */ 1557 void HAL_GPT_PWM_MspDeInit(GPT_HandleTypeDef *htim); 1558 1559 1560 /* Blocking mode: Polling */ 1561 /** 1562 * @brief Starts the PWM signal generation. 1563 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1564 * the configuration information for TIM module. 1565 * @param Channel TIM Channels to be enabled. 1566 * This parameter can be one of the following values: 1567 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1568 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1569 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1570 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1571 * @retval HAL status 1572 */ 1573 HAL_StatusTypeDef HAL_GPT_PWM_Start(GPT_HandleTypeDef *htim, uint32_t Channel); 1574 /** 1575 * @brief Stops the PWM signal generation. 1576 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1577 * the configuration information for TIM module. 1578 * @param Channel TIM Channels to be disabled. 1579 * This parameter can be one of the following values: 1580 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1581 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1582 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1583 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1584 * @retval HAL status 1585 */ 1586 HAL_StatusTypeDef HAL_GPT_PWM_Stop(GPT_HandleTypeDef *htim, uint32_t Channel); 1587 1588 /* Non-Blocking mode: Interrupt */ 1589 1590 /** 1591 * @brief Starts the PWM signal generation in interrupt mode. 1592 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1593 * the configuration information for TIM module. 1594 * @param Channel TIM Channel to be enabled. 1595 * This parameter can be one of the following values: 1596 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1597 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1598 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1599 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1600 * @retval HAL status 1601 */ 1602 HAL_StatusTypeDef HAL_GPT_PWM_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1603 1604 /** 1605 * @brief Stops the PWM signal generation in interrupt mode. 1606 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1607 * the configuration information for TIM module. 1608 * @param Channel TIM Channels to be disabled. 1609 * This parameter can be one of the following values: 1610 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1611 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1612 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1613 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1614 * @retval HAL status 1615 */ 1616 HAL_StatusTypeDef HAL_GPT_PWM_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1617 1618 /* Non-Blocking mode: DMA */ 1619 /** 1620 * @brief Starts the TIM PWM signal generation in CCX DMA mode. 1621 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1622 * the configuration information for TIM module. 1623 * @param Channel TIM Channels to be enabled. 1624 * This parameter can be one of the following values: 1625 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1626 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1627 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1628 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1629 * @param pData The source Buffer address. 1630 * @param Length The length of data to be transferred from memory to TIM peripheral 1631 * @retval HAL status 1632 */ 1633 HAL_StatusTypeDef HAL_GPT_PWM_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1634 1635 /** 1636 * @brief Starts the TIM PWM signal generation in Update DMA mode. 1637 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1638 * the configuration information for TIM module. 1639 * @param Channel TIM Channels to be enabled. 1640 * This parameter can be one of the following values: 1641 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1642 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1643 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1644 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1645 * @param pData The source Buffer address. 1646 * @param Length The length of data to be transferred from memory to TIM peripheral 1647 * @retval HAL status 1648 */ 1649 HAL_StatusTypeDef HAL_GPT_PWM_Update_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1650 1651 /** 1652 * @brief Stops the TIM PWM signal generation in DMA mode. 1653 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1654 * the configuration information for TIM module. 1655 * @param Channel TIM Channels to be disabled. 1656 * This parameter can be one of the following values: 1657 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1658 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1659 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1660 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1661 * @retval HAL status 1662 */ 1663 HAL_StatusTypeDef HAL_GPT_PWM_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel); 1664 /** 1665 * @brief Stops the TIM PWM signal generation in Update DMA mode. 1666 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1667 * the configuration information for TIM module. 1668 * @param Channel TIM Channels to be disabled. 1669 * This parameter can be one of the following values: 1670 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1671 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1672 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1673 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1674 * @retval HAL status 1675 */ 1676 HAL_StatusTypeDef HAL_GPT_PWM_Update_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel); 1677 1678 /** 1679 * @} 1680 */ 1681 1682 /** @addtogroup GPT_Exported_Functions_Group4 1683 * @{ 1684 */ 1685 /* Timer Input Capture functions ***********************************************/ 1686 /** 1687 * @brief Initializes the TIM Input Capture Time base according to the specified 1688 * parameters in the GPT_HandleTypeDef and create the associated handle. 1689 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1690 * the configuration information for TIM module. 1691 * @retval HAL status 1692 */ 1693 HAL_StatusTypeDef HAL_GPT_IC_Init(GPT_HandleTypeDef *htim); 1694 1695 /** 1696 * @brief DeInitializes the TIM peripheral 1697 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1698 * the configuration information for TIM module. 1699 * @retval HAL status 1700 */ 1701 HAL_StatusTypeDef HAL_GPT_IC_DeInit(GPT_HandleTypeDef *htim); 1702 1703 /** 1704 * @brief Initializes the TIM INput Capture MSP. 1705 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1706 * the configuration information for TIM module. 1707 * @retval None 1708 */ 1709 void HAL_GPT_IC_MspInit(GPT_HandleTypeDef *htim); 1710 1711 /** 1712 * @brief DeInitializes TIM Input Capture MSP. 1713 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1714 * the configuration information for TIM module. 1715 * @retval None 1716 */ 1717 void HAL_GPT_IC_MspDeInit(GPT_HandleTypeDef *htim); 1718 1719 /* Blocking mode: Polling */ 1720 /** 1721 * @brief Starts the TIM Input Capture measurement. 1722 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1723 * the configuration information for TIM module. 1724 * @param Channel TIM Channels to be enabled. 1725 * This parameter can be one of the following values: 1726 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1727 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1728 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1729 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1730 * @retval HAL status 1731 */ 1732 HAL_StatusTypeDef HAL_GPT_IC_Start(GPT_HandleTypeDef *htim, uint32_t Channel); 1733 1734 /** 1735 * @brief Stops the TIM Input Capture measurement. 1736 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1737 * the configuration information for TIM module. 1738 * @param Channel TIM Channels to be disabled. 1739 * This parameter can be one of the following values: 1740 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1741 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1742 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1743 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1744 * @retval HAL status 1745 */ 1746 HAL_StatusTypeDef HAL_GPT_IC_Stop(GPT_HandleTypeDef *htim, uint32_t Channel); 1747 1748 /* Non-Blocking mode: Interrupt */ 1749 /** 1750 * @brief Starts the TIM Input Capture measurement in interrupt mode. 1751 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1752 * the configuration information for TIM module. 1753 * @param Channel TIM Channels to be enabled. 1754 * This parameter can be one of the following values: 1755 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1756 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1757 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1758 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1759 * @retval HAL status 1760 */ 1761 HAL_StatusTypeDef HAL_GPT_IC_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1762 1763 /** 1764 * @brief Stops the TIM Input Capture measurement in interrupt mode. 1765 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1766 * the configuration information for TIM module. 1767 * @param Channel TIM Channels to be disabled. 1768 * This parameter can be one of the following values: 1769 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1770 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1771 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1772 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1773 * @retval HAL status 1774 */ 1775 HAL_StatusTypeDef HAL_GPT_IC_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1776 1777 /* Non-Blocking mode: DMA */ 1778 /** 1779 * @brief Starts the TIM Input Capture measurement on in DMA mode. 1780 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1781 * the configuration information for TIM module. 1782 * @param Channel TIM Channels to be enabled. 1783 * This parameter can be one of the following values: 1784 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1785 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1786 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1787 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1788 * @param pData The destination Buffer address. 1789 * @param Length The length of data to be transferred from TIM peripheral to memory. 1790 * @retval HAL status 1791 */ 1792 HAL_StatusTypeDef HAL_GPT_IC_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1793 1794 /** 1795 * @brief Stops the TIM Input Capture measurement on in DMA mode. 1796 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1797 * the configuration information for TIM module. 1798 * @param Channel TIM Channels to be disabled. 1799 * This parameter can be one of the following values: 1800 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1801 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1802 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 1803 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 1804 * @retval HAL status 1805 */ 1806 HAL_StatusTypeDef HAL_GPT_IC_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel); 1807 1808 /** 1809 * @} 1810 */ 1811 1812 /** @addtogroup GPT_Exported_Functions_Group5 1813 * @{ 1814 */ 1815 /* Timer One Pulse functions ***************************************************/ 1816 /** 1817 * @brief Initializes the TIM One Pulse Time Base according to the specified 1818 * parameters in the GPT_HandleTypeDef and create the associated handle. 1819 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1820 * the configuration information for TIM module. 1821 * @param OnePulseMode Select the One pulse mode. 1822 * This parameter can be one of the following values: 1823 * @arg GPT_OPMODE_SINGLE: Only one pulse will be generated. 1824 * @arg GPT_OPMODE_REPETITIVE: Repetitive pulses will be generated. 1825 * @retval HAL status 1826 */ 1827 HAL_StatusTypeDef HAL_GPT_OnePulse_Init(GPT_HandleTypeDef *htim, uint32_t OnePulseMode); 1828 /** 1829 * @brief DeInitializes the TIM One Pulse 1830 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1831 * the configuration information for TIM module. 1832 * @retval HAL status 1833 */ 1834 HAL_StatusTypeDef HAL_GPT_OnePulse_DeInit(GPT_HandleTypeDef *htim); 1835 /** 1836 * @brief Initializes the TIM One Pulse MSP. 1837 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1838 * the configuration information for TIM module. 1839 * @retval None 1840 */ 1841 void HAL_GPT_OnePulse_MspInit(GPT_HandleTypeDef *htim); 1842 /** 1843 * @brief DeInitializes TIM One Pulse MSP. 1844 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1845 * the configuration information for TIM module. 1846 * @retval None 1847 */ 1848 void HAL_GPT_OnePulse_MspDeInit(GPT_HandleTypeDef *htim); 1849 1850 /* Blocking mode: Polling */ 1851 /** 1852 * @brief Starts the TIM One Pulse signal generation. 1853 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1854 * the configuration information for TIM module. 1855 * @param OutputChannel TIM Channels to be enabled. 1856 * This parameter can be one of the following values: 1857 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1858 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1859 * @retval HAL status 1860 */ 1861 1862 HAL_StatusTypeDef HAL_GPT_OnePulse_Start(GPT_HandleTypeDef *htim, uint32_t OutputChannel); 1863 /** 1864 * @brief Stops the TIM One Pulse signal generation. 1865 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1866 * the configuration information for TIM module. 1867 * @param OutputChannel TIM Channels to be disable. 1868 * This parameter can be one of the following values: 1869 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1870 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1871 * @retval HAL status 1872 */ 1873 HAL_StatusTypeDef HAL_GPT_OnePulse_Stop(GPT_HandleTypeDef *htim, uint32_t OutputChannel); 1874 1875 /* Non-Blocking mode: Interrupt */ 1876 /** 1877 * @brief Starts the TIM One Pulse signal generation in interrupt mode. 1878 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1879 * the configuration information for TIM module. 1880 * @param OutputChannel TIM Channels to be enabled. 1881 * This parameter can be one of the following values: 1882 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1883 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1884 * @retval HAL status 1885 */ 1886 HAL_StatusTypeDef HAL_GPT_OnePulse_Start_IT(GPT_HandleTypeDef *htim, uint32_t OutputChannel); 1887 /** 1888 * @brief Stops the TIM One Pulse signal generation in interrupt mode. 1889 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1890 * the configuration information for TIM module. 1891 * @param OutputChannel TIM Channels to be enabled. 1892 * This parameter can be one of the following values: 1893 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1894 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1895 * @retval HAL status 1896 */ 1897 HAL_StatusTypeDef HAL_GPT_OnePulse_Stop_IT(GPT_HandleTypeDef *htim, uint32_t OutputChannel); 1898 1899 /** 1900 * @} 1901 */ 1902 1903 /** @addtogroup GPT_Exported_Functions_Group6 1904 * @{ 1905 */ 1906 /* Timer Encoder functions *****************************************************/ 1907 /** 1908 * @brief Initializes the TIM Encoder Interface and create the associated handle. 1909 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1910 * the configuration information for TIM module. 1911 * @param sConfig TIM Encoder Interface configuration structure 1912 * @retval HAL status 1913 */ 1914 HAL_StatusTypeDef HAL_GPT_Encoder_Init(GPT_HandleTypeDef *htim, GPT_Encoder_InitTypeDef *sConfig); 1915 /** 1916 * @brief DeInitializes the TIM Encoder interface 1917 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1918 * the configuration information for TIM module. 1919 * @retval HAL status 1920 */ 1921 HAL_StatusTypeDef HAL_GPT_Encoder_DeInit(GPT_HandleTypeDef *htim); 1922 /** 1923 * @brief Initializes the TIM Encoder Interface MSP. 1924 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1925 * the configuration information for TIM module. 1926 * @retval None 1927 */ 1928 void HAL_GPT_Encoder_MspInit(GPT_HandleTypeDef *htim); 1929 /** 1930 * @brief DeInitializes TIM Encoder Interface MSP. 1931 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1932 * the configuration information for TIM module. 1933 * @retval None 1934 */ 1935 void HAL_GPT_Encoder_MspDeInit(GPT_HandleTypeDef *htim); 1936 1937 /* Blocking mode: Polling */ 1938 1939 /** 1940 * @brief Starts the TIM Encoder Interface. 1941 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1942 * the configuration information for TIM module. 1943 * @param Channel TIM Channels to be enabled. 1944 * This parameter can be one of the following values: 1945 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1946 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1947 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 1948 * @retval HAL status 1949 */ 1950 HAL_StatusTypeDef HAL_GPT_Encoder_Start(GPT_HandleTypeDef *htim, uint32_t Channel); 1951 /** 1952 * @brief Stops the TIM Encoder Interface. 1953 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1954 * the configuration information for TIM module. 1955 * @param Channel TIM Channels to be disabled. 1956 * This parameter can be one of the following values: 1957 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1958 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1959 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 1960 * @retval HAL status 1961 */ 1962 HAL_StatusTypeDef HAL_GPT_Encoder_Stop(GPT_HandleTypeDef *htim, uint32_t Channel); 1963 1964 /* Non-Blocking mode: Interrupt */ 1965 /** 1966 * @brief Starts the TIM Encoder Interface in interrupt mode. 1967 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1968 * the configuration information for TIM module. 1969 * @param Channel TIM Channels to be enabled. 1970 * This parameter can be one of the following values: 1971 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1972 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1973 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 1974 * @retval HAL status 1975 */ 1976 HAL_StatusTypeDef HAL_GPT_Encoder_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1977 /** 1978 * @brief Stops the TIM Encoder Interface in interrupt mode. 1979 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1980 * the configuration information for TIM module. 1981 * @param Channel TIM Channels to be disabled. 1982 * This parameter can be one of the following values: 1983 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1984 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1985 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 1986 * @retval HAL status 1987 */ 1988 HAL_StatusTypeDef HAL_GPT_Encoder_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel); 1989 1990 /* Non-Blocking mode: DMA */ 1991 /** 1992 * @brief Starts the TIM Encoder Interface in DMA mode. 1993 * @param htim pointer to a GPT_HandleTypeDef structure that contains 1994 * the configuration information for TIM module. 1995 * @param Channel TIM Channels to be enabled. 1996 * This parameter can be one of the following values: 1997 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 1998 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 1999 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 2000 * @param pData1 The destination Buffer address for IC1. 2001 * @param pData2 The destination Buffer address for IC2. 2002 * @param Length The length of data to be transferred from TIM peripheral to memory. 2003 * @retval HAL status 2004 */ 2005 HAL_StatusTypeDef HAL_GPT_Encoder_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); 2006 /** 2007 * @brief Stops the TIM Encoder Interface in DMA mode. 2008 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2009 * the configuration information for TIM module. 2010 * @param Channel TIM Channels to be enabled. 2011 * This parameter can be one of the following values: 2012 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2013 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2014 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 2015 * @retval HAL status 2016 */ 2017 HAL_StatusTypeDef HAL_GPT_Encoder_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel); 2018 2019 /** 2020 * @} 2021 */ 2022 2023 /** @addtogroup GPT_Exported_Functions_Group7 2024 * @{ 2025 */ 2026 /* Interrupt Handler functions **********************************************/ 2027 /** 2028 * @brief This function handles TIM interrupts requests. 2029 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2030 * the configuration information for TIM module. 2031 * @retval None 2032 */ 2033 void HAL_GPT_IRQHandler(GPT_HandleTypeDef *htim); 2034 2035 /** 2036 * @} 2037 */ 2038 2039 /** @addtogroup GPT_Exported_Functions_Group8 2040 * @{ 2041 */ 2042 /* Control functions *********************************************************/ 2043 /** 2044 * @brief Initializes the TIM Output Compare Channels according to the specified 2045 * parameters in the GPT_OC_InitTypeDef. 2046 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2047 * the configuration information for TIM module. 2048 * @param sConfig TIM Output Compare configuration structure 2049 * @param Channel TIM Channels to be enabled. 2050 * This parameter can be one of the following values: 2051 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2052 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2053 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 2054 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 2055 * @retval HAL status 2056 */ 2057 HAL_StatusTypeDef HAL_GPT_OC_ConfigChannel(GPT_HandleTypeDef *htim, GPT_OC_InitTypeDef *sConfig, uint32_t Channel); 2058 /** 2059 * @brief Initializes the TIM Input Capture Channels according to the specified 2060 * parameters in the GPT_IC_InitTypeDef. 2061 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2062 * the configuration information for TIM module. 2063 * @param sConfig TIM Input Capture configuration structure 2064 * @param Channel TIM Channels to be enabled. 2065 * This parameter can be one of the following values: 2066 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2067 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2068 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 2069 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 2070 * @retval HAL status 2071 */ 2072 HAL_StatusTypeDef HAL_GPT_IC_ConfigChannel(GPT_HandleTypeDef *htim, GPT_IC_InitTypeDef *sConfig, uint32_t Channel); 2073 /** 2074 * @brief Initializes the TIM PWM channels according to the specified 2075 * parameters in the GPT_OC_InitTypeDef. 2076 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2077 * the configuration information for TIM module. 2078 * @param sConfig TIM PWM configuration structure 2079 * @param Channel TIM Channels to be enabled. 2080 * This parameter can be one of the following values: 2081 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2082 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2083 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 2084 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 2085 * @retval HAL status 2086 */ 2087 HAL_StatusTypeDef HAL_GPT_PWM_ConfigChannel(GPT_HandleTypeDef *htim, GPT_OC_InitTypeDef *sConfig, uint32_t Channel); 2088 /** 2089 * @brief Initializes the TIM One Pulse Channels according to the specified 2090 * parameters in the GPT_OnePulse_InitTypeDef. 2091 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2092 * the configuration information for TIM module. 2093 * @param sConfig TIM One Pulse configuration structure 2094 * @param OutputChannel TIM Channels to be enabled. 2095 * This parameter can be one of the following values: 2096 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2097 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2098 * @param InputChannel TIM Channels to be enabled. 2099 * This parameter can be one of the following values: 2100 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2101 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2102 * @retval HAL status 2103 */ 2104 HAL_StatusTypeDef HAL_GPT_OnePulse_ConfigChannel(GPT_HandleTypeDef *htim, GPT_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); 2105 /** 2106 * @brief Configures the OCRef clear feature 2107 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2108 * the configuration information for TIM module. 2109 * @param sClearInputConfig pointer to a GPT_ClearInputConfigTypeDef structure that 2110 * contains the OCREF clear feature and parameters for the TIM peripheral. 2111 * @param Channel specifies the TIM Channel. 2112 * This parameter can be one of the following values: 2113 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2114 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2115 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 2116 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 2117 * @retval HAL status 2118 */ 2119 HAL_StatusTypeDef HAL_GPT_ConfigOCrefClear(GPT_HandleTypeDef *htim, GPT_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); 2120 2121 /** 2122 * @brief Configures the clock source to be used 2123 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2124 * the configuration information for TIM module. 2125 * @param sClockSourceConfig pointer to a GPT_ClockConfigTypeDef structure that 2126 * contains the clock source information for the TIM peripheral. 2127 * @retval HAL status 2128 */ 2129 HAL_StatusTypeDef HAL_GPT_ConfigClockSource(GPT_HandleTypeDef *htim, GPT_ClockConfigTypeDef *sClockSourceConfig); 2130 2131 /** 2132 * @brief Selects the signal connected to the TI1 input: direct from CH1_input 2133 * or a XOR combination between CH1_input, CH2_input & CH3_input 2134 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2135 * the configuration information for TIM module. 2136 * @param TI1_Selection Indicate whether or not channel 1 is connected to the 2137 * output of a XOR gate. 2138 * This parameter can be one of the following values: 2139 * @arg GPT_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input 2140 * @arg GPT_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 2141 * pins are connected to the TI1 input (XOR combination) 2142 * @retval HAL status 2143 */ 2144 HAL_StatusTypeDef HAL_GPT_ConfigTI1Input(GPT_HandleTypeDef *htim, uint32_t TI1_Selection); 2145 /** 2146 * @brief Configures the TIM in Slave mode 2147 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2148 * the configuration information for TIM module. 2149 * @param sSlaveConfig pointer to a GPT_SlaveConfigTypeDef structure that 2150 * contains the selected trigger (internal trigger input, filtered 2151 * timer input or external trigger input) and the ) and the Slave 2152 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). 2153 * @retval HAL status 2154 */ 2155 HAL_StatusTypeDef HAL_GPT_SlaveConfigSynchronization(GPT_HandleTypeDef *htim, GPT_SlaveConfigTypeDef *sSlaveConfig); 2156 /** 2157 * @brief Configures the TIM in Slave mode in interrupt mode 2158 * @param htim TIM handle. 2159 * @param sSlaveConfig pointer to a GPT_SlaveConfigTypeDef structure that 2160 * contains the selected trigger (internal trigger input, filtered 2161 * timer input or external trigger input) and the ) and the Slave 2162 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). 2163 * @retval HAL status 2164 */ 2165 HAL_StatusTypeDef HAL_GPT_SlaveConfigSynchronization_IT(GPT_HandleTypeDef *htim, GPT_SlaveConfigTypeDef *sSlaveConfig); 2166 2167 /** 2168 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral 2169 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2170 * the configuration information for TIM module. 2171 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write. 2172 * This parameters can be on of the following values: 2173 * @arg GPT_DMABASE_CR1 2174 * @arg GPT_DMABASE_CR2 2175 * @arg GPT_DMABASE_SMCR 2176 * @arg GPT_DMABASE_DIER 2177 * @arg GPT_DMABASE_SR 2178 * @arg GPT_DMABASE_EGR 2179 * @arg GPT_DMABASE_CCMR1 2180 * @arg GPT_DMABASE_CCMR2 2181 * @arg GPT_DMABASE_CCER 2182 * @arg GPT_DMABASE_CNT 2183 * @arg GPT_DMABASE_PSC 2184 * @arg GPT_DMABASE_ARR 2185 * @arg GPT_DMABASE_RCR 2186 * @arg GPT_DMABASE_CCR1 2187 * @arg GPT_DMABASE_CCR2 2188 * @arg GPT_DMABASE_CCR3 2189 * @arg GPT_DMABASE_CCR4 2190 * @arg GPT_DMABASE_BDTR 2191 * @arg GPT_DMABASE_DCR 2192 * @param BurstRequestSrc TIM DMA Request sources. 2193 * This parameters can be on of the following values: 2194 * @arg GPT_DMA_UPDATE: TIM update Interrupt source 2195 * @arg GPT_DMA_CC1: TIM Capture Compare 1 DMA source 2196 * @arg GPT_DMA_CC2: TIM Capture Compare 2 DMA source 2197 * @arg GPT_DMA_CC3: TIM Capture Compare 3 DMA source 2198 * @arg GPT_DMA_CC4: TIM Capture Compare 4 DMA source 2199 * @arg GPT_DMA_COM: TIM Commutation DMA source 2200 * @arg GPT_DMA_TRIGGER: TIM Trigger DMA source 2201 * @param BurstBuffer The Buffer address. 2202 * @param BurstLength DMA Burst length. This parameter can be one value 2203 * between GPT_DMABURSTLENGTH_1TRANSFER and GPT_DMABURSTLENGTH_18TRANSFERS. 2204 * @retval HAL status 2205 */ 2206 HAL_StatusTypeDef HAL_GPT_DMABurst_WriteStart(GPT_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 2207 uint32_t *BurstBuffer, uint32_t BurstLength); 2208 /** 2209 * @brief Stops the TIM DMA Burst mode 2210 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2211 * the configuration information for TIM module. 2212 * @param BurstRequestSrc TIM DMA Request sources to disable 2213 * @retval HAL status 2214 */ 2215 HAL_StatusTypeDef HAL_GPT_DMABurst_WriteStop(GPT_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2216 2217 /** 2218 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 2219 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2220 * the configuration information for TIM module. 2221 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read. 2222 * This parameters can be on of the following values: 2223 * @arg GPT_DMABASE_CR1 2224 * @arg GPT_DMABASE_CR2 2225 * @arg GPT_DMABASE_SMCR 2226 * @arg GPT_DMABASE_DIER 2227 * @arg GPT_DMABASE_SR 2228 * @arg GPT_DMABASE_EGR 2229 * @arg GPT_DMABASE_CCMR1 2230 * @arg GPT_DMABASE_CCMR2 2231 * @arg GPT_DMABASE_CCER 2232 * @arg GPT_DMABASE_CNT 2233 * @arg GPT_DMABASE_PSC 2234 * @arg GPT_DMABASE_ARR 2235 * @arg GPT_DMABASE_RCR 2236 * @arg GPT_DMABASE_CCR1 2237 * @arg GPT_DMABASE_CCR2 2238 * @arg GPT_DMABASE_CCR3 2239 * @arg GPT_DMABASE_CCR4 2240 * @arg GPT_DMABASE_BDTR 2241 * @arg GPT_DMABASE_DCR 2242 * @param BurstRequestSrc TIM DMA Request sources. 2243 * This parameters can be on of the following values: 2244 * @arg GPT_DMA_UPDATE: TIM update Interrupt source 2245 * @arg GPT_DMA_CC1: TIM Capture Compare 1 DMA source 2246 * @arg GPT_DMA_CC2: TIM Capture Compare 2 DMA source 2247 * @arg GPT_DMA_CC3: TIM Capture Compare 3 DMA source 2248 * @arg GPT_DMA_CC4: TIM Capture Compare 4 DMA source 2249 * @arg GPT_DMA_COM: TIM Commutation DMA source 2250 * @arg GPT_DMA_TRIGGER: TIM Trigger DMA source 2251 * @param BurstBuffer The Buffer address. 2252 * @param BurstLength DMA Burst length. This parameter can be one value 2253 * between GPT_DMABURSTLENGTH_1TRANSFER and GPT_DMABURSTLENGTH_18TRANSFERS. 2254 * @retval HAL status 2255 */ 2256 HAL_StatusTypeDef HAL_GPT_DMABurst_ReadStart(GPT_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 2257 uint32_t *BurstBuffer, uint32_t BurstLength); 2258 2259 /** 2260 * @brief Stop the DMA burst reading 2261 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2262 * the configuration information for TIM module. 2263 * @param BurstRequestSrc TIM DMA Request sources to disable. 2264 * @retval HAL status 2265 */ 2266 HAL_StatusTypeDef HAL_GPT_DMABurst_ReadStop(GPT_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2267 2268 /** 2269 * @brief Generate a software event 2270 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2271 * the configuration information for TIM module. 2272 * @param EventSource specifies the event source. 2273 * This parameter can be one of the following values: 2274 * @arg GPT_EVENTSOURCE_UPDATE: Timer update Event source 2275 * @arg GPT_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source 2276 * @arg GPT_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source 2277 * @arg GPT_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source 2278 * @arg GPT_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source 2279 * @arg GPT_EVENTSOURCE_COM: Timer COM event source 2280 * @arg GPT_EVENTSOURCE_TRIGGER: Timer Trigger Event source 2281 * @arg GPT_EVENTSOURCE_BREAK: Timer Break event source 2282 * @note TIM6 and TIM7 can only generate an update event. 2283 * @note GPT_EVENTSOURCE_COM and GPT_EVENTSOURCE_BREAK are used only with TIM1 and TIM8. 2284 * @retval HAL status 2285 */ 2286 HAL_StatusTypeDef HAL_GPT_GenerateEvent(GPT_HandleTypeDef *htim, uint32_t EventSource); 2287 /** 2288 * @brief Read the captured value from Capture Compare unit 2289 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2290 * the configuration information for TIM module. 2291 * @param Channel TIM Channels to be enabled. 2292 * This parameter can be one of the following values: 2293 * @arg GPT_CHANNEL_1: TIM Channel 1 selected 2294 * @arg GPT_CHANNEL_2: TIM Channel 2 selected 2295 * @arg GPT_CHANNEL_3: TIM Channel 3 selected 2296 * @arg GPT_CHANNEL_4: TIM Channel 4 selected 2297 * @retval Captured value 2298 */ 2299 uint32_t HAL_GPT_ReadCapturedValue(GPT_HandleTypeDef *htim, uint32_t Channel); 2300 2301 /** 2302 * @} 2303 */ 2304 2305 /** @addtogroup GPT_Exported_Functions_Group9 2306 * @{ 2307 */ 2308 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2309 /** 2310 * @brief HW timer periodical timeout call back 2311 * @param[in] htim: low leverl HW timer device. 2312 */ 2313 void HAL_GPT_PeriodElapsedCallback(GPT_HandleTypeDef *htim); 2314 /** 2315 * @brief Output Compare callback in non blocking mode 2316 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2317 * the configuration information for TIM module. 2318 * @retval None 2319 */ 2320 void HAL_GPT_OC_DelayElapsedCallback(GPT_HandleTypeDef *htim); 2321 /** 2322 * @brief Input Capture callback in non blocking mode 2323 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2324 * the configuration information for TIM module. 2325 * @retval None 2326 */ 2327 void HAL_GPT_IC_CaptureCallback(GPT_HandleTypeDef *htim); 2328 /** 2329 * @brief PWM Pulse finished callback in non blocking mode 2330 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2331 * the configuration information for TIM module. 2332 * @retval None 2333 */ 2334 void HAL_GPT_PWM_PulseFinishedCallback(GPT_HandleTypeDef *htim); 2335 2336 /** 2337 * @brief PWM Pulse finished half complete callback in non-blocking mode 2338 * @param htim TIM handle 2339 * @retval None 2340 */ 2341 void HAL_GPT_PWM_PulseFinishedHalfCpltCallback(GPT_HandleTypeDef *htim); 2342 2343 /** 2344 * @brief Hall Trigger detection callback in non blocking mode 2345 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2346 * the configuration information for TIM module. 2347 * @retval None 2348 */ 2349 void HAL_GPT_TriggerCallback(GPT_HandleTypeDef *htim); 2350 /** 2351 * @brief Timer error callback in non blocking mode 2352 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2353 * the configuration information for TIM module. 2354 * @retval None 2355 */ 2356 void HAL_GPT_ErrorCallback(GPT_HandleTypeDef *htim); 2357 2358 /** 2359 * @} 2360 */ 2361 2362 /** @addtogroup GPT_Exported_Functions_Group10 2363 * @{ 2364 */ 2365 /* Peripheral State functions **************************************************/ 2366 /** 2367 * @brief Return the TIM Base state 2368 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2369 * the configuration information for TIM module. 2370 * @retval HAL state 2371 */ 2372 HAL_GPT_StateTypeDef HAL_GPT_Base_GetState(GPT_HandleTypeDef *htim); 2373 /** 2374 * @brief Return the TIM OC state 2375 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2376 * the configuration information for TIM module. 2377 * @retval HAL state 2378 */ 2379 HAL_GPT_StateTypeDef HAL_GPT_OC_GetState(GPT_HandleTypeDef *htim); 2380 /** 2381 * @brief Return the TIM PWM state 2382 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2383 * the configuration information for TIM module. 2384 * @retval HAL state 2385 */ 2386 HAL_GPT_StateTypeDef HAL_GPT_PWM_GetState(GPT_HandleTypeDef *htim); 2387 /** 2388 * @brief Return the TIM Input Capture state 2389 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2390 * the configuration information for TIM module. 2391 * @retval HAL state 2392 */ 2393 HAL_GPT_StateTypeDef HAL_GPT_IC_GetState(GPT_HandleTypeDef *htim); 2394 /** 2395 * @brief Return the TIM One Pulse Mode state 2396 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2397 * the configuration information for TIM module. 2398 * @retval HAL state 2399 */ 2400 HAL_GPT_StateTypeDef HAL_GPT_OnePulse_GetState(GPT_HandleTypeDef *htim); 2401 /** 2402 * @brief Return the TIM Encoder Mode state 2403 * @param htim pointer to a GPT_HandleTypeDef structure that contains 2404 * the configuration information for TIM module. 2405 * @retval HAL state 2406 */ 2407 HAL_GPT_StateTypeDef HAL_GPT_Encoder_GetState(GPT_HandleTypeDef *htim); 2408 2409 /** 2410 * @} 2411 */ 2412 2413 /** 2414 * @} 2415 */ 2416 2417 /* Private macros ------------------------------------------------------------*/ 2418 /** @defgroup GPT_Private_Macros TIM Private Macros 2419 * @{ 2420 */ 2421 2422 /** @defgroup GPT_IS_GPT_Definitions TIM Private macros to check input parameters 2423 * @{ 2424 */ 2425 #define IS_GPT_COUNTER_MODE(MODE) (((MODE) == GPT_COUNTERMODE_UP) || \ 2426 ((MODE) == GPT_COUNTERMODE_DOWN) || \ 2427 ((MODE) == GPT_COUNTERMODE_CENTERALIGNED3)) 2428 2429 #define IS_GPT_PWM_MODE(MODE) (((MODE) == GPT_OCMODE_PWM1) || \ 2430 ((MODE) == GPT_OCMODE_PWM2)) 2431 2432 #define IS_GPT_OC_MODE(MODE) (((MODE) == GPT_OCMODE_TIMING) || \ 2433 ((MODE) == GPT_OCMODE_ACTIVE) || \ 2434 ((MODE) == GPT_OCMODE_INACTIVE) || \ 2435 ((MODE) == GPT_OCMODE_TOGGLE) || \ 2436 ((MODE) == GPT_OCMODE_FORCED_ACTIVE) || \ 2437 ((MODE) == GPT_OCMODE_FORCED_INACTIVE)) 2438 2439 #define IS_GPT_FAST_STATE(STATE) (((STATE) == GPT_OCFAST_DISABLE) || \ 2440 ((STATE) == GPT_OCFAST_ENABLE)) 2441 2442 #define IS_GPT_OC_POLARITY(POLARITY) (((POLARITY) == GPT_OCPOLARITY_HIGH) || \ 2443 ((POLARITY) == GPT_OCPOLARITY_LOW)) 2444 2445 #define IS_GPT_OCN_POLARITY(POLARITY) (((POLARITY) == GPT_OCNPOLARITY_HIGH) || \ 2446 ((POLARITY) == GPT_OCNPOLARITY_LOW)) 2447 2448 #define IS_GPT_OCIDLE_STATE(STATE) (((STATE) == GPT_OCIDLESTATE_SET) || \ 2449 ((STATE) == GPT_OCIDLESTATE_RESET)) 2450 2451 #define IS_GPT_OCNIDLE_STATE(STATE) (((STATE) == GPT_OCNIDLESTATE_SET) || \ 2452 ((STATE) == GPT_OCNIDLESTATE_RESET)) 2453 2454 #define IS_GPT_CHANNELS(CHANNEL) (((CHANNEL) == GPT_CHANNEL_1) || \ 2455 ((CHANNEL) == GPT_CHANNEL_2) || \ 2456 ((CHANNEL) == GPT_CHANNEL_3) || \ 2457 ((CHANNEL) == GPT_CHANNEL_4) || \ 2458 ((CHANNEL) == GPT_CHANNEL_ALL)) 2459 2460 #define IS_GPT_OPM_CHANNELS(CHANNEL) (((CHANNEL) == GPT_CHANNEL_1) || \ 2461 ((CHANNEL) == GPT_CHANNEL_2)) 2462 2463 #define IS_GPT_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == GPT_CHANNEL_1) || \ 2464 ((CHANNEL) == GPT_CHANNEL_2) || \ 2465 ((CHANNEL) == GPT_CHANNEL_3)) 2466 2467 #define IS_GPT_IC_POLARITY(POLARITY) (((POLARITY) == GPT_ICPOLARITY_RISING) || \ 2468 ((POLARITY) == GPT_ICPOLARITY_FALLING) || \ 2469 ((POLARITY) == GPT_ICPOLARITY_BOTHEDGE)) 2470 2471 #define IS_GPT_IC_SELECTION(SELECTION) (((SELECTION) == GPT_ICSELECTION_DIRECTTI) || \ 2472 ((SELECTION) == GPT_ICSELECTION_INDIRECTTI) || \ 2473 ((SELECTION) == GPT_ICSELECTION_TRC)) 2474 2475 #define IS_GPT_IC_PRESCALER(PRESCALER) (((PRESCALER) == GPT_ICPSC_DIV1) || \ 2476 ((PRESCALER) == GPT_ICPSC_DIV2) || \ 2477 ((PRESCALER) == GPT_ICPSC_DIV4) || \ 2478 ((PRESCALER) == GPT_ICPSC_DIV8)) 2479 2480 #define IS_GPT_OPM_MODE(MODE) (((MODE) == GPT_OPMODE_SINGLE) || \ 2481 ((MODE) == GPT_OPMODE_REPETITIVE)) 2482 2483 #define IS_GPT_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) 2484 2485 #define IS_GPT_ENCODER_MODE(MODE) (((MODE) == GPT_ENCODERMODE_TI1) || \ 2486 ((MODE) == GPT_ENCODERMODE_TI2) || \ 2487 ((MODE) == GPT_ENCODERMODE_TI3)) 2488 2489 #define IS_GPT_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) 2490 2491 #define IS_GPT_CLOCKSOURCE(CLOCK) (((CLOCK) == GPT_CLOCKSOURCE_INTERNAL) || \ 2492 ((CLOCK) == GPT_CLOCKSOURCE_ETRMODE2) || \ 2493 ((CLOCK) == GPT_CLOCKSOURCE_ITR0) || \ 2494 ((CLOCK) == GPT_CLOCKSOURCE_ITR1) || \ 2495 ((CLOCK) == GPT_CLOCKSOURCE_ITR2) || \ 2496 ((CLOCK) == GPT_CLOCKSOURCE_ITR3) || \ 2497 ((CLOCK) == GPT_CLOCKSOURCE_TI1ED) || \ 2498 ((CLOCK) == GPT_CLOCKSOURCE_TI1) || \ 2499 ((CLOCK) == GPT_CLOCKSOURCE_TI2) || \ 2500 ((CLOCK) == GPT_CLOCKSOURCE_ETRMODE1)) 2501 2502 #define IS_GPT_CLOCKPOLARITY(POLARITY) (((POLARITY) == GPT_CLOCKPOLARITY_INVERTED) || \ 2503 ((POLARITY) == GPT_CLOCKPOLARITY_NONINVERTED) || \ 2504 ((POLARITY) == GPT_CLOCKPOLARITY_RISING) || \ 2505 ((POLARITY) == GPT_CLOCKPOLARITY_FALLING) || \ 2506 ((POLARITY) == GPT_CLOCKPOLARITY_BOTHEDGE)) 2507 2508 #define IS_GPT_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == GPT_CLOCKPRESCALER_DIV1) || \ 2509 ((PRESCALER) == GPT_CLOCKPRESCALER_DIV2) || \ 2510 ((PRESCALER) == GPT_CLOCKPRESCALER_DIV4) || \ 2511 ((PRESCALER) == GPT_CLOCKPRESCALER_DIV8)) 2512 2513 #define IS_GPT_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 2514 2515 #define IS_GPT_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == GPT_CLEARINPUTSOURCE_NONE) || \ 2516 ((SOURCE) == GPT_CLEARINPUTSOURCE_ETR)) 2517 2518 #define IS_GPT_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == GPT_CLEARINPUTPOLARITY_INVERTED) || \ 2519 ((POLARITY) == GPT_CLEARINPUTPOLARITY_NONINVERTED)) 2520 2521 #define IS_GPT_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == GPT_CLEARINPUTPRESCALER_DIV1) || \ 2522 ((PRESCALER) == GPT_CLEARINPUTPRESCALER_DIV2) || \ 2523 ((PRESCALER) == GPT_CLEARINPUTPRESCALER_DIV4) || \ 2524 ((PRESCALER) == GPT_CLEARINPUTPRESCALER_DIV8)) 2525 2526 #define IS_GPT_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 2527 2528 #define IS_GPT_OSSR_STATE(STATE) (((STATE) == GPT_OSSR_ENABLE) || \ 2529 ((STATE) == GPT_OSSR_DISABLE)) 2530 2531 #define IS_GPT_OSSI_STATE(STATE) (((STATE) == GPT_OSSI_ENABLE) || \ 2532 ((STATE) == GPT_OSSI_DISABLE)) 2533 2534 #define IS_GPT_LOCK_LEVEL(LEVEL) (((LEVEL) == GPT_LOCKLEVEL_OFF) || \ 2535 ((LEVEL) == GPT_LOCKLEVEL_1) || \ 2536 ((LEVEL) == GPT_LOCKLEVEL_2) || \ 2537 ((LEVEL) == GPT_LOCKLEVEL_3)) 2538 2539 #define IS_GPT_BREAK_STATE(STATE) (((STATE) == GPT_BREAK_ENABLE) || \ 2540 ((STATE) == GPT_BREAK_DISABLE)) 2541 2542 #define IS_GPT_BREAK_POLARITY(POLARITY) (((POLARITY) == GPT_BREAKPOLARITY_LOW) || \ 2543 ((POLARITY) == GPT_BREAKPOLARITY_HIGH)) 2544 2545 #define IS_GPT_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == GPT_AUTOMATICOUTPUT_ENABLE) || \ 2546 ((STATE) == GPT_AUTOMATICOUTPUT_DISABLE)) 2547 2548 #define IS_GPT_TRGO_SOURCE(SOURCE) (((SOURCE) == GPT_TRGO_RESET) || \ 2549 ((SOURCE) == GPT_TRGO_ENABLE) || \ 2550 ((SOURCE) == GPT_TRGO_UPDATE) || \ 2551 ((SOURCE) == GPT_TRGO_OC1) || \ 2552 ((SOURCE) == GPT_TRGO_OC1REF) || \ 2553 ((SOURCE) == GPT_TRGO_OC2REF) || \ 2554 ((SOURCE) == GPT_TRGO_OC3REF) || \ 2555 ((SOURCE) == GPT_TRGO_OC4REF)) 2556 2557 #define IS_GPT_SLAVE_MODE(MODE) (((MODE) == GPT_SLAVEMODE_DISABLE) || \ 2558 ((MODE) == GPT_SLAVEMODE_GATED) || \ 2559 ((MODE) == GPT_SLAVEMODE_RESET) || \ 2560 ((MODE) == GPT_SLAVEMODE_TRIGGER) || \ 2561 ((MODE) == GPT_SLAVEMODE_EXTERNAL1)) 2562 2563 #define IS_GPT_MSM_STATE(STATE) (((STATE) == GPT_MASTERSLAVEMODE_ENABLE) || \ 2564 ((STATE) == GPT_MASTERSLAVEMODE_DISABLE)) 2565 2566 #define IS_GPT_TRIGGER_SELECTION(SELECTION) (((SELECTION) == GPT_TS_ITR0) || \ 2567 ((SELECTION) == GPT_TS_ITR1) || \ 2568 ((SELECTION) == GPT_TS_ITR2) || \ 2569 ((SELECTION) == GPT_TS_ITR3) || \ 2570 ((SELECTION) == GPT_TS_TI1F_ED) || \ 2571 ((SELECTION) == GPT_TS_TI1FP1) || \ 2572 ((SELECTION) == GPT_TS_TI2FP2) || \ 2573 ((SELECTION) == GPT_TS_ETRF)) 2574 2575 #define IS_GPT_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == GPT_TS_ITR0) || \ 2576 ((SELECTION) == GPT_TS_ITR1) || \ 2577 ((SELECTION) == GPT_TS_ITR2) || \ 2578 ((SELECTION) == GPT_TS_ITR3) || \ 2579 ((SELECTION) == GPT_TS_NONE)) 2580 2581 #define IS_GPT_TRIGGERPOLARITY(POLARITY) (((POLARITY) == GPT_TRIGGERPOLARITY_INVERTED ) || \ 2582 ((POLARITY) == GPT_TRIGGERPOLARITY_NONINVERTED) || \ 2583 ((POLARITY) == GPT_TRIGGERPOLARITY_RISING ) || \ 2584 ((POLARITY) == GPT_TRIGGERPOLARITY_FALLING ) || \ 2585 ((POLARITY) == GPT_TRIGGERPOLARITY_BOTHEDGE )) 2586 2587 #define IS_GPT_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == GPT_TRIGGERPRESCALER_DIV1) || \ 2588 ((PRESCALER) == GPT_TRIGGERPRESCALER_DIV2) || \ 2589 ((PRESCALER) == GPT_TRIGGERPRESCALER_DIV4) || \ 2590 ((PRESCALER) == GPT_TRIGGERPRESCALER_DIV8)) 2591 2592 #define IS_GPT_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 2593 2594 #define IS_GPT_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == GPT_TI1SELECTION_CH1) || \ 2595 ((TI1SELECTION) == GPT_TI1SELECTION_XORCOMBINATION)) 2596 2597 #define IS_GPT_DMA_BASE(BASE) (((BASE) == GPT_DMABASE_CR1) || \ 2598 ((BASE) == GPT_DMABASE_CR2) || \ 2599 ((BASE) == GPT_DMABASE_SMCR) || \ 2600 ((BASE) == GPT_DMABASE_DIER) || \ 2601 ((BASE) == GPT_DMABASE_SR) || \ 2602 ((BASE) == GPT_DMABASE_EGR) || \ 2603 ((BASE) == GPT_DMABASE_CCMR1) || \ 2604 ((BASE) == GPT_DMABASE_CCMR2) || \ 2605 ((BASE) == GPT_DMABASE_CCER) || \ 2606 ((BASE) == GPT_DMABASE_CNT) || \ 2607 ((BASE) == GPT_DMABASE_PSC) || \ 2608 ((BASE) == GPT_DMABASE_ARR) || \ 2609 ((BASE) == GPT_DMABASE_RCR) || \ 2610 ((BASE) == GPT_DMABASE_CCR1) || \ 2611 ((BASE) == GPT_DMABASE_CCR2) || \ 2612 ((BASE) == GPT_DMABASE_CCR3) || \ 2613 ((BASE) == GPT_DMABASE_CCR4) || \ 2614 ((BASE) == GPT_DMABASE_BDTR) || \ 2615 ((BASE) == GPT_DMABASE_DCR) || \ 2616 ((BASE) == GPT_DMABASE_OR)) 2617 2618 #define IS_GPT_DMA_LENGTH(LENGTH) (((LENGTH) == GPT_DMABURSTLENGTH_1TRANSFER) || \ 2619 ((LENGTH) == GPT_DMABURSTLENGTH_2TRANSFERS) || \ 2620 ((LENGTH) == GPT_DMABURSTLENGTH_3TRANSFERS) || \ 2621 ((LENGTH) == GPT_DMABURSTLENGTH_4TRANSFERS) || \ 2622 ((LENGTH) == GPT_DMABURSTLENGTH_5TRANSFERS) || \ 2623 ((LENGTH) == GPT_DMABURSTLENGTH_6TRANSFERS) || \ 2624 ((LENGTH) == GPT_DMABURSTLENGTH_7TRANSFERS) || \ 2625 ((LENGTH) == GPT_DMABURSTLENGTH_8TRANSFERS) || \ 2626 ((LENGTH) == GPT_DMABURSTLENGTH_9TRANSFERS) || \ 2627 ((LENGTH) == GPT_DMABURSTLENGTH_10TRANSFERS) || \ 2628 ((LENGTH) == GPT_DMABURSTLENGTH_11TRANSFERS) || \ 2629 ((LENGTH) == GPT_DMABURSTLENGTH_12TRANSFERS) || \ 2630 ((LENGTH) == GPT_DMABURSTLENGTH_13TRANSFERS) || \ 2631 ((LENGTH) == GPT_DMABURSTLENGTH_14TRANSFERS) || \ 2632 ((LENGTH) == GPT_DMABURSTLENGTH_15TRANSFERS) || \ 2633 ((LENGTH) == GPT_DMABURSTLENGTH_16TRANSFERS) || \ 2634 ((LENGTH) == GPT_DMABURSTLENGTH_17TRANSFERS) || \ 2635 ((LENGTH) == GPT_DMABURSTLENGTH_18TRANSFERS)) 2636 2637 #define IS_GPT_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 2638 /** 2639 * @} 2640 */ 2641 2642 /** @defgroup GPT_Mask_Definitions TIM Mask Definition 2643 * @{ 2644 */ 2645 /* The counter of a timer instance is disabled only if all the CCx and CCxN 2646 channels have been disabled */ 2647 #define GPT_CCER_CCxE_MASK ((uint32_t)(GPT_CCER_CC1E | GPT_CCER_CC2E | GPT_CCER_CC3E | GPT_CCER_CC4E)) 2648 #define GPT_CCER_CCxNE_MASK ((uint32_t)(GPT_CCER_CC1NE | GPT_CCER_CC2NE | GPT_CCER_CC3NE)) 2649 2650 /** 2651 * @} 2652 */ 2653 2654 /** 2655 * @} 2656 */ 2657 2658 /* Private functions ---------------------------------------------------------*/ 2659 /** @defgroup GPT_Private_Functions TIM Private Functions 2660 * @{ 2661 */ 2662 void GPT_Base_SetConfig(GPT_TypeDef *TIMx, GPT_Base_InitTypeDef *Structure); 2663 void GPT_TI1_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection, uint32_t GPT_ICFilter); 2664 void GPT_OC2_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config); 2665 void GPT_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 2666 void GPT_DMAError(DMA_HandleTypeDef *hdma); 2667 void GPT_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2668 void GPT_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2669 void GPT_CCxChannelCmd(GPT_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2670 /** 2671 * @} 2672 */ 2673 2674 /** 2675 * @} 2676 */ 2677 2678 /** 2679 * @} 2680 */ 2681 2682 #ifdef HAL_ATIM_MODULE_ENABLED 2683 #define GPT_CCER_CC1NE ATIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 2684 #define GPT_CCER_CC2NE ATIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 2685 #define GPT_CCER_CC3NE ATIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 2686 #else 2687 #define GPT_CCER_CC1NE_Pos (2U) 2688 #define GPT_CCER_CC1NE_Msk (0x1U << GPT_CCER_CC1NE_Pos) /*!< 0x00000004 */ 2689 #define GPT_CCER_CC1NE GPT_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 2690 #define GPT_CCER_CC2NE_Pos (6U) 2691 #define GPT_CCER_CC2NE_Msk (0x1U << GPT_CCER_CC2NE_Pos) /*!< 0x00000040 */ 2692 #define GPT_CCER_CC2NE GPT_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 2693 #define GPT_CCER_CC3NE_Pos (10U) 2694 #define GPT_CCER_CC3NE_Msk (0x1U << GPT_CCER_CC3NE_Pos) /*!< 0x00000400 */ 2695 #define GPT_CCER_CC3NE GPT_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 2696 #endif 2697 2698 2699 #define GPT_DIER_COMIE_Pos (5U) 2700 #define GPT_DIER_COMIE_Msk (0x1U << GPT_DIER_COMIE_Pos) /*!< 0x00000020 */ 2701 #define GPT_DIER_COMIE GPT_DIER_COMIE_Msk /*!<COM interrupt enable */ 2702 #define GPT_DIER_BIE_Pos (7U) 2703 #define GPT_DIER_BIE_Msk (0x1U << GPT_DIER_BIE_Pos) /*!< 0x00000080 */ 2704 #define GPT_DIER_BIE GPT_DIER_BIE_Msk /*!<Break interrupt enable */ 2705 #define GPT_DIER_COMDE_Pos (13U) 2706 #define GPT_DIER_COMDE_Msk (0x1U << GPT_DIER_COMDE_Pos) /*!< 0x00002000 */ 2707 #define GPT_DIER_COMDE GPT_DIER_COMDE_Msk /*!<COM DMA request enable */ 2708 2709 #define GPT_CR1_CKD_0 (0x1U << GPT_CR1_CKD_Pos) /*!< 0x00000100 */ 2710 #define GPT_CR1_CKD_1 (0x2U << GPT_CR1_CKD_Pos) /*!< 0x00000200 */ 2711 2712 #define GPT_CR2_CCUS_Pos (2U) 2713 #define GPT_CR2_CCUS_Msk (0x1U << GPT_CR2_CCUS_Pos) /*!< 0x00000004 */ 2714 #define GPT_CR2_CCUS GPT_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 2715 #define GPT_CR2_OIS1_Pos (8U) 2716 #define GPT_CR2_OIS1_Msk (0x1U << GPT_CR2_OIS1_Pos) /*!< 0x00000100 */ 2717 #define GPT_CR2_OIS1 GPT_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 2718 #define GPT_CR2_OIS1N_Pos (9U) 2719 #define GPT_CR2_OIS1N_Msk (0x1U << GPT_CR2_OIS1N_Pos) /*!< 0x00000200 */ 2720 #define GPT_CR2_OIS1N GPT_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 2721 #define GPT_CR2_OIS2_Pos (10U) 2722 #define GPT_CR2_OIS2_Msk (0x1U << GPT_CR2_OIS2_Pos) /*!< 0x00000400 */ 2723 #define GPT_CR2_OIS2 GPT_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 2724 #define GPT_CR2_OIS2N_Pos (11U) 2725 #define GPT_CR2_OIS2N_Msk (0x1U << GPT_CR2_OIS2N_Pos) /*!< 0x00000800 */ 2726 #define GPT_CR2_OIS2N GPT_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 2727 #define GPT_CR2_OIS3_Pos (12U) 2728 #define GPT_CR2_OIS3_Msk (0x1U << GPT_CR2_OIS3_Pos) /*!< 0x00001000 */ 2729 #define GPT_CR2_OIS3 GPT_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 2730 #define GPT_CR2_OIS3N_Pos (13U) 2731 #define GPT_CR2_OIS3N_Msk (0x1U << GPT_CR2_OIS3N_Pos) /*!< 0x00002000 */ 2732 #define GPT_CR2_OIS3N GPT_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 2733 #define GPT_CR2_OIS4_Pos (14U) 2734 #define GPT_CR2_OIS4_Msk (0x1U << GPT_CR2_OIS4_Pos) /*!< 0x00004000 */ 2735 #define GPT_CR2_OIS4 GPT_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 2736 2737 #define GPT_SR_COMIF_Pos (5U) 2738 #define GPT_SR_COMIF_Msk (0x1U << GPT_SR_COMIF_Pos) /*!< 0x00000020 */ 2739 #define GPT_SR_COMIF GPT_SR_COMIF_Msk /*!<COM interrupt Flag */ 2740 #define GPT_SR_BIF_Pos (7U) 2741 #define GPT_SR_BIF_Msk (0x1U << GPT_SR_BIF_Pos) /*!< 0x00000080 */ 2742 #define GPT_SR_BIF GPT_SR_BIF_Msk /*!<Break interrupt Flag */ 2743 2744 #define GPT_SMCR_ETPS_0 (0x1U << GPT_SMCR_ETPS_Pos) /*!< 0x00001000 */ 2745 #define GPT_SMCR_ETPS_1 (0x2U << GPT_SMCR_ETPS_Pos) /*!< 0x00002000 */ 2746 #define GPT_SMCR_TS_0 (0x1U << GPT_SMCR_TS_Pos) /*!< 0x00000010 */ 2747 #define GPT_SMCR_TS_1 (0x2U << GPT_SMCR_TS_Pos) /*!< 0x00000020 */ 2748 #define GPT_SMCR_TS_2 (0x4U << GPT_SMCR_TS_Pos) /*!< 0x00000040 */ 2749 2750 #define GPT_CCMR1_CC1S_0 (0x1U << GPT_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 2751 #define GPT_CCMR1_CC1S_1 (0x2U << GPT_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 2752 #define GPT_CCMR1_OC1M_0 (0x1U << GPT_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 2753 #define GPT_CCMR1_OC1M_1 (0x2U << GPT_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 2754 #define GPT_CCMR1_OC1M_2 (0x4U << GPT_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 2755 2756 2757 /************ TIM Instances : at least 1 capture/compare channels *************/ 2758 #ifdef hwp_gptim3 2759 #define IS_GPT_CC1_INSTANCE(inst) (((inst) == hwp_gptim1) || \ 2760 ((inst) == hwp_gptim2) || \ 2761 ((inst) == hwp_gptim3) || \ 2762 ((inst) == hwp_gptim4) || \ 2763 ((inst) == hwp_gptim5) || \ 2764 IS_ATIM_INSTANCE(inst) \ 2765 ) 2766 #else 2767 #define IS_GPT_CC1_INSTANCE(inst) (((inst) == hwp_gptim1) || \ 2768 ((inst) == hwp_gptim2) || \ 2769 IS_ATIM_INSTANCE(inst) \ 2770 ) 2771 #endif 2772 2773 /************ TIM Instances : at least 2 capture/compare channels *************/ 2774 #define IS_GPT_CC2_INSTANCE(inst) IS_GPT_CC1_INSTANCE(inst) 2775 2776 /************ TIM Instances : at least 3 capture/compare channels *************/ 2777 #define IS_GPT_CC3_INSTANCE(inst) IS_GPT_CC1_INSTANCE(inst) 2778 2779 /************ TIM Instances : at least 4 capture/compare channels *************/ 2780 2781 #define IS_GPT_CC4_INSTANCE(__INSTANCE__) IS_GPT_CC1_INSTANCE(__INSTANCE__) 2782 2783 2784 /******************** TIM Instances : Advanced-control timers *****************/ 2785 #ifdef hwp_atim2 2786 #define IS_GPT_ADVANCED_INSTANCE(inst) (((inst) == (GPT_TypeDef*)hwp_atim1) || \ 2787 ((inst) == (GPT_TypeDef*)hwp_atim2)) 2788 2789 2790 #elif defined(hwp_atim1) 2791 #define IS_GPT_ADVANCED_INSTANCE(inst) ((inst) == (GPT_TypeDef*)hwp_atim1) 2792 #else 2793 #define IS_GPT_ADVANCED_INSTANCE(inst) 0 2794 #endif 2795 2796 /****************** TIM Instances : All supported instances *******************/ 2797 #ifdef hwp_atim2 2798 #define IS_ATIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) ==(GPT_TypeDef *)hwp_atim1) \ 2799 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_atim2) \ 2800 ) 2801 #elif defined(hwp_atim1) 2802 #define IS_ATIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) ==(GPT_TypeDef *)hwp_atim1) 2803 #else 2804 #define IS_ATIM_INSTANCE(__INSTANCE__) 0 2805 #endif 2806 2807 #ifdef hwp_gptim3 2808 #define IS_GPT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) \ 2809 || ((__INSTANCE__) == hwp_gptim2) \ 2810 || ((__INSTANCE__) == hwp_gptim3) \ 2811 || ((__INSTANCE__) == hwp_gptim4) \ 2812 || ((__INSTANCE__) == hwp_gptim5) \ 2813 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) \ 2814 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) \ 2815 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) \ 2816 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4) \ 2817 || IS_ATIM_INSTANCE(__INSTANCE__) \ 2818 ) 2819 2820 #define IS_GPT_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) \ 2821 || ((__INSTANCE__) == hwp_gptim2) \ 2822 || ((__INSTANCE__) == hwp_gptim3) \ 2823 || ((__INSTANCE__) == hwp_gptim4) \ 2824 || ((__INSTANCE__) == hwp_gptim5) \ 2825 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) \ 2826 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) \ 2827 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) \ 2828 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4) \ 2829 || IS_ATIM_DMA_INSTANCE(__INSTANCE__) \ 2830 ) 2831 2832 2833 #else 2834 #define IS_GPT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) \ 2835 || ((__INSTANCE__) == hwp_gptim2) \ 2836 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) \ 2837 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) \ 2838 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) \ 2839 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4) \ 2840 || IS_ATIM_INSTANCE(__INSTANCE__) \ 2841 ) 2842 2843 #define IS_GPT_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) \ 2844 || ((__INSTANCE__) == hwp_gptim2) \ 2845 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) \ 2846 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) \ 2847 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) \ 2848 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4) \ 2849 || IS_ATIM_DMA_INSTANCE(__INSTANCE__) \ 2850 ) 2851 #endif 2852 2853 /************ TIM Instances : DMA requests generation (COMDE) *****************/ 2854 #ifdef hwp_atim2 2855 #define IS_ATIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) ==(GPT_TypeDef *)hwp_atim1) \ 2856 || ((__INSTANCE__) == (GPT_TypeDef *)hwp_atim2) \ 2857 ) 2858 #elif defined(hwp_atim1) 2859 #define IS_ATIM_DMA_INSTANCE(__INSTANCE__) ((__INSTANCE__) ==(GPT_TypeDef *)hwp_atim1) 2860 #else 2861 #define IS_ATIM_DMA_INSTANCE(__INSTANCE__) 0 2862 #endif 2863 2864 #ifdef hwp_atim2 2865 #define IS_ATIM_CCX_INSTANCE(INSTANCE, chn) \ 2866 ((((INSTANCE) == (GPT_TypeDef *)hwp_atim1) && \ 2867 (((chn) == TIM_CHANNEL_1) || \ 2868 ((chn) == TIM_CHANNEL_2) || \ 2869 ((chn) == TIM_CHANNEL_3) || \ 2870 ((chn) == TIM_CHANNEL_4) || \ 2871 ((chn) == TIM_CHANNEL_5) || \ 2872 ((chn) == TIM_CHANNEL_6))) \ 2873 || \ 2874 (((INSTANCE) == (GPT_TypeDef *)hwp_atim2) && \ 2875 (((chn) == TIM_CHANNEL_1) || \ 2876 ((chn) == TIM_CHANNEL_2) || \ 2877 ((chn) == TIM_CHANNEL_3) || \ 2878 ((chn) == TIM_CHANNEL_4) || \ 2879 ((chn) == TIM_CHANNEL_5) || \ 2880 ((chn) == TIM_CHANNEL_6)))) 2881 #elif defined(hwp_atim1) 2882 #define IS_ATIM_CCX_INSTANCE(INSTANCE, chn) \ 2883 (((INSTANCE) == (GPT_TypeDef *)hwp_atim1) && \ 2884 (((chn) == TIM_CHANNEL_1) || \ 2885 ((chn) == TIM_CHANNEL_2) || \ 2886 ((chn) == TIM_CHANNEL_3) || \ 2887 ((chn) == TIM_CHANNEL_4) || \ 2888 ((chn) == TIM_CHANNEL_5) || \ 2889 ((chn) == TIM_CHANNEL_6))) 2890 #else 2891 #define IS_ATIM_CCX_INSTANCE(INSTANCE, chn) 0 2892 #endif 2893 2894 /******************* TIM Instances : output(s) available **********************/ 2895 #ifdef hwp_gptim3 2896 #define IS_GPT_CCX_INSTANCE(INSTANCE, chn) \ 2897 ((((INSTANCE) == hwp_gptim1) && \ 2898 (((chn) == TIM_CHANNEL_1) || \ 2899 ((chn) == TIM_CHANNEL_2) || \ 2900 ((chn) == TIM_CHANNEL_3) || \ 2901 ((chn) == TIM_CHANNEL_4))) \ 2902 || \ 2903 (((INSTANCE) == hwp_gptim2) && \ 2904 (((chn) == TIM_CHANNEL_1) || \ 2905 ((chn) == TIM_CHANNEL_2) || \ 2906 ((chn) == TIM_CHANNEL_3) || \ 2907 ((chn) == TIM_CHANNEL_4))) \ 2908 || \ 2909 (((INSTANCE) == hwp_gptim3) && \ 2910 (((chn) == TIM_CHANNEL_1) || \ 2911 ((chn) == TIM_CHANNEL_2) || \ 2912 ((chn) == TIM_CHANNEL_3) || \ 2913 ((chn) == TIM_CHANNEL_4))) \ 2914 || \ 2915 (((INSTANCE) == hwp_gptim4) && \ 2916 (((chn) == TIM_CHANNEL_1) || \ 2917 ((chn) == TIM_CHANNEL_2) || \ 2918 ((chn) == TIM_CHANNEL_3) || \ 2919 ((chn) == TIM_CHANNEL_4))) \ 2920 || \ 2921 (((INSTANCE) == hwp_gptim5) && \ 2922 (((chn) == TIM_CHANNEL_1) || \ 2923 ((chn) == TIM_CHANNEL_2) || \ 2924 ((chn) == TIM_CHANNEL_3) || \ 2925 ((chn) == TIM_CHANNEL_4))) \ 2926 || \ 2927 IS_ATIM_CCX_INSTANCE(INSTANCE, chn) \ 2928 ) 2929 #else 2930 2931 #define IS_GPT_CCX_INSTANCE(INSTANCE, chn) \ 2932 ((((INSTANCE) == hwp_gptim1) && \ 2933 (((chn) == TIM_CHANNEL_1) || \ 2934 ((chn) == TIM_CHANNEL_2) || \ 2935 ((chn) == TIM_CHANNEL_3) || \ 2936 ((chn) == TIM_CHANNEL_4))) \ 2937 || \ 2938 (((INSTANCE) == hwp_gptim2) && \ 2939 (((chn) == TIM_CHANNEL_1) || \ 2940 ((chn) == TIM_CHANNEL_2) || \ 2941 ((chn) == TIM_CHANNEL_3) || \ 2942 ((chn) == TIM_CHANNEL_4))) \ 2943 || \ 2944 IS_ATIM_CCX_INSTANCE(INSTANCE, chn) \ 2945 ) 2946 #endif 2947 2948 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 2949 #ifdef hwp_gptim3 2950 #define IS_GPT_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 2951 ((__INSTANCE__) == hwp_gptim2) || \ 2952 ((__INSTANCE__) == hwp_gptim3) || \ 2953 ((__INSTANCE__) == hwp_gptim4) || \ 2954 ((__INSTANCE__) == hwp_gptim5) || \ 2955 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) || \ 2956 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) || \ 2957 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) || \ 2958 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4)) 2959 #else 2960 #define IS_GPT_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 2961 ((__INSTANCE__) == hwp_gptim2) || \ 2962 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) || \ 2963 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) || \ 2964 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) || \ 2965 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4)) 2966 #endif 2967 2968 2969 /******************* TIM Instances : Timer input XOR function *****************/ 2970 #ifdef hwp_gptim3 2971 #define IS_GPT_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 2972 ((__INSTANCE__) == hwp_gptim2) || \ 2973 ((__INSTANCE__) == hwp_gptim3) || \ 2974 ((__INSTANCE__) == hwp_gptim4) || \ 2975 ((__INSTANCE__) == hwp_gptim5) || \ 2976 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) || \ 2977 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) || \ 2978 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) || \ 2979 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4)) 2980 #else 2981 #define IS_GPT_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 2982 ((__INSTANCE__) == hwp_gptim2) || \ 2983 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) || \ 2984 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) || \ 2985 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) || \ 2986 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4)) 2987 #endif 2988 2989 /***************** TIM Instances : external trigger input availabe ************/ 2990 #ifdef hwp_gptim3 2991 #define IS_GPT_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 2992 ((__INSTANCE__) == hwp_gptim2) || \ 2993 ((__INSTANCE__) == hwp_gptim3) || \ 2994 ((__INSTANCE__) == hwp_gptim4) || \ 2995 ((__INSTANCE__) == hwp_gptim5)) 2996 #else 2997 #define IS_GPT_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 2998 ((__INSTANCE__) == hwp_gptim2)) 2999 #endif 3000 3001 /******************** TIM Instances : DMA burst feature ***********************/ 3002 #ifdef hwp_gptim3 3003 #define IS_GPT_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 3004 ((__INSTANCE__) == hwp_gptim2) || \ 3005 ((__INSTANCE__) == hwp_gptim3) || \ 3006 ((__INSTANCE__) == hwp_gptim4) || \ 3007 ((__INSTANCE__) == hwp_gptim5) || \ 3008 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) || \ 3009 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) || \ 3010 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) || \ 3011 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4)) 3012 #else 3013 #define IS_GPT_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 3014 ((__INSTANCE__) == hwp_gptim2) || \ 3015 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim1) || \ 3016 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim2) || \ 3017 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim3) || \ 3018 ((__INSTANCE__) == (GPT_TypeDef *)hwp_btim4)) 3019 #endif 3020 3021 /************ TIM Instances : DMA requests generation (CCxDE) *****************/ 3022 #ifdef hwp_gptim3 3023 #define IS_GPT_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 3024 ((__INSTANCE__) == hwp_gptim2) || \ 3025 ((__INSTANCE__) == hwp_gptim3) || \ 3026 ((__INSTANCE__) == hwp_gptim4) || \ 3027 ((__INSTANCE__) == hwp_gptim5)) 3028 3029 #else 3030 #define IS_GPT_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == hwp_gptim1) || \ 3031 ((__INSTANCE__) == hwp_gptim2)) 3032 3033 #endif 3034 3035 3036 /************************* For ATIM **********************************/ 3037 3038 #define GPT_SMCR_SMS_0 (1<<GPT_SMCR_SMS_Pos) 3039 #define GPT_SMCR_SMS_1 (2<<GPT_SMCR_SMS_Pos) 3040 #define GPT_SMCR_SMS_2 (4<<GPT_SMCR_SMS_Pos) 3041 3042 #define IS_GPT_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == GPT_SLAVEMODE_TRIGGER) 3043 3044 3045 #ifdef __cplusplus 3046 } 3047 #endif 3048 3049 #endif /* __BF0_HAL_GPT_H */
