1 /* 2 * SPDX-FileCopyrightText: 2016 STMicroelectronics 3 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd 4 * 5 * SPDX-License-Identifier: BSD-3-Clause AND Apache-2.0 6 */ 7 8 #ifndef __BF0_HAL_CORTEX_H 9 #define __BF0_HAL_CORTEX_H 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /* Includes ------------------------------------------------------------------*/ 16 #include "bf0_hal_def.h" 17 18 /** @addtogroup BF0_HAL_Driver 19 * @{ 20 */ 21 22 /** @defgroup CORTEX CORTEX-M interface 23 * @{ 24 */ 25 26 /* Exported types ------------------------------------------------------------*/ 27 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 28 * @{ 29 */ 30 31 #if (__MPU_PRESENT == 1) 32 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 33 * @{ 34 */ 35 typedef struct 36 { 37 uint8_t Enable; /*!< Specifies the status of the region. 38 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 39 uint8_t Number; /*!< Specifies the number of the region to protect. 40 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 41 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 42 uint8_t Size; /*!< Specifies the size of the region to protect. 43 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 44 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 45 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 46 uint8_t TypeExtField; /*!< Specifies the TEX field level. 47 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 48 uint8_t AccessPermission; /*!< Specifies the region access permission type. 49 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 50 uint8_t DisableExec; /*!< Specifies the instruction access status. 51 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 52 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 53 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 54 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 55 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 56 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 57 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 58 } MPU_Region_InitTypeDef; 59 /** 60 * @} 61 */ 62 #endif /* __MPU_PRESENT */ 63 64 /** 65 * @} 66 */ 67 68 /* Exported constants --------------------------------------------------------*/ 69 70 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 71 * @{ 72 */ 73 74 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 75 * @{ 76 */ 77 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 78 4 bits for subpriority */ 79 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 80 3 bits for subpriority */ 81 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 82 2 bits for subpriority */ 83 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 84 1 bit for subpriority */ 85 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, 86 0 bit for subpriority */ 87 /** 88 * @} 89 */ 90 91 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 92 * @{ 93 */ 94 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) 95 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) 96 /** 97 * @} 98 */ 99 100 #if (__MPU_PRESENT == 1) 101 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 102 * @{ 103 */ 104 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) 105 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) 106 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) 107 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) 108 /** 109 * @} 110 */ 111 112 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 113 * @{ 114 */ 115 #define MPU_REGION_ENABLE ((uint8_t)0x01) 116 #define MPU_REGION_DISABLE ((uint8_t)0x00) 117 /** 118 * @} 119 */ 120 121 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 122 * @{ 123 */ 124 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 125 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 126 /** 127 * @} 128 */ 129 130 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 131 * @{ 132 */ 133 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 134 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 135 /** 136 * @} 137 */ 138 139 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 140 * @{ 141 */ 142 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 143 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 144 /** 145 * @} 146 */ 147 148 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 149 * @{ 150 */ 151 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 152 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 153 /** 154 * @} 155 */ 156 157 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 158 * @{ 159 */ 160 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 161 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 162 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 163 /** 164 * @} 165 */ 166 167 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 168 * @{ 169 */ 170 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 171 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 172 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 173 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 174 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 175 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 176 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 177 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 178 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 179 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 180 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 181 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 182 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 183 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 184 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 185 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 186 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 187 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 188 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 189 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 190 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 191 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 192 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 193 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 194 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 195 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 196 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 197 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 198 /** 199 * @} 200 */ 201 202 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 203 * @{ 204 */ 205 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 206 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 207 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 208 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 209 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 210 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 211 /** 212 * @} 213 */ 214 215 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 216 * @{ 217 */ 218 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 219 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 220 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 221 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 222 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 223 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 224 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 225 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 226 /** 227 * @} 228 */ 229 #endif /* __MPU_PRESENT */ 230 231 /** 232 * @} 233 */ 234 235 /* Exported macros -----------------------------------------------------------*/ 236 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 237 * @{ 238 */ 239 240 /** 241 * @} 242 */ 243 244 /* Exported functions --------------------------------------------------------*/ 245 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 246 * @{ 247 */ 248 249 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 250 * @brief Initialization and Configuration functions 251 * @{ 252 */ 253 /* Initialization and Configuration functions *****************************/ 254 /** 255 * @brief Set the priority grouping field (pre-emption priority and subpriority) 256 * using the required unlock sequence. 257 * @param PriorityGroup: The priority grouping bits length. 258 * This parameter can be one of the following values: 259 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 260 * 4 bits for subpriority 261 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 262 * 3 bits for subpriority 263 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 264 * 2 bits for subpriority 265 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 266 * 1 bit for subpriority 267 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 268 * 0 bit for subpriority 269 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 270 * The pending IRQ priority will be managed only by the subpriority. 271 * @retval None 272 */ 273 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 274 275 /** 276 * @brief Set the priority of an interrupt. 277 * @param IRQn: External interrupt number. 278 * This parameter can be an enumerator of IRQn_Type enumeration 279 * @param PreemptPriority: The pre-emption priority for the IRQn channel. 280 * This parameter can be a value between 0 and 15 281 * A lower priority value indicates a higher priority 282 * @param SubPriority: the subpriority level for the IRQ channel. 283 * This parameter can be a value between 0 and 15 284 * A lower priority value indicates a higher priority. 285 * @retval None 286 */ 287 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 288 289 /** 290 * @brief Enable a device specific interrupt in the NVIC interrupt controller. 291 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 292 * function should be called before. 293 * @param IRQn External interrupt number. 294 * This parameter can be an enumerator of IRQn_Type enumeration 295 * @retval None 296 */ 297 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 298 299 /** 300 * @brief Disable a device specific interrupt in the NVIC interrupt controller. 301 * @param IRQn External interrupt number. 302 * This parameter can be an enumerator of IRQn_Type enumeration 303 * @retval None 304 */ 305 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 306 307 /** 308 * @brief Initiate a system reset request to reset the MCU. 309 * @retval None 310 */ 311 void HAL_NVIC_SystemReset(void); 312 313 /** 314 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): 315 * Counter is in free running mode to generate periodic interrupts. 316 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. 317 * @retval status: - 0 Function succeeded. 318 * - 1 Function failed. 319 */ 320 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 321 322 /** 323 * @} 324 */ 325 326 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 327 * @brief Cortex control functions 328 * @{ 329 */ 330 /* Peripheral Control functions ***********************************************/ 331 /** 332 * @brief Get the priority grouping field from the NVIC Interrupt Controller. 333 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) 334 */ 335 uint32_t HAL_NVIC_GetPriorityGrouping(void); 336 337 /** 338 * @brief Get the priority of an interrupt. 339 * @param IRQn: External interrupt number. 340 * This parameter can be an enumerator of IRQn_Type enumeration 341 * @param PriorityGroup: the priority grouping bits length. 342 * This parameter can be one of the following values: 343 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 344 * 4 bits for subpriority 345 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 346 * 3 bits for subpriority 347 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 348 * 2 bits for subpriority 349 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 350 * 1 bit for subpriority 351 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 352 * 0 bit for subpriority 353 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). 354 * @param pSubPriority: Pointer on the Subpriority value (starting from 0). 355 * @retval None 356 */ 357 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); 358 359 360 /** 361 * @brief Get Pending Interrupt (read the pending register in the NVIC 362 * and return the pending bit for the specified interrupt). 363 * @param IRQn External interrupt number. 364 * This parameter can be an enumerator of IRQn_Type enumeration 365 * @retval status: - 0 Interrupt status is not pending. 366 * - 1 Interrupt status is pending. 367 */ 368 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 369 370 /** 371 * @brief Set Pending bit of an external interrupt. 372 * @param IRQn External interrupt number 373 * This parameter can be an enumerator of IRQn_Type enumeration 374 * @retval None 375 */ 376 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 377 378 /** 379 * @brief Clear the pending bit of an external interrupt. 380 * @param IRQn External interrupt number. 381 * This parameter can be an enumerator of IRQn_Type enumeration 382 * @retval None 383 */ 384 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 385 386 387 /** 388 * @brief Get active interrupt (read the active register in NVIC and return the active bit). 389 * @param IRQn External interrupt number 390 * This parameter can be an enumerator of IRQn_Type enumeration 391 * @retval status: - 0 Interrupt status is not pending. 392 * - 1 Interrupt status is pending. 393 */ 394 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 395 396 /** 397 * @brief Get the enable status for the specified interrupt IRQn. 398 * @param IRQn External interrupt number 399 * This parameter can be an enumerator of IRQn_Type enumeration 400 * @retval status: - 0 Interrupt is not enabled. 401 * - 1 Interrupt is enabled. 402 */ 403 uint32_t HAL_NVIC_GetEnableIRQ(IRQn_Type IRQn); 404 405 406 /** 407 * @brief Configure the SysTick clock source. 408 * @param CLKSource: specifies the SysTick clock source. 409 * This parameter can be one of the following values: 410 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. 411 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 412 * @retval None 413 */ 414 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 415 416 /** 417 * @brief Handle SYSTICK interrupt request. 418 * @retval None 419 */ 420 void HAL_SYSTICK_IRQHandler(void); 421 422 /** 423 * @brief SYSTICK callback. 424 * @retval None 425 */ 426 void HAL_SYSTICK_Callback(void); 427 428 #if (__MPU_PRESENT == 1) 429 430 /** 431 * @brief Enable the MPU. 432 * @param MPU_Control: Specifies the control mode of the MPU during hard fault, 433 * NMI, FAULTMASK and privileged accessto the default memory 434 * This parameter can be one of the following values: 435 * @arg MPU_HFNMI_PRIVDEF_NONE 436 * @arg MPU_HARDFAULT_NMI 437 * @arg MPU_PRIVILEGED_DEFAULT 438 * @arg MPU_HFNMI_PRIVDEF 439 * @retval None 440 */ 441 void HAL_MPU_Enable(uint32_t MPU_Control); 442 443 /** 444 * @brief Disable the MPU. 445 * @retval None 446 */ 447 void HAL_MPU_Disable(void); 448 449 /** 450 * @brief Initialize and configure the Region and the memory to be protected. 451 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains 452 * the initialization and configuration information. 453 * @retval None 454 */ 455 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 456 #endif /* __MPU_PRESENT */ 457 /** 458 * @} 459 */ 460 461 /** 462 * @} 463 */ 464 465 /* Private types -------------------------------------------------------------*/ 466 /* Private variables ---------------------------------------------------------*/ 467 /* Private constants ---------------------------------------------------------*/ 468 /* Private macros ------------------------------------------------------------*/ 469 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 470 * @{ 471 */ 472 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 473 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 474 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 475 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 476 ((GROUP) == NVIC_PRIORITYGROUP_4)) 477 478 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 479 480 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 481 482 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 483 484 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 485 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 486 487 #if (__MPU_PRESENT == 1) 488 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 489 ((STATE) == MPU_REGION_DISABLE)) 490 491 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 492 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 493 494 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 495 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 496 497 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 498 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 499 500 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 501 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 502 503 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 504 ((TYPE) == MPU_TEX_LEVEL1) || \ 505 ((TYPE) == MPU_TEX_LEVEL2)) 506 507 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 508 ((TYPE) == MPU_REGION_PRIV_RW) || \ 509 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 510 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 511 ((TYPE) == MPU_REGION_PRIV_RO) || \ 512 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 513 514 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 515 ((NUMBER) == MPU_REGION_NUMBER1) || \ 516 ((NUMBER) == MPU_REGION_NUMBER2) || \ 517 ((NUMBER) == MPU_REGION_NUMBER3) || \ 518 ((NUMBER) == MPU_REGION_NUMBER4) || \ 519 ((NUMBER) == MPU_REGION_NUMBER5) || \ 520 ((NUMBER) == MPU_REGION_NUMBER6) || \ 521 ((NUMBER) == MPU_REGION_NUMBER7)) 522 523 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 524 ((SIZE) == MPU_REGION_SIZE_64B) || \ 525 ((SIZE) == MPU_REGION_SIZE_128B) || \ 526 ((SIZE) == MPU_REGION_SIZE_256B) || \ 527 ((SIZE) == MPU_REGION_SIZE_512B) || \ 528 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 529 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 530 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 531 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 532 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 533 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 534 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 535 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 536 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 537 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 538 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 539 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 540 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 541 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 542 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 543 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 544 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 545 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 546 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 547 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 548 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 549 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 550 ((SIZE) == MPU_REGION_SIZE_4GB)) 551 552 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 553 #endif /* __MPU_PRESENT */ 554 555 /** 556 * @} 557 */ 558 559 /* Private functions ---------------------------------------------------------*/ 560 561 /** 562 * @} 563 */ 564 565 /** 566 * @} 567 */ 568 569 #ifdef __cplusplus 570 } 571 #endif 572 573 #endif /* __BF0_HAL_CORTEX_H */
