1 /*
2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef __BF0_HAL_CACHE_H
8 #define __BF0_HAL_CACHE_H
9
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13
14 /* Includes ------------------------------------------------------------------*/
15 #include "bf0_hal_def.h"
16
17 /** @addtogroup CACHE
18 * @ingroup BF0_HAL_Driver
19 * @{
20 */
21
22
23 /**
24 * @brief Clear all counters, i.e. reset to 0
25 * @retval void
26 */
27 #define HAL_CACHE_RESET() (hwp_cache->CCR |= CACHE_CCR_CNTCLR_Msk)
28
29
30
31 /** @defgroup ICACHE_PROF_MODE icache profiling mode
32 * @brief ICACHE profiling mode, could be multiple selected
33 * @{
34 */
35 #ifdef SF32LB58X
36
37 /** Enable MPI1 ICache profiling */
38 #define HAL_CACHE_ICACHE_MPI1 (CACHE_CCR_IRANGE_MPI1)
39 /** Enable MPI2 ICache profiling */
40 #define HAL_CACHE_ICACHE_MPI2 (CACHE_CCR_IRANGE_MPI2)
41 /** Enable MPI3 ICache profiling */
42 #define HAL_CACHE_ICACHE_MPI3 (CACHE_CCR_IRANGE_MPI3)
43 /** Enable MPI4 ICache profiling */
44 #define HAL_CACHE_ICACHE_MPI4 (CACHE_CCR_IRANGE_MPI4)
45 /** Enable MPI5 ICache profiling */
46 #define HAL_CACHE_ICACHE_MPI5 (CACHE_CCR_IRANGE_MPI5)
47 /** Enable all ICache profiling */
48 #define HAL_CACHE_ICACHE_ALL (CACHE_CCR_IRANGE_MPI1 | CACHE_CCR_IRANGE_MPI2 \
49 | CACHE_CCR_IRANGE_MPI3 | CACHE_CCR_IRANGE_MPI4 | CACHE_CCR_IRANGE_MPI5)
50
51 #elif defined(SF32LB56X)
52
53 /** Enable MPI1 ICache profiling */
54 #define HAL_CACHE_ICACHE_MPI1 (CACHE_CCR_IRANGE_MPI1)
55 /** Enable MPI2 ICache profiling */
56 #define HAL_CACHE_ICACHE_MPI2 (CACHE_CCR_IRANGE_MPI2)
57 /** Enable MPI3 ICache profiling */
58 #define HAL_CACHE_ICACHE_MPI3 (CACHE_CCR_IRANGE_MPI3)
59 /** Enable MPI5 ICache profiling */
60 #define HAL_CACHE_ICACHE_MPI5 (CACHE_CCR_IRANGE_MPI5)
61 /** Enable all ICache profiling */
62 #define HAL_CACHE_ICACHE_ALL (CACHE_CCR_IRANGE_MPI1 | CACHE_CCR_IRANGE_MPI2 \
63 | CACHE_CCR_IRANGE_MPI3 | CACHE_CCR_IRANGE_MPI5)
64
65 #elif defined(SF32LB52X)
66
67
68 /** Enable MPI1 ICache profiling */
69 #define HAL_CACHE_ICACHE_MPI1 (CACHE_CCR_IRANGE_MPI1)
70 /** Enable MPI2 ICache profiling */
71 #define HAL_CACHE_ICACHE_MPI2 (CACHE_CCR_IRANGE_MPI2)
72 /** Enable all ICache profiling */
73 #define HAL_CACHE_ICACHE_ALL (CACHE_CCR_IRANGE_MPI1 | CACHE_CCR_IRANGE_MPI2)
74
75 #else
76
77 /** Enable QSPI1 and QSPI4 ICache profiling */
78 #define HAL_CACHE_ICACHE_QSPI1_4 (CACHE_CCR_IRANGE_QSPI1_4)
79 /** Enable QSPI2 ICache profiling */
80 #define HAL_CACHE_ICACHE_QSPI2 (CACHE_CCR_IRANGE_QSPI2)
81 /** Enable QSPI3 ICache profiling */
82 #define HAL_CACHE_ICACHE_QSPI3 (CACHE_CCR_IRANGE_QSPI3)
83 /** Enable OPSRAM ICache profiling */
84 #define HAL_CACHE_ICACHE_OPSRAM (CACHE_CCR_IRANGE_OPSRAM)
85 /** Enable all ICache profiling */
86 #define HAL_CACHE_ICACHE_ALL (HAL_CACHE_ICACHE_QSPI1_4 | HAL_CACHE_ICACHE_QSPI2 \
87 | HAL_CACHE_ICACHE_QSPI3 | HAL_CACHE_ICACHE_OPSRAM)
88
89 #endif
90
91 /**
92 *
93 * @}
94 */
95
96
97 /** @defgroup DCACHE_PROF_MODE dcache profiling mode
98 * @brief DCACHE profiling mode, could be multiple selected
99 * @{
100 */
101 #ifdef SF32LB58X
102
103 /** Enable MPI1 ICache profiling */
104 #define HAL_CACHE_DCACHE_MPI1 (CACHE_CCR_DRANGE_MPI1)
105 /** Enable MPI2 ICache profiling */
106 #define HAL_CACHE_DCACHE_MPI2 (CACHE_CCR_DRANGE_MPI2)
107 /** Enable MPI3 ICache profiling */
108 #define HAL_CACHE_DCACHE_MPI3 (CACHE_CCR_DRANGE_MPI3)
109 /** Enable MPI4 ICache profiling */
110 #define HAL_CACHE_DCACHE_MPI4 (CACHE_CCR_DRANGE_MPI4)
111 /** Enable MPI5 ICache profiling */
112 #define HAL_CACHE_DCACHE_MPI5 (CACHE_CCR_DRANGE_MPI5)
113 /** Enable all ICache profiling */
114 #define HAL_CACHE_DCACHE_ALL (CACHE_CCR_DRANGE_MPI1 | CACHE_CCR_DRANGE_MPI2 \
115 | CACHE_CCR_DRANGE_MPI3 | CACHE_CCR_DRANGE_MPI4 | CACHE_CCR_DRANGE_MPI5)
116
117 #elif defined(SF32LB56X)
118
119 /** Enable MPI1 ICache profiling */
120 #define HAL_CACHE_DCACHE_MPI1 (CACHE_CCR_DRANGE_MPI1)
121 /** Enable MPI2 ICache profiling */
122 #define HAL_CACHE_DCACHE_MPI2 (CACHE_CCR_DRANGE_MPI2)
123 /** Enable MPI3 ICache profiling */
124 #define HAL_CACHE_DCACHE_MPI3 (CACHE_CCR_DRANGE_MPI3)
125 /** Enable MPI5 ICache profiling */
126 #define HAL_CACHE_DCACHE_MPI5 (CACHE_CCR_DRANGE_MPI5)
127 /** Enable all ICache profiling */
128 #define HAL_CACHE_DCACHE_ALL (CACHE_CCR_DRANGE_MPI1 | CACHE_CCR_DRANGE_MPI2 \
129 | CACHE_CCR_DRANGE_MPI3 | CACHE_CCR_DRANGE_MPI5)
130
131
132 #elif defined(SF32LB52X)
133
134 /** Enable MPI1 ICache profiling */
135 #define HAL_CACHE_DCACHE_MPI1 (CACHE_CCR_DRANGE_MPI1)
136 /** Enable MPI2 ICache profiling */
137 #define HAL_CACHE_DCACHE_MPI2 (CACHE_CCR_DRANGE_MPI2)
138 /** Enable all ICache profiling */
139 #define HAL_CACHE_DCACHE_ALL (CACHE_CCR_DRANGE_MPI1 | CACHE_CCR_DRANGE_MPI2)
140
141 #else
142 /** Enable QSPI1 and QSPI4 DCache profiling */
143 #define HAL_CACHE_DCACHE_QSPI1_4 (CACHE_CCR_DRANGE_QSPI1_4)
144 /** Enable QSPI2 DCache profiling */
145 #define HAL_CACHE_DCACHE_QSPI2 (CACHE_CCR_DRANGE_QSPI2)
146 /** Enable QSPI3 DCache profiling */
147 #define HAL_CACHE_DCACHE_QSPI3 (CACHE_CCR_DRANGE_QSPI3)
148 /** Enable OPSRAM DCache profiling */
149 #define HAL_CACHE_DCACHE_OPSRAM (CACHE_CCR_DRANGE_OPSRAM)
150 /** Enable all ICache profiling */
151 #define HAL_CACHE_DCACHE_ALL (HAL_CACHE_DCACHE_QSPI1_4 | HAL_CACHE_DCACHE_QSPI2 \
152 | HAL_CACHE_DCACHE_QSPI3 | HAL_CACHE_DCACHE_OPSRAM)
153 #endif
154
155 /**
156 *
157 * @}
158 */
159
160
161 /**
162 * @brief Enable cache profiling
163 *
164 * @param[in] imode ICache profiling mode bitmap,
165 * see @ref ICACHE_PROF_MODE, could select multiple modes,
166 * such as HAL_CACHE_ICACHE_QSPI1_4|HAL_CACHE_ICACHE_QSPI2 for SF32LB55X
167 * @param[in] dmode DCache profiling mode bitmap,
168 * see @ref DCACHE_PROF_MODE, could select multiple modes,
169 * such as HAL_CACHE_DCACHE_QSPI1_4|HAL_CACHE_DCACHE_QSPI2 for SF32LB55X
170 * @retval void
171 */
HAL_CACHE_Enable(uint32_t imode,uint32_t dmode)172 __STATIC_INLINE void HAL_CACHE_Enable(uint32_t imode, uint32_t dmode)
173 {
174 MODIFY_REG(hwp_cache->CCR, CACHE_CCR_DRANGE_Msk | CACHE_CCR_IRANGE_Msk,
175 imode | dmode);
176 hwp_cache->CCR |= CACHE_CCR_CNTEN;
177 HAL_CACHE_RESET();
178 }
179
180 /**
181 * @brief Disable cache profiling
182 * @retval void
183 */
HAL_CACHE_Disable(void)184 __STATIC_INLINE void HAL_CACHE_Disable(void)
185 {
186 hwp_cache->CCR &= ~CACHE_CCR_CNTEN;
187 }
188
189 /**
190 * @brief Get ICACHE and DCACHE miss rate
191 * @param[out] irate pointer of output icache miss rate, unit: percentage
192 * @param[out] drate pointer of output dcache miss rate, unit: percentage
193 * @param[in] reset true: reset all counters, false: do not reset counters
194 * @retval void
195 */
HAL_CACHE_GetMissRate(float * irate,float * drate,bool reset)196 __STATIC_INLINE void HAL_CACHE_GetMissRate(float *irate, float *drate, bool reset)
197 {
198 if (irate)
199 {
200 if (hwp_cache->IACR)
201 {
202 *irate = hwp_cache->IMCR * (float)100 / hwp_cache->IACR;
203 }
204 else
205 {
206 *irate = 0;
207 }
208 }
209 if (drate)
210 {
211 if (hwp_cache->DACR)
212 {
213 *drate = hwp_cache->DMCR * (float)100 / hwp_cache->DACR;
214 }
215 else
216 {
217 *drate = 0;
218 }
219 }
220 if (reset)
221 {
222 HAL_CACHE_RESET();
223 }
224 }
225
226
227 /**
228 * @brief Get ICACHE miss counter snapshot value when access counter overflows
229 * @retval icache miss counter snapshot value
230 */
231 #define HAL_CACHE_GET_ICACHE_SNAPSHOT() (hwp_cache->ISR)
232
233 /**
234 * @brief Get DCACHE miss counter snapshot value when access counter overflows
235 * @retval dcache miss counter snapshot value
236 */
237 #define HAL_CACHE_GET_DCACHE_SNAPSHOT() (hwp_cache->DSR)
238
239
240 #ifdef __cplusplus
241 }
242 #endif
243
244 ///@} CACHE
245
246 #endif /* __BF0_HAL_CACHE_H */
