1 /* 2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __BTIM_H 8 #define __BTIM_H 9 10 typedef struct 11 { 12 __IO uint32_t CR1; 13 __IO uint32_t CR2; 14 __IO uint32_t SMCR; 15 __IO uint32_t DIER; 16 __IO uint32_t SR; 17 __IO uint32_t EGR; 18 __IO uint32_t RSVD1[3]; 19 __IO uint32_t CNT; 20 __IO uint32_t PSC; 21 __IO uint32_t ARR; 22 } BTIM_TypeDef; 23 24 25 /******************** Bit definition for BTIM_CR1 register ********************/ 26 #define BTIM_CR1_CEN_Pos (0U) 27 #define BTIM_CR1_CEN_Msk (0x1UL << BTIM_CR1_CEN_Pos) 28 #define BTIM_CR1_CEN BTIM_CR1_CEN_Msk 29 #define BTIM_CR1_UDIS_Pos (1U) 30 #define BTIM_CR1_UDIS_Msk (0x1UL << BTIM_CR1_UDIS_Pos) 31 #define BTIM_CR1_UDIS BTIM_CR1_UDIS_Msk 32 #define BTIM_CR1_URS_Pos (2U) 33 #define BTIM_CR1_URS_Msk (0x1UL << BTIM_CR1_URS_Pos) 34 #define BTIM_CR1_URS BTIM_CR1_URS_Msk 35 #define BTIM_CR1_OPM_Pos (3U) 36 #define BTIM_CR1_OPM_Msk (0x1UL << BTIM_CR1_OPM_Pos) 37 #define BTIM_CR1_OPM BTIM_CR1_OPM_Msk 38 #define BTIM_CR1_ARPE_Pos (7U) 39 #define BTIM_CR1_ARPE_Msk (0x1UL << BTIM_CR1_ARPE_Pos) 40 #define BTIM_CR1_ARPE BTIM_CR1_ARPE_Msk 41 42 /******************** Bit definition for BTIM_CR2 register ********************/ 43 #define BTIM_CR2_MMS_Pos (4U) 44 #define BTIM_CR2_MMS_Msk (0x3UL << BTIM_CR2_MMS_Pos) 45 #define BTIM_CR2_MMS BTIM_CR2_MMS_Msk 46 47 /******************* Bit definition for BTIM_SMCR register ********************/ 48 #define BTIM_SMCR_TS_Pos (4U) 49 #define BTIM_SMCR_TS_Msk (0x3UL << BTIM_SMCR_TS_Pos) 50 #define BTIM_SMCR_TS BTIM_SMCR_TS_Msk 51 #define BTIM_SMCR_MSM_Pos (7U) 52 #define BTIM_SMCR_MSM_Msk (0x1UL << BTIM_SMCR_MSM_Pos) 53 #define BTIM_SMCR_MSM BTIM_SMCR_MSM_Msk 54 #define BTIM_SMCR_SMS_Pos (16U) 55 #define BTIM_SMCR_SMS_Msk (0x7UL << BTIM_SMCR_SMS_Pos) 56 #define BTIM_SMCR_SMS BTIM_SMCR_SMS_Msk 57 #define BTIM_SMCR_GTS_Pos (20U) 58 #define BTIM_SMCR_GTS_Msk (0x3UL << BTIM_SMCR_GTS_Pos) 59 #define BTIM_SMCR_GTS BTIM_SMCR_GTS_Msk 60 #define BTIM_SMCR_GTP_Pos (22U) 61 #define BTIM_SMCR_GTP_Msk (0x1UL << BTIM_SMCR_GTP_Pos) 62 #define BTIM_SMCR_GTP BTIM_SMCR_GTP_Msk 63 #define BTIM_SMCR_GM_Pos (23U) 64 #define BTIM_SMCR_GM_Msk (0x1UL << BTIM_SMCR_GM_Pos) 65 #define BTIM_SMCR_GM BTIM_SMCR_GM_Msk 66 67 /******************* Bit definition for BTIM_DIER register ********************/ 68 #define BTIM_DIER_UIE_Pos (0U) 69 #define BTIM_DIER_UIE_Msk (0x1UL << BTIM_DIER_UIE_Pos) 70 #define BTIM_DIER_UIE BTIM_DIER_UIE_Msk 71 #define BTIM_DIER_UDE_Pos (8U) 72 #define BTIM_DIER_UDE_Msk (0x1UL << BTIM_DIER_UDE_Pos) 73 #define BTIM_DIER_UDE BTIM_DIER_UDE_Msk 74 75 /******************** Bit definition for BTIM_SR register *********************/ 76 #define BTIM_SR_UIF_Pos (0U) 77 #define BTIM_SR_UIF_Msk (0x1UL << BTIM_SR_UIF_Pos) 78 #define BTIM_SR_UIF BTIM_SR_UIF_Msk 79 80 /******************** Bit definition for BTIM_EGR register ********************/ 81 #define BTIM_EGR_UG_Pos (0U) 82 #define BTIM_EGR_UG_Msk (0x1UL << BTIM_EGR_UG_Pos) 83 #define BTIM_EGR_UG BTIM_EGR_UG_Msk 84 85 /******************** Bit definition for BTIM_CNT register ********************/ 86 #define BTIM_CNT_CNT_Pos (0U) 87 #define BTIM_CNT_CNT_Msk (0xFFFFFFFFUL << BTIM_CNT_CNT_Pos) 88 #define BTIM_CNT_CNT BTIM_CNT_CNT_Msk 89 90 /******************** Bit definition for BTIM_PSC register ********************/ 91 #define BTIM_PSC_PSC_Pos (0U) 92 #define BTIM_PSC_PSC_Msk (0xFFFFUL << BTIM_PSC_PSC_Pos) 93 #define BTIM_PSC_PSC BTIM_PSC_PSC_Msk 94 95 /******************** Bit definition for BTIM_ARR register ********************/ 96 #define BTIM_ARR_ARR_Pos (0U) 97 #define BTIM_ARR_ARR_Msk (0xFFFFFFFFUL << BTIM_ARR_ARR_Pos) 98 #define BTIM_ARR_ARR BTIM_ARR_ARR_Msk 99 100 #endif 101
