1 /* 2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __BLE_PHY_H 8 #define __BLE_PHY_H 9 10 typedef struct 11 { 12 __IO uint32_t RX_CTRL1; 13 __IO uint32_t RX_RCC_CTRL1; 14 __IO uint32_t NOTCH_CFG1; 15 __IO uint32_t NOTCH_CFG2; 16 __IO uint32_t NOTCH_CFG3; 17 __IO uint32_t NOTCH_CFG4; 18 __IO uint32_t INTERP_CFG1; 19 __IO uint32_t MIXER_CFG1; 20 __IO uint32_t PKTDET_CFG1; 21 __IO uint32_t DEMOD_CFG1; 22 __IO uint32_t DEMOD_CFG2; 23 __IO uint32_t DEMOD_CFG3; 24 __IO uint32_t DEMOD_CFG4; 25 __IO uint32_t DEMOD_CFG5; 26 __IO uint32_t DEMOD_CFG6; 27 __IO uint32_t DEMOD_CFG7; 28 __IO uint32_t CODED_CFG1; 29 __IO uint32_t CODED_CFG2; 30 __IO uint32_t CODED_CFG3; 31 __IO uint32_t CODED_CFG4; 32 __IO uint32_t RX_STATUS1; 33 __IO uint32_t AGC_CTRL; 34 __IO uint32_t AGC_CFG1; 35 __IO uint32_t AGC_CFG2; 36 __IO uint32_t AGC_CFG3; 37 __IO uint32_t AGC_CFG4; 38 __IO uint32_t AGC_CFG5; 39 __IO uint32_t AGC_CFG6; 40 __IO uint32_t AGC_CFG7; 41 __IO uint32_t AGC_CFG8; 42 __IO uint32_t AGC_CFG9; 43 __IO uint32_t AGC_CFG10; 44 __IO uint32_t AGC_CFG11; 45 __IO uint32_t AGC_CFG12; 46 __IO uint32_t RSSI_CFG1; 47 __IO uint32_t AGC_STATUS; 48 __IO uint32_t TX_CTRL; 49 __IO uint32_t TX_RCC_CTRL; 50 __IO uint32_t TX_GAUSSFLT_CFG; 51 __IO uint32_t TX_IF_MOD_CFG; 52 __IO uint32_t TX_HFP_CFG; 53 __IO uint32_t TX_LFP_CFG; 54 __IO uint32_t TX_PA_CFG; 55 __IO uint32_t LFP_MMDIV_CFG0; 56 __IO uint32_t LFP_MMDIV_CFG1; 57 __IO uint32_t LFP_MMDIV_CFG2; 58 __IO uint32_t LFP_MMDIV_CFG3; 59 __IO uint32_t RX_HFP_CFG; 60 __IO uint32_t LNA_GAIN_TBL0; 61 __IO uint32_t LNA_GAIN_TBL1; 62 __IO uint32_t LNA_GAIN_TBL2; 63 __IO uint32_t LNA_GAIN_TBL3; 64 __IO uint32_t LNA_GAIN_TBL4; 65 __IO uint32_t LNA_GAIN_TBL5; 66 __IO uint32_t MP_TEST_CFG; 67 } BLE_PHY_TypeDef; 68 69 70 /**************** Bit definition for BLE_PHY_RX_CTRL1 register ****************/ 71 #define BLE_PHY_RX_CTRL1_ADC_SIGN_Pos (0U) 72 #define BLE_PHY_RX_CTRL1_ADC_SIGN_Msk (0x1UL << BLE_PHY_RX_CTRL1_ADC_SIGN_Pos) 73 #define BLE_PHY_RX_CTRL1_ADC_SIGN BLE_PHY_RX_CTRL1_ADC_SIGN_Msk 74 #define BLE_PHY_RX_CTRL1_MIXER_IQ_SWAP_EN_Pos (1U) 75 #define BLE_PHY_RX_CTRL1_MIXER_IQ_SWAP_EN_Msk (0x1UL << BLE_PHY_RX_CTRL1_MIXER_IQ_SWAP_EN_Pos) 76 #define BLE_PHY_RX_CTRL1_MIXER_IQ_SWAP_EN BLE_PHY_RX_CTRL1_MIXER_IQ_SWAP_EN_Msk 77 #define BLE_PHY_RX_CTRL1_ADC_IQ_SWAP_EN_Pos (2U) 78 #define BLE_PHY_RX_CTRL1_ADC_IQ_SWAP_EN_Msk (0x1UL << BLE_PHY_RX_CTRL1_ADC_IQ_SWAP_EN_Pos) 79 #define BLE_PHY_RX_CTRL1_ADC_IQ_SWAP_EN BLE_PHY_RX_CTRL1_ADC_IQ_SWAP_EN_Msk 80 #define BLE_PHY_RX_CTRL1_FORCE_RX_ON_Pos (3U) 81 #define BLE_PHY_RX_CTRL1_FORCE_RX_ON_Msk (0x1UL << BLE_PHY_RX_CTRL1_FORCE_RX_ON_Pos) 82 #define BLE_PHY_RX_CTRL1_FORCE_RX_ON BLE_PHY_RX_CTRL1_FORCE_RX_ON_Msk 83 #define BLE_PHY_RX_CTRL1_ADC_Q_EN_Pos (4U) 84 #define BLE_PHY_RX_CTRL1_ADC_Q_EN_Msk (0x1UL << BLE_PHY_RX_CTRL1_ADC_Q_EN_Pos) 85 #define BLE_PHY_RX_CTRL1_ADC_Q_EN BLE_PHY_RX_CTRL1_ADC_Q_EN_Msk 86 #define BLE_PHY_RX_CTRL1_LPF1_SAMPLE_PHASE_SEL_Pos (5U) 87 #define BLE_PHY_RX_CTRL1_LPF1_SAMPLE_PHASE_SEL_Msk (0x1UL << BLE_PHY_RX_CTRL1_LPF1_SAMPLE_PHASE_SEL_Pos) 88 #define BLE_PHY_RX_CTRL1_LPF1_SAMPLE_PHASE_SEL BLE_PHY_RX_CTRL1_LPF1_SAMPLE_PHASE_SEL_Msk 89 #define BLE_PHY_RX_CTRL1_RSSI_SAMPLE_SEL_Pos (6U) 90 #define BLE_PHY_RX_CTRL1_RSSI_SAMPLE_SEL_Msk (0x1UL << BLE_PHY_RX_CTRL1_RSSI_SAMPLE_SEL_Pos) 91 #define BLE_PHY_RX_CTRL1_RSSI_SAMPLE_SEL BLE_PHY_RX_CTRL1_RSSI_SAMPLE_SEL_Msk 92 #define BLE_PHY_RX_CTRL1_DEMOD_METHOD_Pos (7U) 93 #define BLE_PHY_RX_CTRL1_DEMOD_METHOD_Msk (0x1UL << BLE_PHY_RX_CTRL1_DEMOD_METHOD_Pos) 94 #define BLE_PHY_RX_CTRL1_DEMOD_METHOD BLE_PHY_RX_CTRL1_DEMOD_METHOD_Msk 95 #define BLE_PHY_RX_CTRL1_PHY_RX_DUMP_EN_Pos (8U) 96 #define BLE_PHY_RX_CTRL1_PHY_RX_DUMP_EN_Msk (0x1UL << BLE_PHY_RX_CTRL1_PHY_RX_DUMP_EN_Pos) 97 #define BLE_PHY_RX_CTRL1_PHY_RX_DUMP_EN BLE_PHY_RX_CTRL1_PHY_RX_DUMP_EN_Msk 98 #define BLE_PHY_RX_CTRL1_RX_DUMP_CLK_SEL_Pos (9U) 99 #define BLE_PHY_RX_CTRL1_RX_DUMP_CLK_SEL_Msk (0x3UL << BLE_PHY_RX_CTRL1_RX_DUMP_CLK_SEL_Pos) 100 #define BLE_PHY_RX_CTRL1_RX_DUMP_CLK_SEL BLE_PHY_RX_CTRL1_RX_DUMP_CLK_SEL_Msk 101 #define BLE_PHY_RX_CTRL1_RX_DUMP_DATA_SEL_Pos (11U) 102 #define BLE_PHY_RX_CTRL1_RX_DUMP_DATA_SEL_Msk (0xFUL << BLE_PHY_RX_CTRL1_RX_DUMP_DATA_SEL_Pos) 103 #define BLE_PHY_RX_CTRL1_RX_DUMP_DATA_SEL BLE_PHY_RX_CTRL1_RX_DUMP_DATA_SEL_Msk 104 #define BLE_PHY_RX_CTRL1_RX_DBG_TRIG_SEL_Pos (15U) 105 #define BLE_PHY_RX_CTRL1_RX_DBG_TRIG_SEL_Msk (0x3UL << BLE_PHY_RX_CTRL1_RX_DBG_TRIG_SEL_Pos) 106 #define BLE_PHY_RX_CTRL1_RX_DBG_TRIG_SEL BLE_PHY_RX_CTRL1_RX_DBG_TRIG_SEL_Msk 107 #define BLE_PHY_RX_CTRL1_RX_DBG_DATA_SEL_Pos (17U) 108 #define BLE_PHY_RX_CTRL1_RX_DBG_DATA_SEL_Msk (0xFUL << BLE_PHY_RX_CTRL1_RX_DBG_DATA_SEL_Pos) 109 #define BLE_PHY_RX_CTRL1_RX_DBG_DATA_SEL BLE_PHY_RX_CTRL1_RX_DBG_DATA_SEL_Msk 110 #define BLE_PHY_RX_CTRL1_RX_LOOPBACK_MODE_Pos (21U) 111 #define BLE_PHY_RX_CTRL1_RX_LOOPBACK_MODE_Msk (0x1UL << BLE_PHY_RX_CTRL1_RX_LOOPBACK_MODE_Pos) 112 #define BLE_PHY_RX_CTRL1_RX_LOOPBACK_MODE BLE_PHY_RX_CTRL1_RX_LOOPBACK_MODE_Msk 113 #define BLE_PHY_RX_CTRL1_RX_DUMP_Q_SEL_Pos (22U) 114 #define BLE_PHY_RX_CTRL1_RX_DUMP_Q_SEL_Msk (0x1UL << BLE_PHY_RX_CTRL1_RX_DUMP_Q_SEL_Pos) 115 #define BLE_PHY_RX_CTRL1_RX_DUMP_Q_SEL BLE_PHY_RX_CTRL1_RX_DUMP_Q_SEL_Msk 116 117 /************** Bit definition for BLE_PHY_RX_RCC_CTRL1 register **************/ 118 #define BLE_PHY_RX_RCC_CTRL1_FORCE_CLK_ON_AGC_Pos (0U) 119 #define BLE_PHY_RX_RCC_CTRL1_FORCE_CLK_ON_AGC_Msk (0x1UL << BLE_PHY_RX_RCC_CTRL1_FORCE_CLK_ON_AGC_Pos) 120 #define BLE_PHY_RX_RCC_CTRL1_FORCE_CLK_ON_AGC BLE_PHY_RX_RCC_CTRL1_FORCE_CLK_ON_AGC_Msk 121 #define BLE_PHY_RX_RCC_CTRL1_FORCE_RX_RESET_Pos (1U) 122 #define BLE_PHY_RX_RCC_CTRL1_FORCE_RX_RESET_Msk (0x1UL << BLE_PHY_RX_RCC_CTRL1_FORCE_RX_RESET_Pos) 123 #define BLE_PHY_RX_RCC_CTRL1_FORCE_RX_RESET BLE_PHY_RX_RCC_CTRL1_FORCE_RX_RESET_Msk 124 125 /*************** Bit definition for BLE_PHY_NOTCH_CFG1 register ***************/ 126 #define BLE_PHY_NOTCH_CFG1_NOTCH_B0_Pos (0U) 127 #define BLE_PHY_NOTCH_CFG1_NOTCH_B0_Msk (0x3FFFUL << BLE_PHY_NOTCH_CFG1_NOTCH_B0_Pos) 128 #define BLE_PHY_NOTCH_CFG1_NOTCH_B0 BLE_PHY_NOTCH_CFG1_NOTCH_B0_Msk 129 #define BLE_PHY_NOTCH_CFG1_NOTCH_B1_Pos (14U) 130 #define BLE_PHY_NOTCH_CFG1_NOTCH_B1_Msk (0x3FFFUL << BLE_PHY_NOTCH_CFG1_NOTCH_B1_Pos) 131 #define BLE_PHY_NOTCH_CFG1_NOTCH_B1 BLE_PHY_NOTCH_CFG1_NOTCH_B1_Msk 132 133 /*************** Bit definition for BLE_PHY_NOTCH_CFG2 register ***************/ 134 #define BLE_PHY_NOTCH_CFG2_NOTCH_A2_Pos (0U) 135 #define BLE_PHY_NOTCH_CFG2_NOTCH_A2_Msk (0x3FFFUL << BLE_PHY_NOTCH_CFG2_NOTCH_A2_Pos) 136 #define BLE_PHY_NOTCH_CFG2_NOTCH_A2 BLE_PHY_NOTCH_CFG2_NOTCH_A2_Msk 137 138 /*************** Bit definition for BLE_PHY_NOTCH_CFG3 register ***************/ 139 #define BLE_PHY_NOTCH_CFG3_CHNL_NOTCH_EN0_Pos (0U) 140 #define BLE_PHY_NOTCH_CFG3_CHNL_NOTCH_EN0_Msk (0xFFFFFFFFUL << BLE_PHY_NOTCH_CFG3_CHNL_NOTCH_EN0_Pos) 141 #define BLE_PHY_NOTCH_CFG3_CHNL_NOTCH_EN0 BLE_PHY_NOTCH_CFG3_CHNL_NOTCH_EN0_Msk 142 143 /*************** Bit definition for BLE_PHY_NOTCH_CFG4 register ***************/ 144 #define BLE_PHY_NOTCH_CFG4_CHNL_NOTCH_EN1_Pos (0U) 145 #define BLE_PHY_NOTCH_CFG4_CHNL_NOTCH_EN1_Msk (0xFFUL << BLE_PHY_NOTCH_CFG4_CHNL_NOTCH_EN1_Pos) 146 #define BLE_PHY_NOTCH_CFG4_CHNL_NOTCH_EN1 BLE_PHY_NOTCH_CFG4_CHNL_NOTCH_EN1_Msk 147 #define BLE_PHY_NOTCH_CFG4_NOTCH_RSSI_THD_Pos (8U) 148 #define BLE_PHY_NOTCH_CFG4_NOTCH_RSSI_THD_Msk (0xFFUL << BLE_PHY_NOTCH_CFG4_NOTCH_RSSI_THD_Pos) 149 #define BLE_PHY_NOTCH_CFG4_NOTCH_RSSI_THD BLE_PHY_NOTCH_CFG4_NOTCH_RSSI_THD_Msk 150 151 /************** Bit definition for BLE_PHY_INTERP_CFG1 register ***************/ 152 #define BLE_PHY_INTERP_CFG1_INTERP_EN_U_Pos (0U) 153 #define BLE_PHY_INTERP_CFG1_INTERP_EN_U_Msk (0x1UL << BLE_PHY_INTERP_CFG1_INTERP_EN_U_Pos) 154 #define BLE_PHY_INTERP_CFG1_INTERP_EN_U BLE_PHY_INTERP_CFG1_INTERP_EN_U_Msk 155 #define BLE_PHY_INTERP_CFG1_TIMING_FACTOR_Pos (1U) 156 #define BLE_PHY_INTERP_CFG1_TIMING_FACTOR_Msk (0x7FUL << BLE_PHY_INTERP_CFG1_TIMING_FACTOR_Pos) 157 #define BLE_PHY_INTERP_CFG1_TIMING_FACTOR BLE_PHY_INTERP_CFG1_TIMING_FACTOR_Msk 158 #define BLE_PHY_INTERP_CFG1_INTERP_METHOD_U_Pos (8U) 159 #define BLE_PHY_INTERP_CFG1_INTERP_METHOD_U_Msk (0x1UL << BLE_PHY_INTERP_CFG1_INTERP_METHOD_U_Pos) 160 #define BLE_PHY_INTERP_CFG1_INTERP_METHOD_U BLE_PHY_INTERP_CFG1_INTERP_METHOD_U_Msk 161 #define BLE_PHY_INTERP_CFG1_TED_MU_P_U_Pos (9U) 162 #define BLE_PHY_INTERP_CFG1_TED_MU_P_U_Msk (0xFUL << BLE_PHY_INTERP_CFG1_TED_MU_P_U_Pos) 163 #define BLE_PHY_INTERP_CFG1_TED_MU_P_U BLE_PHY_INTERP_CFG1_TED_MU_P_U_Msk 164 #define BLE_PHY_INTERP_CFG1_TED_MU_F_U_Pos (13U) 165 #define BLE_PHY_INTERP_CFG1_TED_MU_F_U_Msk (0xFUL << BLE_PHY_INTERP_CFG1_TED_MU_F_U_Pos) 166 #define BLE_PHY_INTERP_CFG1_TED_MU_F_U BLE_PHY_INTERP_CFG1_TED_MU_F_U_Msk 167 #define BLE_PHY_INTERP_CFG1_INTERP_METHOD_C_Pos (17U) 168 #define BLE_PHY_INTERP_CFG1_INTERP_METHOD_C_Msk (0x1UL << BLE_PHY_INTERP_CFG1_INTERP_METHOD_C_Pos) 169 #define BLE_PHY_INTERP_CFG1_INTERP_METHOD_C BLE_PHY_INTERP_CFG1_INTERP_METHOD_C_Msk 170 #define BLE_PHY_INTERP_CFG1_TED_MU_P_C_Pos (18U) 171 #define BLE_PHY_INTERP_CFG1_TED_MU_P_C_Msk (0xFUL << BLE_PHY_INTERP_CFG1_TED_MU_P_C_Pos) 172 #define BLE_PHY_INTERP_CFG1_TED_MU_P_C BLE_PHY_INTERP_CFG1_TED_MU_P_C_Msk 173 #define BLE_PHY_INTERP_CFG1_TED_MU_F_C_Pos (22U) 174 #define BLE_PHY_INTERP_CFG1_TED_MU_F_C_Msk (0xFUL << BLE_PHY_INTERP_CFG1_TED_MU_F_C_Pos) 175 #define BLE_PHY_INTERP_CFG1_TED_MU_F_C BLE_PHY_INTERP_CFG1_TED_MU_F_C_Msk 176 #define BLE_PHY_INTERP_CFG1_INTERP_EN_C_Pos (26U) 177 #define BLE_PHY_INTERP_CFG1_INTERP_EN_C_Msk (0x1UL << BLE_PHY_INTERP_CFG1_INTERP_EN_C_Pos) 178 #define BLE_PHY_INTERP_CFG1_INTERP_EN_C BLE_PHY_INTERP_CFG1_INTERP_EN_C_Msk 179 180 /*************** Bit definition for BLE_PHY_MIXER_CFG1 register ***************/ 181 #define BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_1_Pos (0U) 182 #define BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_1_Msk (0x3FFUL << BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_1_Pos) 183 #define BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_1 BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_1_Msk 184 #define BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_2_Pos (10U) 185 #define BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_2_Msk (0x3FFUL << BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_2_Pos) 186 #define BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_2 BLE_PHY_MIXER_CFG1_RX_MIXER_PHASE_2_Msk 187 188 /************** Bit definition for BLE_PHY_PKTDET_CFG1 register ***************/ 189 #define BLE_PHY_PKTDET_CFG1_PKTDET_THD_Pos (0U) 190 #define BLE_PHY_PKTDET_CFG1_PKTDET_THD_Msk (0xFFFFUL << BLE_PHY_PKTDET_CFG1_PKTDET_THD_Pos) 191 #define BLE_PHY_PKTDET_CFG1_PKTDET_THD BLE_PHY_PKTDET_CFG1_PKTDET_THD_Msk 192 #define BLE_PHY_PKTDET_CFG1_PKT_CNT_THD_Pos (16U) 193 #define BLE_PHY_PKTDET_CFG1_PKT_CNT_THD_Msk (0xFFUL << BLE_PHY_PKTDET_CFG1_PKT_CNT_THD_Pos) 194 #define BLE_PHY_PKTDET_CFG1_PKT_CNT_THD BLE_PHY_PKTDET_CFG1_PKT_CNT_THD_Msk 195 #define BLE_PHY_PKTDET_CFG1_HARD_CORR_THD_Pos (24U) 196 #define BLE_PHY_PKTDET_CFG1_HARD_CORR_THD_Msk (0xFUL << BLE_PHY_PKTDET_CFG1_HARD_CORR_THD_Pos) 197 #define BLE_PHY_PKTDET_CFG1_HARD_CORR_THD BLE_PHY_PKTDET_CFG1_HARD_CORR_THD_Msk 198 199 /*************** Bit definition for BLE_PHY_DEMOD_CFG1 register ***************/ 200 #define BLE_PHY_DEMOD_CFG1_MU_ERR_Pos (0U) 201 #define BLE_PHY_DEMOD_CFG1_MU_ERR_Msk (0x3FFUL << BLE_PHY_DEMOD_CFG1_MU_ERR_Pos) 202 #define BLE_PHY_DEMOD_CFG1_MU_ERR BLE_PHY_DEMOD_CFG1_MU_ERR_Msk 203 #define BLE_PHY_DEMOD_CFG1_MU_DC_Pos (10U) 204 #define BLE_PHY_DEMOD_CFG1_MU_DC_Msk (0x3FFUL << BLE_PHY_DEMOD_CFG1_MU_DC_Pos) 205 #define BLE_PHY_DEMOD_CFG1_MU_DC BLE_PHY_DEMOD_CFG1_MU_DC_Msk 206 #define BLE_PHY_DEMOD_CFG1_DEMOD_G_Pos (20U) 207 #define BLE_PHY_DEMOD_CFG1_DEMOD_G_Msk (0x7FFUL << BLE_PHY_DEMOD_CFG1_DEMOD_G_Pos) 208 #define BLE_PHY_DEMOD_CFG1_DEMOD_G BLE_PHY_DEMOD_CFG1_DEMOD_G_Msk 209 210 /*************** Bit definition for BLE_PHY_DEMOD_CFG2 register ***************/ 211 #define BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_0_Pos (0U) 212 #define BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_0_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_0_Pos) 213 #define BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_0 BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_0_Msk 214 #define BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_1_Pos (12U) 215 #define BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_1_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_1_Pos) 216 #define BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_1 BLE_PHY_DEMOD_CFG2_DEMOD_PHASE_1_Msk 217 218 /*************** Bit definition for BLE_PHY_DEMOD_CFG3 register ***************/ 219 #define BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_2_Pos (0U) 220 #define BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_2_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_2_Pos) 221 #define BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_2 BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_2_Msk 222 #define BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_3_Pos (12U) 223 #define BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_3_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_3_Pos) 224 #define BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_3 BLE_PHY_DEMOD_CFG3_DEMOD_PHASE_3_Msk 225 226 /*************** Bit definition for BLE_PHY_DEMOD_CFG4 register ***************/ 227 #define BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_4_Pos (0U) 228 #define BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_4_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_4_Pos) 229 #define BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_4 BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_4_Msk 230 #define BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_5_Pos (12U) 231 #define BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_5_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_5_Pos) 232 #define BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_5 BLE_PHY_DEMOD_CFG4_DEMOD_PHASE_5_Msk 233 234 /*************** Bit definition for BLE_PHY_DEMOD_CFG5 register ***************/ 235 #define BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_6_Pos (0U) 236 #define BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_6_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_6_Pos) 237 #define BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_6 BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_6_Msk 238 #define BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_7_Pos (12U) 239 #define BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_7_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_7_Pos) 240 #define BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_7 BLE_PHY_DEMOD_CFG5_DEMOD_PHASE_7_Msk 241 242 /*************** Bit definition for BLE_PHY_DEMOD_CFG6 register ***************/ 243 #define BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_0_Pos (0U) 244 #define BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_0_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_0_Pos) 245 #define BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_0 BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_0_Msk 246 #define BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_1_Pos (12U) 247 #define BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_1_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_1_Pos) 248 #define BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_1 BLE_PHY_DEMOD_CFG6_DEMOD_PHASE_IDEAL_1_Msk 249 250 /*************** Bit definition for BLE_PHY_DEMOD_CFG7 register ***************/ 251 #define BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_2_Pos (0U) 252 #define BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_2_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_2_Pos) 253 #define BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_2 BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_2_Msk 254 #define BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_3_Pos (12U) 255 #define BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_3_Msk (0xFFFUL << BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_3_Pos) 256 #define BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_3 BLE_PHY_DEMOD_CFG7_DEMOD_PHASE_IDEAL_3_Msk 257 258 259 /*************** Bit definition for BLE_PHY_CODED_CFG1 register ***************/ 260 #define BLE_PHY_CODED_CFG1_HARD_ACCESS_CORR_THD_Pos (0U) 261 #define BLE_PHY_CODED_CFG1_HARD_ACCESS_CORR_THD_Msk (0xFFUL << BLE_PHY_CODED_CFG1_HARD_ACCESS_CORR_THD_Pos) 262 #define BLE_PHY_CODED_CFG1_HARD_ACCESS_CORR_THD BLE_PHY_CODED_CFG1_HARD_ACCESS_CORR_THD_Msk 263 #define BLE_PHY_CODED_CFG1_SOFT_ACCESS_CORR_THD_Pos (8U) 264 #define BLE_PHY_CODED_CFG1_SOFT_ACCESS_CORR_THD_Msk (0xFFFUL << BLE_PHY_CODED_CFG1_SOFT_ACCESS_CORR_THD_Pos) 265 #define BLE_PHY_CODED_CFG1_SOFT_ACCESS_CORR_THD BLE_PHY_CODED_CFG1_SOFT_ACCESS_CORR_THD_Msk 266 #define BLE_PHY_CODED_CFG1_PHASE_UNWRAP_THD_Pos (20U) 267 #define BLE_PHY_CODED_CFG1_PHASE_UNWRAP_THD_Msk (0x1FUL << BLE_PHY_CODED_CFG1_PHASE_UNWRAP_THD_Pos) 268 #define BLE_PHY_CODED_CFG1_PHASE_UNWRAP_THD BLE_PHY_CODED_CFG1_PHASE_UNWRAP_THD_Msk 269 #define BLE_PHY_CODED_CFG1_PREAMBLE_LEN_SEL_Pos (25U) 270 #define BLE_PHY_CODED_CFG1_PREAMBLE_LEN_SEL_Msk (0x7UL << BLE_PHY_CODED_CFG1_PREAMBLE_LEN_SEL_Pos) 271 #define BLE_PHY_CODED_CFG1_PREAMBLE_LEN_SEL BLE_PHY_CODED_CFG1_PREAMBLE_LEN_SEL_Msk 272 #define BLE_PHY_CODED_CFG1_PHASE_DIFF_FP_SEL_Pos (28U) 273 #define BLE_PHY_CODED_CFG1_PHASE_DIFF_FP_SEL_Msk (0x3UL << BLE_PHY_CODED_CFG1_PHASE_DIFF_FP_SEL_Pos) 274 #define BLE_PHY_CODED_CFG1_PHASE_DIFF_FP_SEL BLE_PHY_CODED_CFG1_PHASE_DIFF_FP_SEL_Msk 275 276 /*************** Bit definition for BLE_PHY_CODED_CFG2 register ***************/ 277 #define BLE_PHY_CODED_CFG2_HARD_CORR_THD_CODED_Pos (0U) 278 #define BLE_PHY_CODED_CFG2_HARD_CORR_THD_CODED_Msk (0x1FFUL << BLE_PHY_CODED_CFG2_HARD_CORR_THD_CODED_Pos) 279 #define BLE_PHY_CODED_CFG2_HARD_CORR_THD_CODED BLE_PHY_CODED_CFG2_HARD_CORR_THD_CODED_Msk 280 #define BLE_PHY_CODED_CFG2_SOFT_CORR_THD_CODED_Pos (9U) 281 #define BLE_PHY_CODED_CFG2_SOFT_CORR_THD_CODED_Msk (0xFFFUL << BLE_PHY_CODED_CFG2_SOFT_CORR_THD_CODED_Pos) 282 #define BLE_PHY_CODED_CFG2_SOFT_CORR_THD_CODED BLE_PHY_CODED_CFG2_SOFT_CORR_THD_CODED_Msk 283 284 /*************** Bit definition for BLE_PHY_CODED_CFG3 register ***************/ 285 #define BLE_PHY_CODED_CFG3_CI_G_Pos (0U) 286 #define BLE_PHY_CODED_CFG3_CI_G_Msk (0x3FFUL << BLE_PHY_CODED_CFG3_CI_G_Pos) 287 #define BLE_PHY_CODED_CFG3_CI_G BLE_PHY_CODED_CFG3_CI_G_Msk 288 #define BLE_PHY_CODED_CFG3_CI_MU_DC_Pos (10U) 289 #define BLE_PHY_CODED_CFG3_CI_MU_DC_Msk (0x3FFUL << BLE_PHY_CODED_CFG3_CI_MU_DC_Pos) 290 #define BLE_PHY_CODED_CFG3_CI_MU_DC BLE_PHY_CODED_CFG3_CI_MU_DC_Msk 291 #define BLE_PHY_CODED_CFG3_CI_MU_ERR_Pos (20U) 292 #define BLE_PHY_CODED_CFG3_CI_MU_ERR_Msk (0x3FFUL << BLE_PHY_CODED_CFG3_CI_MU_ERR_Pos) 293 #define BLE_PHY_CODED_CFG3_CI_MU_ERR BLE_PHY_CODED_CFG3_CI_MU_ERR_Msk 294 295 /*************** Bit definition for BLE_PHY_CODED_CFG4 register ***************/ 296 #define BLE_PHY_CODED_CFG4_DEC_G_Pos (0U) 297 #define BLE_PHY_CODED_CFG4_DEC_G_Msk (0x3FFUL << BLE_PHY_CODED_CFG4_DEC_G_Pos) 298 #define BLE_PHY_CODED_CFG4_DEC_G BLE_PHY_CODED_CFG4_DEC_G_Msk 299 #define BLE_PHY_CODED_CFG4_DEC_MU_DC_Pos (10U) 300 #define BLE_PHY_CODED_CFG4_DEC_MU_DC_Msk (0x3FFUL << BLE_PHY_CODED_CFG4_DEC_MU_DC_Pos) 301 #define BLE_PHY_CODED_CFG4_DEC_MU_DC BLE_PHY_CODED_CFG4_DEC_MU_DC_Msk 302 #define BLE_PHY_CODED_CFG4_DEC_MU_ERR_Pos (20U) 303 #define BLE_PHY_CODED_CFG4_DEC_MU_ERR_Msk (0x3FFUL << BLE_PHY_CODED_CFG4_DEC_MU_ERR_Pos) 304 #define BLE_PHY_CODED_CFG4_DEC_MU_ERR BLE_PHY_CODED_CFG4_DEC_MU_ERR_Msk 305 306 /*************** Bit definition for BLE_PHY_RX_STATUS1 register ***************/ 307 #define BLE_PHY_RX_STATUS1_PKT_DETECTED_Pos (0U) 308 #define BLE_PHY_RX_STATUS1_PKT_DETECTED_Msk (0x1UL << BLE_PHY_RX_STATUS1_PKT_DETECTED_Pos) 309 #define BLE_PHY_RX_STATUS1_PKT_DETECTED BLE_PHY_RX_STATUS1_PKT_DETECTED_Msk 310 #define BLE_PHY_RX_STATUS1_CFO_PHASE_Pos (1U) 311 #define BLE_PHY_RX_STATUS1_CFO_PHASE_Msk (0xFFFUL << BLE_PHY_RX_STATUS1_CFO_PHASE_Pos) 312 #define BLE_PHY_RX_STATUS1_CFO_PHASE BLE_PHY_RX_STATUS1_CFO_PHASE_Msk 313 314 /**************** Bit definition for BLE_PHY_AGC_CTRL register ****************/ 315 #define BLE_PHY_AGC_CTRL_AGC_ENABLE_Pos (0U) 316 #define BLE_PHY_AGC_CTRL_AGC_ENABLE_Msk (0x1UL << BLE_PHY_AGC_CTRL_AGC_ENABLE_Pos) 317 #define BLE_PHY_AGC_CTRL_AGC_ENABLE BLE_PHY_AGC_CTRL_AGC_ENABLE_Msk 318 #define BLE_PHY_AGC_CTRL_AGC_MODE_Pos (1U) 319 #define BLE_PHY_AGC_CTRL_AGC_MODE_Msk (0x1UL << BLE_PHY_AGC_CTRL_AGC_MODE_Pos) 320 #define BLE_PHY_AGC_CTRL_AGC_MODE BLE_PHY_AGC_CTRL_AGC_MODE_Msk 321 #define BLE_PHY_AGC_CTRL_DIG_GAIN_EN_Pos (2U) 322 #define BLE_PHY_AGC_CTRL_DIG_GAIN_EN_Msk (0x1UL << BLE_PHY_AGC_CTRL_DIG_GAIN_EN_Pos) 323 #define BLE_PHY_AGC_CTRL_DIG_GAIN_EN BLE_PHY_AGC_CTRL_DIG_GAIN_EN_Msk 324 #define BLE_PHY_AGC_CTRL_AGC_VGAADJ_EN_Pos (3U) 325 #define BLE_PHY_AGC_CTRL_AGC_VGAADJ_EN_Msk (0x1UL << BLE_PHY_AGC_CTRL_AGC_VGAADJ_EN_Pos) 326 #define BLE_PHY_AGC_CTRL_AGC_VGAADJ_EN BLE_PHY_AGC_CTRL_AGC_VGAADJ_EN_Msk 327 328 /**************** Bit definition for BLE_PHY_AGC_CFG1 register ****************/ 329 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD0_Pos (0U) 330 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD0_Msk (0x3FFUL << BLE_PHY_AGC_CFG1_ADC_MAG_THD0_Pos) 331 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD0 BLE_PHY_AGC_CFG1_ADC_MAG_THD0_Msk 332 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD1_Pos (10U) 333 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD1_Msk (0x3FFUL << BLE_PHY_AGC_CFG1_ADC_MAG_THD1_Pos) 334 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD1 BLE_PHY_AGC_CFG1_ADC_MAG_THD1_Msk 335 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD2_Pos (20U) 336 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD2_Msk (0x3FFUL << BLE_PHY_AGC_CFG1_ADC_MAG_THD2_Pos) 337 #define BLE_PHY_AGC_CFG1_ADC_MAG_THD2 BLE_PHY_AGC_CFG1_ADC_MAG_THD2_Msk 338 339 /**************** Bit definition for BLE_PHY_AGC_CFG2 register ****************/ 340 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD0_Pos (0U) 341 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD0_Msk (0xFUL << BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD0_Pos) 342 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD0 BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD0_Msk 343 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD1_Pos (4U) 344 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD1_Msk (0xFUL << BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD1_Pos) 345 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD1 BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD1_Msk 346 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD2_Pos (8U) 347 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD2_Msk (0xFUL << BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD2_Pos) 348 #define BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD2 BLE_PHY_AGC_CFG2_ADC_MAG_CNT_THD2_Msk 349 #define BLE_PHY_AGC_CFG2_ADC_MAG_SET_Pos (12U) 350 #define BLE_PHY_AGC_CFG2_ADC_MAG_SET_Msk (0x3FFUL << BLE_PHY_AGC_CFG2_ADC_MAG_SET_Pos) 351 #define BLE_PHY_AGC_CFG2_ADC_MAG_SET BLE_PHY_AGC_CFG2_ADC_MAG_SET_Msk 352 353 /**************** Bit definition for BLE_PHY_AGC_CFG3 register ****************/ 354 #define BLE_PHY_AGC_CFG3_ADC_SAT_THD_Pos (0U) 355 #define BLE_PHY_AGC_CFG3_ADC_SAT_THD_Msk (0x3FFUL << BLE_PHY_AGC_CFG3_ADC_SAT_THD_Pos) 356 #define BLE_PHY_AGC_CFG3_ADC_SAT_THD BLE_PHY_AGC_CFG3_ADC_SAT_THD_Msk 357 #define BLE_PHY_AGC_CFG3_ADC_SAT_NUM_Pos (10U) 358 #define BLE_PHY_AGC_CFG3_ADC_SAT_NUM_Msk (0xFUL << BLE_PHY_AGC_CFG3_ADC_SAT_NUM_Pos) 359 #define BLE_PHY_AGC_CFG3_ADC_SAT_NUM BLE_PHY_AGC_CFG3_ADC_SAT_NUM_Msk 360 #define BLE_PHY_AGC_CFG3_DIG_GAIN_LOW_Pos (14U) 361 #define BLE_PHY_AGC_CFG3_DIG_GAIN_LOW_Msk (0x3FUL << BLE_PHY_AGC_CFG3_DIG_GAIN_LOW_Pos) 362 #define BLE_PHY_AGC_CFG3_DIG_GAIN_LOW BLE_PHY_AGC_CFG3_DIG_GAIN_LOW_Msk 363 #define BLE_PHY_AGC_CFG3_DIG_GAIN_HIGH_Pos (20U) 364 #define BLE_PHY_AGC_CFG3_DIG_GAIN_HIGH_Msk (0x3FUL << BLE_PHY_AGC_CFG3_DIG_GAIN_HIGH_Pos) 365 #define BLE_PHY_AGC_CFG3_DIG_GAIN_HIGH BLE_PHY_AGC_CFG3_DIG_GAIN_HIGH_Msk 366 367 /**************** Bit definition for BLE_PHY_AGC_CFG4 register ****************/ 368 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_THD_Pos (0U) 369 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_THD_Msk (0xFUL << BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_THD_Pos) 370 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_THD BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_THD_Msk 371 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_THD_Pos (4U) 372 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_THD_Msk (0x3UL << BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_THD_Pos) 373 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_THD BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_THD_Msk 374 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_THD_Pos (6U) 375 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_THD_Msk (0xFUL << BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_THD_Pos) 376 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_THD BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_THD_Msk 377 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_INIT_Pos (10U) 378 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_INIT_Msk (0xFUL << BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_INIT_Pos) 379 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_INIT BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_INIT_Msk 380 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_INIT_Pos (14U) 381 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_INIT_Msk (0x3UL << BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_INIT_Pos) 382 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_INIT BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_INIT_Msk 383 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_INIT_Pos (16U) 384 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_INIT_Msk (0xFUL << BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_INIT_Pos) 385 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_INIT BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_INIT_Msk 386 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_STEP_Pos (20U) 387 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_STEP_Msk (0xFUL << BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_STEP_Pos) 388 #define BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_STEP BLE_PHY_AGC_CFG4_LNA_MIXER_GAIN_INDEX_STEP_Msk 389 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_STEP_Pos (24U) 390 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_STEP_Msk (0x3UL << BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_STEP_Pos) 391 #define BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_STEP BLE_PHY_AGC_CFG4_CBPF_GAIN_INDEX_STEP_Msk 392 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_STEP_Pos (26U) 393 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_STEP_Msk (0xFUL << BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_STEP_Pos) 394 #define BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_STEP BLE_PHY_AGC_CFG4_VGA_GAIN_INDEX_STEP_Msk 395 396 /**************** Bit definition for BLE_PHY_AGC_CFG5 register ****************/ 397 #define BLE_PHY_AGC_CFG5_AGC_CBPF_GAIN_INDEX_SETTING0_Pos (0U) 398 #define BLE_PHY_AGC_CFG5_AGC_CBPF_GAIN_INDEX_SETTING0_Msk (0x3UL << BLE_PHY_AGC_CFG5_AGC_CBPF_GAIN_INDEX_SETTING0_Pos) 399 #define BLE_PHY_AGC_CFG5_AGC_CBPF_GAIN_INDEX_SETTING0 BLE_PHY_AGC_CFG5_AGC_CBPF_GAIN_INDEX_SETTING0_Msk 400 #define BLE_PHY_AGC_CFG5_AGC_VGA_GAIN_INDEX_SETTING0_Pos (2U) 401 #define BLE_PHY_AGC_CFG5_AGC_VGA_GAIN_INDEX_SETTING0_Msk (0xFUL << BLE_PHY_AGC_CFG5_AGC_VGA_GAIN_INDEX_SETTING0_Pos) 402 #define BLE_PHY_AGC_CFG5_AGC_VGA_GAIN_INDEX_SETTING0 BLE_PHY_AGC_CFG5_AGC_VGA_GAIN_INDEX_SETTING0_Msk 403 404 /**************** Bit definition for BLE_PHY_AGC_CFG6 register ****************/ 405 #define BLE_PHY_AGC_CFG6_AGC_DELAY_RESET_1_Pos (0U) 406 #define BLE_PHY_AGC_CFG6_AGC_DELAY_RESET_1_Msk (0x7FUL << BLE_PHY_AGC_CFG6_AGC_DELAY_RESET_1_Pos) 407 #define BLE_PHY_AGC_CFG6_AGC_DELAY_RESET_1 BLE_PHY_AGC_CFG6_AGC_DELAY_RESET_1_Msk 408 #define BLE_PHY_AGC_CFG6_AGC_DELAY_PKDET_1_Pos (7U) 409 #define BLE_PHY_AGC_CFG6_AGC_DELAY_PKDET_1_Msk (0x7FUL << BLE_PHY_AGC_CFG6_AGC_DELAY_PKDET_1_Pos) 410 #define BLE_PHY_AGC_CFG6_AGC_DELAY_PKDET_1 BLE_PHY_AGC_CFG6_AGC_DELAY_PKDET_1_Msk 411 #define BLE_PHY_AGC_CFG6_AGC_DELAY_LNA_1_Pos (14U) 412 #define BLE_PHY_AGC_CFG6_AGC_DELAY_LNA_1_Msk (0x7FUL << BLE_PHY_AGC_CFG6_AGC_DELAY_LNA_1_Pos) 413 #define BLE_PHY_AGC_CFG6_AGC_DELAY_LNA_1 BLE_PHY_AGC_CFG6_AGC_DELAY_LNA_1_Msk 414 #define BLE_PHY_AGC_CFG6_AGC_DELAY_DIG_1_Pos (21U) 415 #define BLE_PHY_AGC_CFG6_AGC_DELAY_DIG_1_Msk (0x7FUL << BLE_PHY_AGC_CFG6_AGC_DELAY_DIG_1_Pos) 416 #define BLE_PHY_AGC_CFG6_AGC_DELAY_DIG_1 BLE_PHY_AGC_CFG6_AGC_DELAY_DIG_1_Msk 417 418 /**************** Bit definition for BLE_PHY_AGC_CFG7 register ****************/ 419 #define BLE_PHY_AGC_CFG7_AGC_DELAY_RESET_2_Pos (0U) 420 #define BLE_PHY_AGC_CFG7_AGC_DELAY_RESET_2_Msk (0x7FUL << BLE_PHY_AGC_CFG7_AGC_DELAY_RESET_2_Pos) 421 #define BLE_PHY_AGC_CFG7_AGC_DELAY_RESET_2 BLE_PHY_AGC_CFG7_AGC_DELAY_RESET_2_Msk 422 #define BLE_PHY_AGC_CFG7_AGC_DELAY_PKDET_2_Pos (7U) 423 #define BLE_PHY_AGC_CFG7_AGC_DELAY_PKDET_2_Msk (0x7FUL << BLE_PHY_AGC_CFG7_AGC_DELAY_PKDET_2_Pos) 424 #define BLE_PHY_AGC_CFG7_AGC_DELAY_PKDET_2 BLE_PHY_AGC_CFG7_AGC_DELAY_PKDET_2_Msk 425 #define BLE_PHY_AGC_CFG7_AGC_DELAY_LNA_2_Pos (14U) 426 #define BLE_PHY_AGC_CFG7_AGC_DELAY_LNA_2_Msk (0x7FUL << BLE_PHY_AGC_CFG7_AGC_DELAY_LNA_2_Pos) 427 #define BLE_PHY_AGC_CFG7_AGC_DELAY_LNA_2 BLE_PHY_AGC_CFG7_AGC_DELAY_LNA_2_Msk 428 #define BLE_PHY_AGC_CFG7_AGC_DELAY_DIG_2_Pos (21U) 429 #define BLE_PHY_AGC_CFG7_AGC_DELAY_DIG_2_Msk (0x7FUL << BLE_PHY_AGC_CFG7_AGC_DELAY_DIG_2_Pos) 430 #define BLE_PHY_AGC_CFG7_AGC_DELAY_DIG_2 BLE_PHY_AGC_CFG7_AGC_DELAY_DIG_2_Msk 431 432 /**************** Bit definition for BLE_PHY_AGC_CFG8 register ****************/ 433 #define BLE_PHY_AGC_CFG8_AGC_DELAY_CBPF_1_Pos (0U) 434 #define BLE_PHY_AGC_CFG8_AGC_DELAY_CBPF_1_Msk (0x7FUL << BLE_PHY_AGC_CFG8_AGC_DELAY_CBPF_1_Pos) 435 #define BLE_PHY_AGC_CFG8_AGC_DELAY_CBPF_1 BLE_PHY_AGC_CFG8_AGC_DELAY_CBPF_1_Msk 436 #define BLE_PHY_AGC_CFG8_AGC_DELAY_ADC_1_Pos (7U) 437 #define BLE_PHY_AGC_CFG8_AGC_DELAY_ADC_1_Msk (0x7FUL << BLE_PHY_AGC_CFG8_AGC_DELAY_ADC_1_Pos) 438 #define BLE_PHY_AGC_CFG8_AGC_DELAY_ADC_1 BLE_PHY_AGC_CFG8_AGC_DELAY_ADC_1_Msk 439 #define BLE_PHY_AGC_CFG8_DIG_GAIN_WINDOW_1_Pos (14U) 440 #define BLE_PHY_AGC_CFG8_DIG_GAIN_WINDOW_1_Msk (0x7FUL << BLE_PHY_AGC_CFG8_DIG_GAIN_WINDOW_1_Pos) 441 #define BLE_PHY_AGC_CFG8_DIG_GAIN_WINDOW_1 BLE_PHY_AGC_CFG8_DIG_GAIN_WINDOW_1_Msk 442 #define BLE_PHY_AGC_CFG8_ADC_POWER_TARGET_Pos (21U) 443 #define BLE_PHY_AGC_CFG8_ADC_POWER_TARGET_Msk (0x7FUL << BLE_PHY_AGC_CFG8_ADC_POWER_TARGET_Pos) 444 #define BLE_PHY_AGC_CFG8_ADC_POWER_TARGET BLE_PHY_AGC_CFG8_ADC_POWER_TARGET_Msk 445 446 /**************** Bit definition for BLE_PHY_AGC_CFG9 register ****************/ 447 #define BLE_PHY_AGC_CFG9_AGC_DELAY_CBPF_2_Pos (0U) 448 #define BLE_PHY_AGC_CFG9_AGC_DELAY_CBPF_2_Msk (0x7FUL << BLE_PHY_AGC_CFG9_AGC_DELAY_CBPF_2_Pos) 449 #define BLE_PHY_AGC_CFG9_AGC_DELAY_CBPF_2 BLE_PHY_AGC_CFG9_AGC_DELAY_CBPF_2_Msk 450 #define BLE_PHY_AGC_CFG9_AGC_DELAY_ADC_2_Pos (7U) 451 #define BLE_PHY_AGC_CFG9_AGC_DELAY_ADC_2_Msk (0x7FUL << BLE_PHY_AGC_CFG9_AGC_DELAY_ADC_2_Pos) 452 #define BLE_PHY_AGC_CFG9_AGC_DELAY_ADC_2 BLE_PHY_AGC_CFG9_AGC_DELAY_ADC_2_Msk 453 #define BLE_PHY_AGC_CFG9_DIG_GAIN_WINDOW_2_Pos (14U) 454 #define BLE_PHY_AGC_CFG9_DIG_GAIN_WINDOW_2_Msk (0x7FUL << BLE_PHY_AGC_CFG9_DIG_GAIN_WINDOW_2_Pos) 455 #define BLE_PHY_AGC_CFG9_DIG_GAIN_WINDOW_2 BLE_PHY_AGC_CFG9_DIG_GAIN_WINDOW_2_Msk 456 457 /*************** Bit definition for BLE_PHY_AGC_CFG10 register ****************/ 458 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET1_1_Pos (0U) 459 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET1_1_Msk (0x7FUL << BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET1_1_Pos) 460 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET1_1 BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET1_1_Msk 461 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD1_1_Pos (7U) 462 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD1_1_Msk (0x7FUL << BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD1_1_Pos) 463 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD1_1 BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD1_1_Msk 464 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET2_1_Pos (14U) 465 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET2_1_Msk (0x7FUL << BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET2_1_Pos) 466 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET2_1 BLE_PHY_AGC_CFG10_AGC_PEAKDET_TIMER_SET2_1_Msk 467 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD2_1_Pos (21U) 468 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD2_1_Msk (0x7FUL << BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD2_1_Pos) 469 #define BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD2_1 BLE_PHY_AGC_CFG10_AGC_PEAKDET_CNT_THD2_1_Msk 470 471 /*************** Bit definition for BLE_PHY_AGC_CFG11 register ****************/ 472 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET1_2_Pos (0U) 473 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET1_2_Msk (0x7FUL << BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET1_2_Pos) 474 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET1_2 BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET1_2_Msk 475 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD1_2_Pos (7U) 476 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD1_2_Msk (0x7FUL << BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD1_2_Pos) 477 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD1_2 BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD1_2_Msk 478 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET2_2_Pos (14U) 479 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET2_2_Msk (0x7FUL << BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET2_2_Pos) 480 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET2_2 BLE_PHY_AGC_CFG11_AGC_PEAKDET_TIMER_SET2_2_Msk 481 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD2_2_Pos (21U) 482 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD2_2_Msk (0x7FUL << BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD2_2_Pos) 483 #define BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD2_2 BLE_PHY_AGC_CFG11_AGC_PEAKDET_CNT_THD2_2_Msk 484 485 /*************** Bit definition for BLE_PHY_AGC_CFG12 register ****************/ 486 #define BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_1_Pos (0U) 487 #define BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_1_Msk (0x7FUL << BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_1_Pos) 488 #define BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_1 BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_1_Msk 489 #define BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_2_Pos (7U) 490 #define BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_2_Msk (0x7FUL << BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_2_Pos) 491 #define BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_2 BLE_PHY_AGC_CFG12_AGC_URUN_WINDOW_2_Msk 492 #define BLE_PHY_AGC_CFG12_ADC_POWER_URUN_THD_Pos (14U) 493 #define BLE_PHY_AGC_CFG12_ADC_POWER_URUN_THD_Msk (0x7FUL << BLE_PHY_AGC_CFG12_ADC_POWER_URUN_THD_Pos) 494 #define BLE_PHY_AGC_CFG12_ADC_POWER_URUN_THD BLE_PHY_AGC_CFG12_ADC_POWER_URUN_THD_Msk 495 496 /*************** Bit definition for BLE_PHY_RSSI_CFG1 register ****************/ 497 #define BLE_PHY_RSSI_CFG1_DIG_GAIN_LOW_DB_Pos (0U) 498 #define BLE_PHY_RSSI_CFG1_DIG_GAIN_LOW_DB_Msk (0x7FUL << BLE_PHY_RSSI_CFG1_DIG_GAIN_LOW_DB_Pos) 499 #define BLE_PHY_RSSI_CFG1_DIG_GAIN_LOW_DB BLE_PHY_RSSI_CFG1_DIG_GAIN_LOW_DB_Msk 500 #define BLE_PHY_RSSI_CFG1_DIG_GAIN_HIGH_DB_Pos (7U) 501 #define BLE_PHY_RSSI_CFG1_DIG_GAIN_HIGH_DB_Msk (0x7FUL << BLE_PHY_RSSI_CFG1_DIG_GAIN_HIGH_DB_Pos) 502 #define BLE_PHY_RSSI_CFG1_DIG_GAIN_HIGH_DB BLE_PHY_RSSI_CFG1_DIG_GAIN_HIGH_DB_Msk 503 #define BLE_PHY_RSSI_CFG1_RSSI_MU_Pos (14U) 504 #define BLE_PHY_RSSI_CFG1_RSSI_MU_Msk (0x7UL << BLE_PHY_RSSI_CFG1_RSSI_MU_Pos) 505 #define BLE_PHY_RSSI_CFG1_RSSI_MU BLE_PHY_RSSI_CFG1_RSSI_MU_Msk 506 #define BLE_PHY_RSSI_CFG1_RSSI_OFFSET_Pos (17U) 507 #define BLE_PHY_RSSI_CFG1_RSSI_OFFSET_Msk (0x3FUL << BLE_PHY_RSSI_CFG1_RSSI_OFFSET_Pos) 508 #define BLE_PHY_RSSI_CFG1_RSSI_OFFSET BLE_PHY_RSSI_CFG1_RSSI_OFFSET_Msk 509 510 /*************** Bit definition for BLE_PHY_AGC_STATUS register ***************/ 511 #define BLE_PHY_AGC_STATUS_LNA_MIXER_GAIN_INDEX_Pos (0U) 512 #define BLE_PHY_AGC_STATUS_LNA_MIXER_GAIN_INDEX_Msk (0xFUL << BLE_PHY_AGC_STATUS_LNA_MIXER_GAIN_INDEX_Pos) 513 #define BLE_PHY_AGC_STATUS_LNA_MIXER_GAIN_INDEX BLE_PHY_AGC_STATUS_LNA_MIXER_GAIN_INDEX_Msk 514 #define BLE_PHY_AGC_STATUS_CBPF_GAIN_INDEX_Pos (4U) 515 #define BLE_PHY_AGC_STATUS_CBPF_GAIN_INDEX_Msk (0x3UL << BLE_PHY_AGC_STATUS_CBPF_GAIN_INDEX_Pos) 516 #define BLE_PHY_AGC_STATUS_CBPF_GAIN_INDEX BLE_PHY_AGC_STATUS_CBPF_GAIN_INDEX_Msk 517 #define BLE_PHY_AGC_STATUS_VGA_GAIN_INDEX_Pos (6U) 518 #define BLE_PHY_AGC_STATUS_VGA_GAIN_INDEX_Msk (0xFUL << BLE_PHY_AGC_STATUS_VGA_GAIN_INDEX_Pos) 519 #define BLE_PHY_AGC_STATUS_VGA_GAIN_INDEX BLE_PHY_AGC_STATUS_VGA_GAIN_INDEX_Msk 520 #define BLE_PHY_AGC_STATUS_ADC_DIG_GAIN_Pos (10U) 521 #define BLE_PHY_AGC_STATUS_ADC_DIG_GAIN_Msk (0x3FUL << BLE_PHY_AGC_STATUS_ADC_DIG_GAIN_Pos) 522 #define BLE_PHY_AGC_STATUS_ADC_DIG_GAIN BLE_PHY_AGC_STATUS_ADC_DIG_GAIN_Msk 523 #define BLE_PHY_AGC_STATUS_RSSI_Pos (16U) 524 #define BLE_PHY_AGC_STATUS_RSSI_Msk (0xFFUL << BLE_PHY_AGC_STATUS_RSSI_Pos) 525 #define BLE_PHY_AGC_STATUS_RSSI BLE_PHY_AGC_STATUS_RSSI_Msk 526 527 /**************** Bit definition for BLE_PHY_TX_CTRL register *****************/ 528 #define BLE_PHY_TX_CTRL_FORCE_TX_ON_Pos (0U) 529 #define BLE_PHY_TX_CTRL_FORCE_TX_ON_Msk (0x1UL << BLE_PHY_TX_CTRL_FORCE_TX_ON_Pos) 530 #define BLE_PHY_TX_CTRL_FORCE_TX_ON BLE_PHY_TX_CTRL_FORCE_TX_ON_Msk 531 #define BLE_PHY_TX_CTRL_TX_LOOPBACK_MODE_Pos (1U) 532 #define BLE_PHY_TX_CTRL_TX_LOOPBACK_MODE_Msk (0x1UL << BLE_PHY_TX_CTRL_TX_LOOPBACK_MODE_Pos) 533 #define BLE_PHY_TX_CTRL_TX_LOOPBACK_MODE BLE_PHY_TX_CTRL_TX_LOOPBACK_MODE_Msk 534 #define BLE_PHY_TX_CTRL_MAC_PWR_CTRL_EN_Pos (2U) 535 #define BLE_PHY_TX_CTRL_MAC_PWR_CTRL_EN_Msk (0x1UL << BLE_PHY_TX_CTRL_MAC_PWR_CTRL_EN_Pos) 536 #define BLE_PHY_TX_CTRL_MAC_PWR_CTRL_EN BLE_PHY_TX_CTRL_MAC_PWR_CTRL_EN_Msk 537 538 /************** Bit definition for BLE_PHY_TX_RCC_CTRL register ***************/ 539 #define BLE_PHY_TX_RCC_CTRL_FORCE_PA_CTRL_ON_Pos (0U) 540 #define BLE_PHY_TX_RCC_CTRL_FORCE_PA_CTRL_ON_Msk (0x1UL << BLE_PHY_TX_RCC_CTRL_FORCE_PA_CTRL_ON_Pos) 541 #define BLE_PHY_TX_RCC_CTRL_FORCE_PA_CTRL_ON BLE_PHY_TX_RCC_CTRL_FORCE_PA_CTRL_ON_Msk 542 #define BLE_PHY_TX_RCC_CTRL_FORCE_LFP_ON_Pos (1U) 543 #define BLE_PHY_TX_RCC_CTRL_FORCE_LFP_ON_Msk (0x1UL << BLE_PHY_TX_RCC_CTRL_FORCE_LFP_ON_Pos) 544 #define BLE_PHY_TX_RCC_CTRL_FORCE_LFP_ON BLE_PHY_TX_RCC_CTRL_FORCE_LFP_ON_Msk 545 #define BLE_PHY_TX_RCC_CTRL_FORCE_HFP_ON_Pos (2U) 546 #define BLE_PHY_TX_RCC_CTRL_FORCE_HFP_ON_Msk (0x1UL << BLE_PHY_TX_RCC_CTRL_FORCE_HFP_ON_Pos) 547 #define BLE_PHY_TX_RCC_CTRL_FORCE_HFP_ON BLE_PHY_TX_RCC_CTRL_FORCE_HFP_ON_Msk 548 #define BLE_PHY_TX_RCC_CTRL_FORCE_IF_MOD_ON_Pos (3U) 549 #define BLE_PHY_TX_RCC_CTRL_FORCE_IF_MOD_ON_Msk (0x1UL << BLE_PHY_TX_RCC_CTRL_FORCE_IF_MOD_ON_Pos) 550 #define BLE_PHY_TX_RCC_CTRL_FORCE_IF_MOD_ON BLE_PHY_TX_RCC_CTRL_FORCE_IF_MOD_ON_Msk 551 #define BLE_PHY_TX_RCC_CTRL_FORCE_RC_ON_Pos (4U) 552 #define BLE_PHY_TX_RCC_CTRL_FORCE_RC_ON_Msk (0x1UL << BLE_PHY_TX_RCC_CTRL_FORCE_RC_ON_Pos) 553 #define BLE_PHY_TX_RCC_CTRL_FORCE_RC_ON BLE_PHY_TX_RCC_CTRL_FORCE_RC_ON_Msk 554 #define BLE_PHY_TX_RCC_CTRL_FORCE_GAUSSFLT_ON_Pos (5U) 555 #define BLE_PHY_TX_RCC_CTRL_FORCE_GAUSSFLT_ON_Msk (0x1UL << BLE_PHY_TX_RCC_CTRL_FORCE_GAUSSFLT_ON_Pos) 556 #define BLE_PHY_TX_RCC_CTRL_FORCE_GAUSSFLT_ON BLE_PHY_TX_RCC_CTRL_FORCE_GAUSSFLT_ON_Msk 557 #define BLE_PHY_TX_RCC_CTRL_FORCE_TX_RESET_Pos (6U) 558 #define BLE_PHY_TX_RCC_CTRL_FORCE_TX_RESET_Msk (0x1UL << BLE_PHY_TX_RCC_CTRL_FORCE_TX_RESET_Pos) 559 #define BLE_PHY_TX_RCC_CTRL_FORCE_TX_RESET BLE_PHY_TX_RCC_CTRL_FORCE_TX_RESET_Msk 560 561 /************ Bit definition for BLE_PHY_TX_GAUSSFLT_CFG register *************/ 562 #define BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_1_Pos (0U) 563 #define BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_1_Msk (0x1FFUL << BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_1_Pos) 564 #define BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_1 BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_1_Msk 565 #define BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_2_Pos (9U) 566 #define BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_2_Msk (0x1FFUL << BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_2_Pos) 567 #define BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_2 BLE_PHY_TX_GAUSSFLT_CFG_GAUSS_GAIN_2_Msk 568 569 /************* Bit definition for BLE_PHY_TX_IF_MOD_CFG register **************/ 570 #define BLE_PHY_TX_IF_MOD_CFG_TX_MOD_GAIN_Pos (0U) 571 #define BLE_PHY_TX_IF_MOD_CFG_TX_MOD_GAIN_Msk (0xFFUL << BLE_PHY_TX_IF_MOD_CFG_TX_MOD_GAIN_Pos) 572 #define BLE_PHY_TX_IF_MOD_CFG_TX_MOD_GAIN BLE_PHY_TX_IF_MOD_CFG_TX_MOD_GAIN_Msk 573 #define BLE_PHY_TX_IF_MOD_CFG_TX_IF_PHASE_Pos (8U) 574 #define BLE_PHY_TX_IF_MOD_CFG_TX_IF_PHASE_Msk (0x3FFUL << BLE_PHY_TX_IF_MOD_CFG_TX_IF_PHASE_Pos) 575 #define BLE_PHY_TX_IF_MOD_CFG_TX_IF_PHASE BLE_PHY_TX_IF_MOD_CFG_TX_IF_PHASE_Msk 576 577 /*************** Bit definition for BLE_PHY_TX_HFP_CFG register ***************/ 578 #define BLE_PHY_TX_HFP_CFG_TX_KCAL_COEF_Pos (0U) 579 #define BLE_PHY_TX_HFP_CFG_TX_KCAL_COEF_Msk (0x1FFUL << BLE_PHY_TX_HFP_CFG_TX_KCAL_COEF_Pos) 580 #define BLE_PHY_TX_HFP_CFG_TX_KCAL_COEF BLE_PHY_TX_HFP_CFG_TX_KCAL_COEF_Msk 581 #define BLE_PHY_TX_HFP_CFG_TX_KCAL_Pos (9U) 582 #define BLE_PHY_TX_HFP_CFG_TX_KCAL_Msk (0xFFFUL << BLE_PHY_TX_HFP_CFG_TX_KCAL_Pos) 583 #define BLE_PHY_TX_HFP_CFG_TX_KCAL BLE_PHY_TX_HFP_CFG_TX_KCAL_Msk 584 #define BLE_PHY_TX_HFP_CFG_HFP_FCW_SEL_Pos (21U) 585 #define BLE_PHY_TX_HFP_CFG_HFP_FCW_SEL_Msk (0x1UL << BLE_PHY_TX_HFP_CFG_HFP_FCW_SEL_Pos) 586 #define BLE_PHY_TX_HFP_CFG_HFP_FCW_SEL BLE_PHY_TX_HFP_CFG_HFP_FCW_SEL_Msk 587 #define BLE_PHY_TX_HFP_CFG_HFP_FCW_Pos (22U) 588 #define BLE_PHY_TX_HFP_CFG_HFP_FCW_Msk (0x3FUL << BLE_PHY_TX_HFP_CFG_HFP_FCW_Pos) 589 #define BLE_PHY_TX_HFP_CFG_HFP_FCW BLE_PHY_TX_HFP_CFG_HFP_FCW_Msk 590 #define BLE_PHY_TX_HFP_CFG_HFP_DELAY_SEL_Pos (28U) 591 #define BLE_PHY_TX_HFP_CFG_HFP_DELAY_SEL_Msk (0x7UL << BLE_PHY_TX_HFP_CFG_HFP_DELAY_SEL_Pos) 592 #define BLE_PHY_TX_HFP_CFG_HFP_DELAY_SEL BLE_PHY_TX_HFP_CFG_HFP_DELAY_SEL_Msk 593 594 /*************** Bit definition for BLE_PHY_TX_LFP_CFG register ***************/ 595 #define BLE_PHY_TX_LFP_CFG_LFP_FCW_SEL_Pos (0U) 596 #define BLE_PHY_TX_LFP_CFG_LFP_FCW_SEL_Msk (0x1UL << BLE_PHY_TX_LFP_CFG_LFP_FCW_SEL_Pos) 597 #define BLE_PHY_TX_LFP_CFG_LFP_FCW_SEL BLE_PHY_TX_LFP_CFG_LFP_FCW_SEL_Msk 598 #define BLE_PHY_TX_LFP_CFG_LFP_FCW_Pos (1U) 599 #define BLE_PHY_TX_LFP_CFG_LFP_FCW_Msk (0x3FFUL << BLE_PHY_TX_LFP_CFG_LFP_FCW_Pos) 600 #define BLE_PHY_TX_LFP_CFG_LFP_FCW BLE_PHY_TX_LFP_CFG_LFP_FCW_Msk 601 #define BLE_PHY_TX_LFP_CFG_TX_SDM_DITHER_EN_Pos (11U) 602 #define BLE_PHY_TX_LFP_CFG_TX_SDM_DITHER_EN_Msk (0x1UL << BLE_PHY_TX_LFP_CFG_TX_SDM_DITHER_EN_Pos) 603 #define BLE_PHY_TX_LFP_CFG_TX_SDM_DITHER_EN BLE_PHY_TX_LFP_CFG_TX_SDM_DITHER_EN_Msk 604 #define BLE_PHY_TX_LFP_CFG_TX_SDM_SEL_Pos (12U) 605 #define BLE_PHY_TX_LFP_CFG_TX_SDM_SEL_Msk (0x1UL << BLE_PHY_TX_LFP_CFG_TX_SDM_SEL_Pos) 606 #define BLE_PHY_TX_LFP_CFG_TX_SDM_SEL BLE_PHY_TX_LFP_CFG_TX_SDM_SEL_Msk 607 608 /*************** Bit definition for BLE_PHY_TX_PA_CFG register ****************/ 609 #define BLE_PHY_TX_PA_CFG_PA_RAMP_FORCE_Pos (0U) 610 #define BLE_PHY_TX_PA_CFG_PA_RAMP_FORCE_Msk (0x3UL << BLE_PHY_TX_PA_CFG_PA_RAMP_FORCE_Pos) 611 #define BLE_PHY_TX_PA_CFG_PA_RAMP_FORCE BLE_PHY_TX_PA_CFG_PA_RAMP_FORCE_Msk 612 #define BLE_PHY_TX_PA_CFG_PA_CTRL_TARGET_Pos (2U) 613 #define BLE_PHY_TX_PA_CFG_PA_CTRL_TARGET_Msk (0x3FUL << BLE_PHY_TX_PA_CFG_PA_CTRL_TARGET_Pos) 614 #define BLE_PHY_TX_PA_CFG_PA_CTRL_TARGET BLE_PHY_TX_PA_CFG_PA_CTRL_TARGET_Msk 615 #define BLE_PHY_TX_PA_CFG_PA_RAMP_FACTOR_IDX_Pos (8U) 616 #define BLE_PHY_TX_PA_CFG_PA_RAMP_FACTOR_IDX_Msk (0x7UL << BLE_PHY_TX_PA_CFG_PA_RAMP_FACTOR_IDX_Pos) 617 #define BLE_PHY_TX_PA_CFG_PA_RAMP_FACTOR_IDX BLE_PHY_TX_PA_CFG_PA_RAMP_FACTOR_IDX_Msk 618 619 /************* Bit definition for BLE_PHY_LFP_MMDIV_CFG0 register *************/ 620 #define BLE_PHY_LFP_MMDIV_CFG0_RX_MMDIV_OFFSET_1M_Pos (0U) 621 #define BLE_PHY_LFP_MMDIV_CFG0_RX_MMDIV_OFFSET_1M_Msk (0x1FFFFUL << BLE_PHY_LFP_MMDIV_CFG0_RX_MMDIV_OFFSET_1M_Pos) 622 #define BLE_PHY_LFP_MMDIV_CFG0_RX_MMDIV_OFFSET_1M BLE_PHY_LFP_MMDIV_CFG0_RX_MMDIV_OFFSET_1M_Msk 623 624 /************* Bit definition for BLE_PHY_LFP_MMDIV_CFG1 register *************/ 625 #define BLE_PHY_LFP_MMDIV_CFG1_RX_MMDIV_OFFSET_2M_Pos (0U) 626 #define BLE_PHY_LFP_MMDIV_CFG1_RX_MMDIV_OFFSET_2M_Msk (0x1FFFFUL << BLE_PHY_LFP_MMDIV_CFG1_RX_MMDIV_OFFSET_2M_Pos) 627 #define BLE_PHY_LFP_MMDIV_CFG1_RX_MMDIV_OFFSET_2M BLE_PHY_LFP_MMDIV_CFG1_RX_MMDIV_OFFSET_2M_Msk 628 629 /************* Bit definition for BLE_PHY_LFP_MMDIV_CFG2 register *************/ 630 #define BLE_PHY_LFP_MMDIV_CFG2_TX_MMDIV_OFFSET_Pos (0U) 631 #define BLE_PHY_LFP_MMDIV_CFG2_TX_MMDIV_OFFSET_Msk (0x1FFFFUL << BLE_PHY_LFP_MMDIV_CFG2_TX_MMDIV_OFFSET_Pos) 632 #define BLE_PHY_LFP_MMDIV_CFG2_TX_MMDIV_OFFSET BLE_PHY_LFP_MMDIV_CFG2_TX_MMDIV_OFFSET_Msk 633 634 /************* Bit definition for BLE_PHY_LFP_MMDIV_CFG3 register *************/ 635 #define BLE_PHY_LFP_MMDIV_CFG3_RF_MMDIV_TEST_Pos (0U) 636 #define BLE_PHY_LFP_MMDIV_CFG3_RF_MMDIV_TEST_Msk (0x1FFFFFFUL << BLE_PHY_LFP_MMDIV_CFG3_RF_MMDIV_TEST_Pos) 637 #define BLE_PHY_LFP_MMDIV_CFG3_RF_MMDIV_TEST BLE_PHY_LFP_MMDIV_CFG3_RF_MMDIV_TEST_Msk 638 #define BLE_PHY_LFP_MMDIV_CFG3_RF_TEST_MODE_Pos (25U) 639 #define BLE_PHY_LFP_MMDIV_CFG3_RF_TEST_MODE_Msk (0x1UL << BLE_PHY_LFP_MMDIV_CFG3_RF_TEST_MODE_Pos) 640 #define BLE_PHY_LFP_MMDIV_CFG3_RF_TEST_MODE BLE_PHY_LFP_MMDIV_CFG3_RF_TEST_MODE_Msk 641 642 /*************** Bit definition for BLE_PHY_RX_HFP_CFG register ***************/ 643 #define BLE_PHY_RX_HFP_CFG_RX_HFP_FCW_Pos (0U) 644 #define BLE_PHY_RX_HFP_CFG_RX_HFP_FCW_Msk (0x3FUL << BLE_PHY_RX_HFP_CFG_RX_HFP_FCW_Pos) 645 #define BLE_PHY_RX_HFP_CFG_RX_HFP_FCW BLE_PHY_RX_HFP_CFG_RX_HFP_FCW_Msk 646 647 /************* Bit definition for BLE_PHY_LNA_GAIN_TBL0 register **************/ 648 #define BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_0_Pos (0U) 649 #define BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_0_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_0_Pos) 650 #define BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_0 BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_0_Msk 651 #define BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_1_Pos (11U) 652 #define BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_1_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_1_Pos) 653 #define BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_1 BLE_PHY_LNA_GAIN_TBL0_LNA_GAIN_1_Msk 654 655 /************* Bit definition for BLE_PHY_LNA_GAIN_TBL1 register **************/ 656 #define BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_2_Pos (0U) 657 #define BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_2_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_2_Pos) 658 #define BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_2 BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_2_Msk 659 #define BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_3_Pos (11U) 660 #define BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_3_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_3_Pos) 661 #define BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_3 BLE_PHY_LNA_GAIN_TBL1_LNA_GAIN_3_Msk 662 663 /************* Bit definition for BLE_PHY_LNA_GAIN_TBL2 register **************/ 664 #define BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_4_Pos (0U) 665 #define BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_4_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_4_Pos) 666 #define BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_4 BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_4_Msk 667 #define BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_5_Pos (11U) 668 #define BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_5_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_5_Pos) 669 #define BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_5 BLE_PHY_LNA_GAIN_TBL2_LNA_GAIN_5_Msk 670 671 /************* Bit definition for BLE_PHY_LNA_GAIN_TBL3 register **************/ 672 #define BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_6_Pos (0U) 673 #define BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_6_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_6_Pos) 674 #define BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_6 BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_6_Msk 675 #define BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_7_Pos (11U) 676 #define BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_7_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_7_Pos) 677 #define BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_7 BLE_PHY_LNA_GAIN_TBL3_LNA_GAIN_7_Msk 678 679 /************* Bit definition for BLE_PHY_LNA_GAIN_TBL4 register **************/ 680 #define BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_8_Pos (0U) 681 #define BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_8_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_8_Pos) 682 #define BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_8 BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_8_Msk 683 #define BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_9_Pos (11U) 684 #define BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_9_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_9_Pos) 685 #define BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_9 BLE_PHY_LNA_GAIN_TBL4_LNA_GAIN_9_Msk 686 687 /************* Bit definition for BLE_PHY_LNA_GAIN_TBL5 register **************/ 688 #define BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_10_Pos (0U) 689 #define BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_10_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_10_Pos) 690 #define BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_10 BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_10_Msk 691 #define BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_11_Pos (11U) 692 #define BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_11_Msk (0x7FFUL << BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_11_Pos) 693 #define BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_11 BLE_PHY_LNA_GAIN_TBL5_LNA_GAIN_11_Msk 694 695 /************** Bit definition for BLE_PHY_MP_TEST_CFG register ***************/ 696 #define BLE_PHY_MP_TEST_CFG_DC_EST_EN_Pos (0U) 697 #define BLE_PHY_MP_TEST_CFG_DC_EST_EN_Msk (0x1UL << BLE_PHY_MP_TEST_CFG_DC_EST_EN_Pos) 698 #define BLE_PHY_MP_TEST_CFG_DC_EST_EN BLE_PHY_MP_TEST_CFG_DC_EST_EN_Msk 699 #define BLE_PHY_MP_TEST_CFG_DC_EST_MU_Pos (1U) 700 #define BLE_PHY_MP_TEST_CFG_DC_EST_MU_Msk (0x7UL << BLE_PHY_MP_TEST_CFG_DC_EST_MU_Pos) 701 #define BLE_PHY_MP_TEST_CFG_DC_EST_MU BLE_PHY_MP_TEST_CFG_DC_EST_MU_Msk 702 #define BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_LOW_Pos (4U) 703 #define BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_LOW_Msk (0xFUL << BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_LOW_Pos) 704 #define BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_LOW BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_LOW_Msk 705 #define BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_HIGH_Pos (8U) 706 #define BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_HIGH_Msk (0xFUL << BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_HIGH_Pos) 707 #define BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_HIGH BLE_PHY_MP_TEST_CFG_MP_LNA_GAIN_INDEX_HIGH_Msk 708 #define BLE_PHY_MP_TEST_CFG_DC_EST_BYPASS_Pos (12U) 709 #define BLE_PHY_MP_TEST_CFG_DC_EST_BYPASS_Msk (0x1UL << BLE_PHY_MP_TEST_CFG_DC_EST_BYPASS_Pos) 710 #define BLE_PHY_MP_TEST_CFG_DC_EST_BYPASS BLE_PHY_MP_TEST_CFG_DC_EST_BYPASS_Msk 711 #endif
