1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : XOSC
10 // Version        : 1
11 // Bus type       : apb
12 // Description    : Controls the crystal oscillator
13 // =============================================================================
14 #ifndef _HARDWARE_REGS_XOSC_H
15 #define _HARDWARE_REGS_XOSC_H
16 // =============================================================================
17 // Register    : XOSC_CTRL
18 // Description : Crystal Oscillator Control
19 #define XOSC_CTRL_OFFSET _u(0x00000000)
20 #define XOSC_CTRL_BITS   _u(0x00ffffff)
21 #define XOSC_CTRL_RESET  _u(0x00000000)
22 // -----------------------------------------------------------------------------
23 // Field       : XOSC_CTRL_ENABLE
24 // Description : On power-up this field is initialised to DISABLE and the chip
25 //               runs from the ROSC.
26 //               If the chip has subsequently been programmed to run from the
27 //               XOSC then setting this field to DISABLE may lock-up the chip.
28 //               If  this is a concern then run the clk_ref from the ROSC and
29 //               enable the clk_sys RESUS feature.
30 //               The 12-bit code is intended to give some protection against
31 //               accidental writes. An invalid setting will retain the previous
32 //               value. The actual value being used can be read from
33 //               STATUS_ENABLED
34 //               0xd1e -> DISABLE
35 //               0xfab -> ENABLE
36 #define XOSC_CTRL_ENABLE_RESET  "-"
37 #define XOSC_CTRL_ENABLE_BITS   _u(0x00fff000)
38 #define XOSC_CTRL_ENABLE_MSB    _u(23)
39 #define XOSC_CTRL_ENABLE_LSB    _u(12)
40 #define XOSC_CTRL_ENABLE_ACCESS "RW"
41 #define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
42 #define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
43 // -----------------------------------------------------------------------------
44 // Field       : XOSC_CTRL_FREQ_RANGE
45 // Description : The 12-bit code is intended to give some protection against
46 //               accidental writes. An invalid setting will retain the previous
47 //               value. The actual value being used can be read from
48 //               STATUS_FREQ_RANGE
49 //               0xaa0 -> 1_15MHZ
50 //               0xaa1 -> 10_30MHZ
51 //               0xaa2 -> 25_60MHZ
52 //               0xaa3 -> 40_100MHZ
53 #define XOSC_CTRL_FREQ_RANGE_RESET  "-"
54 #define XOSC_CTRL_FREQ_RANGE_BITS   _u(0x00000fff)
55 #define XOSC_CTRL_FREQ_RANGE_MSB    _u(11)
56 #define XOSC_CTRL_FREQ_RANGE_LSB    _u(0)
57 #define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
58 #define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
59 #define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ _u(0xaa1)
60 #define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ _u(0xaa2)
61 #define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ _u(0xaa3)
62 // =============================================================================
63 // Register    : XOSC_STATUS
64 // Description : Crystal Oscillator Status
65 #define XOSC_STATUS_OFFSET _u(0x00000004)
66 #define XOSC_STATUS_BITS   _u(0x81001003)
67 #define XOSC_STATUS_RESET  _u(0x00000000)
68 // -----------------------------------------------------------------------------
69 // Field       : XOSC_STATUS_STABLE
70 // Description : Oscillator is running and stable
71 #define XOSC_STATUS_STABLE_RESET  _u(0x0)
72 #define XOSC_STATUS_STABLE_BITS   _u(0x80000000)
73 #define XOSC_STATUS_STABLE_MSB    _u(31)
74 #define XOSC_STATUS_STABLE_LSB    _u(31)
75 #define XOSC_STATUS_STABLE_ACCESS "RO"
76 // -----------------------------------------------------------------------------
77 // Field       : XOSC_STATUS_BADWRITE
78 // Description : An invalid value has been written to CTRL_ENABLE or
79 //               CTRL_FREQ_RANGE or DORMANT
80 #define XOSC_STATUS_BADWRITE_RESET  _u(0x0)
81 #define XOSC_STATUS_BADWRITE_BITS   _u(0x01000000)
82 #define XOSC_STATUS_BADWRITE_MSB    _u(24)
83 #define XOSC_STATUS_BADWRITE_LSB    _u(24)
84 #define XOSC_STATUS_BADWRITE_ACCESS "WC"
85 // -----------------------------------------------------------------------------
86 // Field       : XOSC_STATUS_ENABLED
87 // Description : Oscillator is enabled but not necessarily running and stable,
88 //               resets to 0
89 #define XOSC_STATUS_ENABLED_RESET  "-"
90 #define XOSC_STATUS_ENABLED_BITS   _u(0x00001000)
91 #define XOSC_STATUS_ENABLED_MSB    _u(12)
92 #define XOSC_STATUS_ENABLED_LSB    _u(12)
93 #define XOSC_STATUS_ENABLED_ACCESS "RO"
94 // -----------------------------------------------------------------------------
95 // Field       : XOSC_STATUS_FREQ_RANGE
96 // Description : The current frequency range setting
97 //               0x0 -> 1_15MHZ
98 //               0x1 -> 10_30MHZ
99 //               0x2 -> 25_60MHZ
100 //               0x3 -> 40_100MHZ
101 #define XOSC_STATUS_FREQ_RANGE_RESET  "-"
102 #define XOSC_STATUS_FREQ_RANGE_BITS   _u(0x00000003)
103 #define XOSC_STATUS_FREQ_RANGE_MSB    _u(1)
104 #define XOSC_STATUS_FREQ_RANGE_LSB    _u(0)
105 #define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
106 #define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
107 #define XOSC_STATUS_FREQ_RANGE_VALUE_10_30MHZ _u(0x1)
108 #define XOSC_STATUS_FREQ_RANGE_VALUE_25_60MHZ _u(0x2)
109 #define XOSC_STATUS_FREQ_RANGE_VALUE_40_100MHZ _u(0x3)
110 // =============================================================================
111 // Register    : XOSC_DORMANT
112 // Description : Crystal Oscillator pause control
113 //               This is used to save power by pausing the XOSC
114 //               On power-up this field is initialised to WAKE
115 //               An invalid write will also select WAKE
116 //               Warning: stop the PLLs before selecting dormant mode
117 //               Warning: setup the irq before selecting dormant mode
118 //               0x636f6d61 -> dormant
119 //               0x77616b65 -> WAKE
120 #define XOSC_DORMANT_OFFSET _u(0x00000008)
121 #define XOSC_DORMANT_BITS   _u(0xffffffff)
122 #define XOSC_DORMANT_RESET  "-"
123 #define XOSC_DORMANT_MSB    _u(31)
124 #define XOSC_DORMANT_LSB    _u(0)
125 #define XOSC_DORMANT_ACCESS "RW"
126 #define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
127 #define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
128 // =============================================================================
129 // Register    : XOSC_STARTUP
130 // Description : Controls the startup delay
131 #define XOSC_STARTUP_OFFSET _u(0x0000000c)
132 #define XOSC_STARTUP_BITS   _u(0x00103fff)
133 #define XOSC_STARTUP_RESET  _u(0x00000000)
134 // -----------------------------------------------------------------------------
135 // Field       : XOSC_STARTUP_X4
136 // Description : Multiplies the startup_delay by 4, just in case. The reset
137 //               value is controlled by a mask-programmable tiecell and is
138 //               provided in case we are booting from XOSC and the default
139 //               startup delay is insufficient. The reset value is 0x0.
140 #define XOSC_STARTUP_X4_RESET  "-"
141 #define XOSC_STARTUP_X4_BITS   _u(0x00100000)
142 #define XOSC_STARTUP_X4_MSB    _u(20)
143 #define XOSC_STARTUP_X4_LSB    _u(20)
144 #define XOSC_STARTUP_X4_ACCESS "RW"
145 // -----------------------------------------------------------------------------
146 // Field       : XOSC_STARTUP_DELAY
147 // Description : in multiples of 256*xtal_period. The reset value of 0xc4
148 //               corresponds to approx 50 000 cycles.
149 #define XOSC_STARTUP_DELAY_RESET  "-"
150 #define XOSC_STARTUP_DELAY_BITS   _u(0x00003fff)
151 #define XOSC_STARTUP_DELAY_MSB    _u(13)
152 #define XOSC_STARTUP_DELAY_LSB    _u(0)
153 #define XOSC_STARTUP_DELAY_ACCESS "RW"
154 // =============================================================================
155 // Register    : XOSC_COUNT
156 // Description : A down counter running at the xosc frequency which counts to
157 //               zero and stops.
158 //               Can be used for short software pauses when setting up time
159 //               sensitive hardware.
160 //               To start the counter, write a non-zero value. Reads will return
161 //               1 while the count is running and 0 when it has finished.
162 //               Minimum count value is 4. Count values <4 will be treated as
163 //               count value =4.
164 //               Note that synchronisation to the register clock domain costs 2
165 //               register clock cycles and the counter cannot compensate for
166 //               that.
167 #define XOSC_COUNT_OFFSET _u(0x00000010)
168 #define XOSC_COUNT_BITS   _u(0x0000ffff)
169 #define XOSC_COUNT_RESET  _u(0x00000000)
170 #define XOSC_COUNT_MSB    _u(15)
171 #define XOSC_COUNT_LSB    _u(0)
172 #define XOSC_COUNT_ACCESS "RW"
173 // =============================================================================
174 #endif // _HARDWARE_REGS_XOSC_H
175 
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