1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : WATCHDOG
10 // Version        : 1
11 // Bus type       : apb
12 // =============================================================================
13 #ifndef _HARDWARE_REGS_WATCHDOG_H
14 #define _HARDWARE_REGS_WATCHDOG_H
15 // =============================================================================
16 // Register    : WATCHDOG_CTRL
17 // Description : Watchdog control
18 //               The rst_wdsel register determines which subsystems are reset
19 //               when the watchdog is triggered.
20 //               The watchdog can be triggered in software.
21 #define WATCHDOG_CTRL_OFFSET _u(0x00000000)
22 #define WATCHDOG_CTRL_BITS   _u(0xc7ffffff)
23 #define WATCHDOG_CTRL_RESET  _u(0x07000000)
24 // -----------------------------------------------------------------------------
25 // Field       : WATCHDOG_CTRL_TRIGGER
26 // Description : Trigger a watchdog reset
27 #define WATCHDOG_CTRL_TRIGGER_RESET  _u(0x0)
28 #define WATCHDOG_CTRL_TRIGGER_BITS   _u(0x80000000)
29 #define WATCHDOG_CTRL_TRIGGER_MSB    _u(31)
30 #define WATCHDOG_CTRL_TRIGGER_LSB    _u(31)
31 #define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
32 // -----------------------------------------------------------------------------
33 // Field       : WATCHDOG_CTRL_ENABLE
34 // Description : When not enabled the watchdog timer is paused
35 #define WATCHDOG_CTRL_ENABLE_RESET  _u(0x0)
36 #define WATCHDOG_CTRL_ENABLE_BITS   _u(0x40000000)
37 #define WATCHDOG_CTRL_ENABLE_MSB    _u(30)
38 #define WATCHDOG_CTRL_ENABLE_LSB    _u(30)
39 #define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
40 // -----------------------------------------------------------------------------
41 // Field       : WATCHDOG_CTRL_PAUSE_DBG1
42 // Description : Pause the watchdog timer when processor 1 is in debug mode
43 #define WATCHDOG_CTRL_PAUSE_DBG1_RESET  _u(0x1)
44 #define WATCHDOG_CTRL_PAUSE_DBG1_BITS   _u(0x04000000)
45 #define WATCHDOG_CTRL_PAUSE_DBG1_MSB    _u(26)
46 #define WATCHDOG_CTRL_PAUSE_DBG1_LSB    _u(26)
47 #define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
48 // -----------------------------------------------------------------------------
49 // Field       : WATCHDOG_CTRL_PAUSE_DBG0
50 // Description : Pause the watchdog timer when processor 0 is in debug mode
51 #define WATCHDOG_CTRL_PAUSE_DBG0_RESET  _u(0x1)
52 #define WATCHDOG_CTRL_PAUSE_DBG0_BITS   _u(0x02000000)
53 #define WATCHDOG_CTRL_PAUSE_DBG0_MSB    _u(25)
54 #define WATCHDOG_CTRL_PAUSE_DBG0_LSB    _u(25)
55 #define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
56 // -----------------------------------------------------------------------------
57 // Field       : WATCHDOG_CTRL_PAUSE_JTAG
58 // Description : Pause the watchdog timer when JTAG is accessing the bus fabric
59 #define WATCHDOG_CTRL_PAUSE_JTAG_RESET  _u(0x1)
60 #define WATCHDOG_CTRL_PAUSE_JTAG_BITS   _u(0x01000000)
61 #define WATCHDOG_CTRL_PAUSE_JTAG_MSB    _u(24)
62 #define WATCHDOG_CTRL_PAUSE_JTAG_LSB    _u(24)
63 #define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
64 // -----------------------------------------------------------------------------
65 // Field       : WATCHDOG_CTRL_TIME
66 // Description : Indicates the time in usec before a watchdog reset will be
67 //               triggered
68 #define WATCHDOG_CTRL_TIME_RESET  _u(0x000000)
69 #define WATCHDOG_CTRL_TIME_BITS   _u(0x00ffffff)
70 #define WATCHDOG_CTRL_TIME_MSB    _u(23)
71 #define WATCHDOG_CTRL_TIME_LSB    _u(0)
72 #define WATCHDOG_CTRL_TIME_ACCESS "RO"
73 // =============================================================================
74 // Register    : WATCHDOG_LOAD
75 // Description : Load the watchdog timer. The maximum setting is 0xffffff which
76 //               corresponds to approximately 16 seconds.
77 #define WATCHDOG_LOAD_OFFSET _u(0x00000004)
78 #define WATCHDOG_LOAD_BITS   _u(0x00ffffff)
79 #define WATCHDOG_LOAD_RESET  _u(0x00000000)
80 #define WATCHDOG_LOAD_MSB    _u(23)
81 #define WATCHDOG_LOAD_LSB    _u(0)
82 #define WATCHDOG_LOAD_ACCESS "WF"
83 // =============================================================================
84 // Register    : WATCHDOG_REASON
85 // Description : Logs the reason for the last reset. Both bits are zero for the
86 //               case of a hardware reset.
87 //
88 //               Additionally, as of RP2350, a debugger warm reset of either
89 //               core (SYSRESETREQ or hartreset) will also clear the watchdog
90 //               reason register, so that software loaded under the debugger
91 //               following a watchdog timeout will not continue to see the
92 //               timeout condition.
93 #define WATCHDOG_REASON_OFFSET _u(0x00000008)
94 #define WATCHDOG_REASON_BITS   _u(0x00000003)
95 #define WATCHDOG_REASON_RESET  _u(0x00000000)
96 // -----------------------------------------------------------------------------
97 // Field       : WATCHDOG_REASON_FORCE
98 #define WATCHDOG_REASON_FORCE_RESET  _u(0x0)
99 #define WATCHDOG_REASON_FORCE_BITS   _u(0x00000002)
100 #define WATCHDOG_REASON_FORCE_MSB    _u(1)
101 #define WATCHDOG_REASON_FORCE_LSB    _u(1)
102 #define WATCHDOG_REASON_FORCE_ACCESS "RO"
103 // -----------------------------------------------------------------------------
104 // Field       : WATCHDOG_REASON_TIMER
105 #define WATCHDOG_REASON_TIMER_RESET  _u(0x0)
106 #define WATCHDOG_REASON_TIMER_BITS   _u(0x00000001)
107 #define WATCHDOG_REASON_TIMER_MSB    _u(0)
108 #define WATCHDOG_REASON_TIMER_LSB    _u(0)
109 #define WATCHDOG_REASON_TIMER_ACCESS "RO"
110 // =============================================================================
111 // Register    : WATCHDOG_SCRATCH0
112 // Description : Scratch register. Information persists through soft reset of
113 //               the chip.
114 #define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
115 #define WATCHDOG_SCRATCH0_BITS   _u(0xffffffff)
116 #define WATCHDOG_SCRATCH0_RESET  _u(0x00000000)
117 #define WATCHDOG_SCRATCH0_MSB    _u(31)
118 #define WATCHDOG_SCRATCH0_LSB    _u(0)
119 #define WATCHDOG_SCRATCH0_ACCESS "RW"
120 // =============================================================================
121 // Register    : WATCHDOG_SCRATCH1
122 // Description : Scratch register. Information persists through soft reset of
123 //               the chip.
124 #define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
125 #define WATCHDOG_SCRATCH1_BITS   _u(0xffffffff)
126 #define WATCHDOG_SCRATCH1_RESET  _u(0x00000000)
127 #define WATCHDOG_SCRATCH1_MSB    _u(31)
128 #define WATCHDOG_SCRATCH1_LSB    _u(0)
129 #define WATCHDOG_SCRATCH1_ACCESS "RW"
130 // =============================================================================
131 // Register    : WATCHDOG_SCRATCH2
132 // Description : Scratch register. Information persists through soft reset of
133 //               the chip.
134 #define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
135 #define WATCHDOG_SCRATCH2_BITS   _u(0xffffffff)
136 #define WATCHDOG_SCRATCH2_RESET  _u(0x00000000)
137 #define WATCHDOG_SCRATCH2_MSB    _u(31)
138 #define WATCHDOG_SCRATCH2_LSB    _u(0)
139 #define WATCHDOG_SCRATCH2_ACCESS "RW"
140 // =============================================================================
141 // Register    : WATCHDOG_SCRATCH3
142 // Description : Scratch register. Information persists through soft reset of
143 //               the chip.
144 #define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
145 #define WATCHDOG_SCRATCH3_BITS   _u(0xffffffff)
146 #define WATCHDOG_SCRATCH3_RESET  _u(0x00000000)
147 #define WATCHDOG_SCRATCH3_MSB    _u(31)
148 #define WATCHDOG_SCRATCH3_LSB    _u(0)
149 #define WATCHDOG_SCRATCH3_ACCESS "RW"
150 // =============================================================================
151 // Register    : WATCHDOG_SCRATCH4
152 // Description : Scratch register. Information persists through soft reset of
153 //               the chip.
154 #define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
155 #define WATCHDOG_SCRATCH4_BITS   _u(0xffffffff)
156 #define WATCHDOG_SCRATCH4_RESET  _u(0x00000000)
157 #define WATCHDOG_SCRATCH4_MSB    _u(31)
158 #define WATCHDOG_SCRATCH4_LSB    _u(0)
159 #define WATCHDOG_SCRATCH4_ACCESS "RW"
160 // =============================================================================
161 // Register    : WATCHDOG_SCRATCH5
162 // Description : Scratch register. Information persists through soft reset of
163 //               the chip.
164 #define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
165 #define WATCHDOG_SCRATCH5_BITS   _u(0xffffffff)
166 #define WATCHDOG_SCRATCH5_RESET  _u(0x00000000)
167 #define WATCHDOG_SCRATCH5_MSB    _u(31)
168 #define WATCHDOG_SCRATCH5_LSB    _u(0)
169 #define WATCHDOG_SCRATCH5_ACCESS "RW"
170 // =============================================================================
171 // Register    : WATCHDOG_SCRATCH6
172 // Description : Scratch register. Information persists through soft reset of
173 //               the chip.
174 #define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
175 #define WATCHDOG_SCRATCH6_BITS   _u(0xffffffff)
176 #define WATCHDOG_SCRATCH6_RESET  _u(0x00000000)
177 #define WATCHDOG_SCRATCH6_MSB    _u(31)
178 #define WATCHDOG_SCRATCH6_LSB    _u(0)
179 #define WATCHDOG_SCRATCH6_ACCESS "RW"
180 // =============================================================================
181 // Register    : WATCHDOG_SCRATCH7
182 // Description : Scratch register. Information persists through soft reset of
183 //               the chip.
184 #define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
185 #define WATCHDOG_SCRATCH7_BITS   _u(0xffffffff)
186 #define WATCHDOG_SCRATCH7_RESET  _u(0x00000000)
187 #define WATCHDOG_SCRATCH7_MSB    _u(31)
188 #define WATCHDOG_SCRATCH7_LSB    _u(0)
189 #define WATCHDOG_SCRATCH7_ACCESS "RW"
190 // =============================================================================
191 #endif // _HARDWARE_REGS_WATCHDOG_H
192 
193