1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : RESETS 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_RESETS_H 14 #define _HARDWARE_REGS_RESETS_H 15 // ============================================================================= 16 // Register : RESETS_RESET 17 #define RESETS_RESET_OFFSET _u(0x00000000) 18 #define RESETS_RESET_BITS _u(0x1fffffff) 19 #define RESETS_RESET_RESET _u(0x1fffffff) 20 // ----------------------------------------------------------------------------- 21 // Field : RESETS_RESET_USBCTRL 22 #define RESETS_RESET_USBCTRL_RESET _u(0x1) 23 #define RESETS_RESET_USBCTRL_BITS _u(0x10000000) 24 #define RESETS_RESET_USBCTRL_MSB _u(28) 25 #define RESETS_RESET_USBCTRL_LSB _u(28) 26 #define RESETS_RESET_USBCTRL_ACCESS "RW" 27 // ----------------------------------------------------------------------------- 28 // Field : RESETS_RESET_UART1 29 #define RESETS_RESET_UART1_RESET _u(0x1) 30 #define RESETS_RESET_UART1_BITS _u(0x08000000) 31 #define RESETS_RESET_UART1_MSB _u(27) 32 #define RESETS_RESET_UART1_LSB _u(27) 33 #define RESETS_RESET_UART1_ACCESS "RW" 34 // ----------------------------------------------------------------------------- 35 // Field : RESETS_RESET_UART0 36 #define RESETS_RESET_UART0_RESET _u(0x1) 37 #define RESETS_RESET_UART0_BITS _u(0x04000000) 38 #define RESETS_RESET_UART0_MSB _u(26) 39 #define RESETS_RESET_UART0_LSB _u(26) 40 #define RESETS_RESET_UART0_ACCESS "RW" 41 // ----------------------------------------------------------------------------- 42 // Field : RESETS_RESET_TRNG 43 #define RESETS_RESET_TRNG_RESET _u(0x1) 44 #define RESETS_RESET_TRNG_BITS _u(0x02000000) 45 #define RESETS_RESET_TRNG_MSB _u(25) 46 #define RESETS_RESET_TRNG_LSB _u(25) 47 #define RESETS_RESET_TRNG_ACCESS "RW" 48 // ----------------------------------------------------------------------------- 49 // Field : RESETS_RESET_TIMER1 50 #define RESETS_RESET_TIMER1_RESET _u(0x1) 51 #define RESETS_RESET_TIMER1_BITS _u(0x01000000) 52 #define RESETS_RESET_TIMER1_MSB _u(24) 53 #define RESETS_RESET_TIMER1_LSB _u(24) 54 #define RESETS_RESET_TIMER1_ACCESS "RW" 55 // ----------------------------------------------------------------------------- 56 // Field : RESETS_RESET_TIMER0 57 #define RESETS_RESET_TIMER0_RESET _u(0x1) 58 #define RESETS_RESET_TIMER0_BITS _u(0x00800000) 59 #define RESETS_RESET_TIMER0_MSB _u(23) 60 #define RESETS_RESET_TIMER0_LSB _u(23) 61 #define RESETS_RESET_TIMER0_ACCESS "RW" 62 // ----------------------------------------------------------------------------- 63 // Field : RESETS_RESET_TBMAN 64 #define RESETS_RESET_TBMAN_RESET _u(0x1) 65 #define RESETS_RESET_TBMAN_BITS _u(0x00400000) 66 #define RESETS_RESET_TBMAN_MSB _u(22) 67 #define RESETS_RESET_TBMAN_LSB _u(22) 68 #define RESETS_RESET_TBMAN_ACCESS "RW" 69 // ----------------------------------------------------------------------------- 70 // Field : RESETS_RESET_SYSINFO 71 #define RESETS_RESET_SYSINFO_RESET _u(0x1) 72 #define RESETS_RESET_SYSINFO_BITS _u(0x00200000) 73 #define RESETS_RESET_SYSINFO_MSB _u(21) 74 #define RESETS_RESET_SYSINFO_LSB _u(21) 75 #define RESETS_RESET_SYSINFO_ACCESS "RW" 76 // ----------------------------------------------------------------------------- 77 // Field : RESETS_RESET_SYSCFG 78 #define RESETS_RESET_SYSCFG_RESET _u(0x1) 79 #define RESETS_RESET_SYSCFG_BITS _u(0x00100000) 80 #define RESETS_RESET_SYSCFG_MSB _u(20) 81 #define RESETS_RESET_SYSCFG_LSB _u(20) 82 #define RESETS_RESET_SYSCFG_ACCESS "RW" 83 // ----------------------------------------------------------------------------- 84 // Field : RESETS_RESET_SPI1 85 #define RESETS_RESET_SPI1_RESET _u(0x1) 86 #define RESETS_RESET_SPI1_BITS _u(0x00080000) 87 #define RESETS_RESET_SPI1_MSB _u(19) 88 #define RESETS_RESET_SPI1_LSB _u(19) 89 #define RESETS_RESET_SPI1_ACCESS "RW" 90 // ----------------------------------------------------------------------------- 91 // Field : RESETS_RESET_SPI0 92 #define RESETS_RESET_SPI0_RESET _u(0x1) 93 #define RESETS_RESET_SPI0_BITS _u(0x00040000) 94 #define RESETS_RESET_SPI0_MSB _u(18) 95 #define RESETS_RESET_SPI0_LSB _u(18) 96 #define RESETS_RESET_SPI0_ACCESS "RW" 97 // ----------------------------------------------------------------------------- 98 // Field : RESETS_RESET_SHA256 99 #define RESETS_RESET_SHA256_RESET _u(0x1) 100 #define RESETS_RESET_SHA256_BITS _u(0x00020000) 101 #define RESETS_RESET_SHA256_MSB _u(17) 102 #define RESETS_RESET_SHA256_LSB _u(17) 103 #define RESETS_RESET_SHA256_ACCESS "RW" 104 // ----------------------------------------------------------------------------- 105 // Field : RESETS_RESET_PWM 106 #define RESETS_RESET_PWM_RESET _u(0x1) 107 #define RESETS_RESET_PWM_BITS _u(0x00010000) 108 #define RESETS_RESET_PWM_MSB _u(16) 109 #define RESETS_RESET_PWM_LSB _u(16) 110 #define RESETS_RESET_PWM_ACCESS "RW" 111 // ----------------------------------------------------------------------------- 112 // Field : RESETS_RESET_PLL_USB 113 #define RESETS_RESET_PLL_USB_RESET _u(0x1) 114 #define RESETS_RESET_PLL_USB_BITS _u(0x00008000) 115 #define RESETS_RESET_PLL_USB_MSB _u(15) 116 #define RESETS_RESET_PLL_USB_LSB _u(15) 117 #define RESETS_RESET_PLL_USB_ACCESS "RW" 118 // ----------------------------------------------------------------------------- 119 // Field : RESETS_RESET_PLL_SYS 120 #define RESETS_RESET_PLL_SYS_RESET _u(0x1) 121 #define RESETS_RESET_PLL_SYS_BITS _u(0x00004000) 122 #define RESETS_RESET_PLL_SYS_MSB _u(14) 123 #define RESETS_RESET_PLL_SYS_LSB _u(14) 124 #define RESETS_RESET_PLL_SYS_ACCESS "RW" 125 // ----------------------------------------------------------------------------- 126 // Field : RESETS_RESET_PIO2 127 #define RESETS_RESET_PIO2_RESET _u(0x1) 128 #define RESETS_RESET_PIO2_BITS _u(0x00002000) 129 #define RESETS_RESET_PIO2_MSB _u(13) 130 #define RESETS_RESET_PIO2_LSB _u(13) 131 #define RESETS_RESET_PIO2_ACCESS "RW" 132 // ----------------------------------------------------------------------------- 133 // Field : RESETS_RESET_PIO1 134 #define RESETS_RESET_PIO1_RESET _u(0x1) 135 #define RESETS_RESET_PIO1_BITS _u(0x00001000) 136 #define RESETS_RESET_PIO1_MSB _u(12) 137 #define RESETS_RESET_PIO1_LSB _u(12) 138 #define RESETS_RESET_PIO1_ACCESS "RW" 139 // ----------------------------------------------------------------------------- 140 // Field : RESETS_RESET_PIO0 141 #define RESETS_RESET_PIO0_RESET _u(0x1) 142 #define RESETS_RESET_PIO0_BITS _u(0x00000800) 143 #define RESETS_RESET_PIO0_MSB _u(11) 144 #define RESETS_RESET_PIO0_LSB _u(11) 145 #define RESETS_RESET_PIO0_ACCESS "RW" 146 // ----------------------------------------------------------------------------- 147 // Field : RESETS_RESET_PADS_QSPI 148 #define RESETS_RESET_PADS_QSPI_RESET _u(0x1) 149 #define RESETS_RESET_PADS_QSPI_BITS _u(0x00000400) 150 #define RESETS_RESET_PADS_QSPI_MSB _u(10) 151 #define RESETS_RESET_PADS_QSPI_LSB _u(10) 152 #define RESETS_RESET_PADS_QSPI_ACCESS "RW" 153 // ----------------------------------------------------------------------------- 154 // Field : RESETS_RESET_PADS_BANK0 155 #define RESETS_RESET_PADS_BANK0_RESET _u(0x1) 156 #define RESETS_RESET_PADS_BANK0_BITS _u(0x00000200) 157 #define RESETS_RESET_PADS_BANK0_MSB _u(9) 158 #define RESETS_RESET_PADS_BANK0_LSB _u(9) 159 #define RESETS_RESET_PADS_BANK0_ACCESS "RW" 160 // ----------------------------------------------------------------------------- 161 // Field : RESETS_RESET_JTAG 162 #define RESETS_RESET_JTAG_RESET _u(0x1) 163 #define RESETS_RESET_JTAG_BITS _u(0x00000100) 164 #define RESETS_RESET_JTAG_MSB _u(8) 165 #define RESETS_RESET_JTAG_LSB _u(8) 166 #define RESETS_RESET_JTAG_ACCESS "RW" 167 // ----------------------------------------------------------------------------- 168 // Field : RESETS_RESET_IO_QSPI 169 #define RESETS_RESET_IO_QSPI_RESET _u(0x1) 170 #define RESETS_RESET_IO_QSPI_BITS _u(0x00000080) 171 #define RESETS_RESET_IO_QSPI_MSB _u(7) 172 #define RESETS_RESET_IO_QSPI_LSB _u(7) 173 #define RESETS_RESET_IO_QSPI_ACCESS "RW" 174 // ----------------------------------------------------------------------------- 175 // Field : RESETS_RESET_IO_BANK0 176 #define RESETS_RESET_IO_BANK0_RESET _u(0x1) 177 #define RESETS_RESET_IO_BANK0_BITS _u(0x00000040) 178 #define RESETS_RESET_IO_BANK0_MSB _u(6) 179 #define RESETS_RESET_IO_BANK0_LSB _u(6) 180 #define RESETS_RESET_IO_BANK0_ACCESS "RW" 181 // ----------------------------------------------------------------------------- 182 // Field : RESETS_RESET_I2C1 183 #define RESETS_RESET_I2C1_RESET _u(0x1) 184 #define RESETS_RESET_I2C1_BITS _u(0x00000020) 185 #define RESETS_RESET_I2C1_MSB _u(5) 186 #define RESETS_RESET_I2C1_LSB _u(5) 187 #define RESETS_RESET_I2C1_ACCESS "RW" 188 // ----------------------------------------------------------------------------- 189 // Field : RESETS_RESET_I2C0 190 #define RESETS_RESET_I2C0_RESET _u(0x1) 191 #define RESETS_RESET_I2C0_BITS _u(0x00000010) 192 #define RESETS_RESET_I2C0_MSB _u(4) 193 #define RESETS_RESET_I2C0_LSB _u(4) 194 #define RESETS_RESET_I2C0_ACCESS "RW" 195 // ----------------------------------------------------------------------------- 196 // Field : RESETS_RESET_HSTX 197 #define RESETS_RESET_HSTX_RESET _u(0x1) 198 #define RESETS_RESET_HSTX_BITS _u(0x00000008) 199 #define RESETS_RESET_HSTX_MSB _u(3) 200 #define RESETS_RESET_HSTX_LSB _u(3) 201 #define RESETS_RESET_HSTX_ACCESS "RW" 202 // ----------------------------------------------------------------------------- 203 // Field : RESETS_RESET_DMA 204 #define RESETS_RESET_DMA_RESET _u(0x1) 205 #define RESETS_RESET_DMA_BITS _u(0x00000004) 206 #define RESETS_RESET_DMA_MSB _u(2) 207 #define RESETS_RESET_DMA_LSB _u(2) 208 #define RESETS_RESET_DMA_ACCESS "RW" 209 // ----------------------------------------------------------------------------- 210 // Field : RESETS_RESET_BUSCTRL 211 #define RESETS_RESET_BUSCTRL_RESET _u(0x1) 212 #define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) 213 #define RESETS_RESET_BUSCTRL_MSB _u(1) 214 #define RESETS_RESET_BUSCTRL_LSB _u(1) 215 #define RESETS_RESET_BUSCTRL_ACCESS "RW" 216 // ----------------------------------------------------------------------------- 217 // Field : RESETS_RESET_ADC 218 #define RESETS_RESET_ADC_RESET _u(0x1) 219 #define RESETS_RESET_ADC_BITS _u(0x00000001) 220 #define RESETS_RESET_ADC_MSB _u(0) 221 #define RESETS_RESET_ADC_LSB _u(0) 222 #define RESETS_RESET_ADC_ACCESS "RW" 223 // ============================================================================= 224 // Register : RESETS_WDSEL 225 #define RESETS_WDSEL_OFFSET _u(0x00000004) 226 #define RESETS_WDSEL_BITS _u(0x1fffffff) 227 #define RESETS_WDSEL_RESET _u(0x00000000) 228 // ----------------------------------------------------------------------------- 229 // Field : RESETS_WDSEL_USBCTRL 230 #define RESETS_WDSEL_USBCTRL_RESET _u(0x0) 231 #define RESETS_WDSEL_USBCTRL_BITS _u(0x10000000) 232 #define RESETS_WDSEL_USBCTRL_MSB _u(28) 233 #define RESETS_WDSEL_USBCTRL_LSB _u(28) 234 #define RESETS_WDSEL_USBCTRL_ACCESS "RW" 235 // ----------------------------------------------------------------------------- 236 // Field : RESETS_WDSEL_UART1 237 #define RESETS_WDSEL_UART1_RESET _u(0x0) 238 #define RESETS_WDSEL_UART1_BITS _u(0x08000000) 239 #define RESETS_WDSEL_UART1_MSB _u(27) 240 #define RESETS_WDSEL_UART1_LSB _u(27) 241 #define RESETS_WDSEL_UART1_ACCESS "RW" 242 // ----------------------------------------------------------------------------- 243 // Field : RESETS_WDSEL_UART0 244 #define RESETS_WDSEL_UART0_RESET _u(0x0) 245 #define RESETS_WDSEL_UART0_BITS _u(0x04000000) 246 #define RESETS_WDSEL_UART0_MSB _u(26) 247 #define RESETS_WDSEL_UART0_LSB _u(26) 248 #define RESETS_WDSEL_UART0_ACCESS "RW" 249 // ----------------------------------------------------------------------------- 250 // Field : RESETS_WDSEL_TRNG 251 #define RESETS_WDSEL_TRNG_RESET _u(0x0) 252 #define RESETS_WDSEL_TRNG_BITS _u(0x02000000) 253 #define RESETS_WDSEL_TRNG_MSB _u(25) 254 #define RESETS_WDSEL_TRNG_LSB _u(25) 255 #define RESETS_WDSEL_TRNG_ACCESS "RW" 256 // ----------------------------------------------------------------------------- 257 // Field : RESETS_WDSEL_TIMER1 258 #define RESETS_WDSEL_TIMER1_RESET _u(0x0) 259 #define RESETS_WDSEL_TIMER1_BITS _u(0x01000000) 260 #define RESETS_WDSEL_TIMER1_MSB _u(24) 261 #define RESETS_WDSEL_TIMER1_LSB _u(24) 262 #define RESETS_WDSEL_TIMER1_ACCESS "RW" 263 // ----------------------------------------------------------------------------- 264 // Field : RESETS_WDSEL_TIMER0 265 #define RESETS_WDSEL_TIMER0_RESET _u(0x0) 266 #define RESETS_WDSEL_TIMER0_BITS _u(0x00800000) 267 #define RESETS_WDSEL_TIMER0_MSB _u(23) 268 #define RESETS_WDSEL_TIMER0_LSB _u(23) 269 #define RESETS_WDSEL_TIMER0_ACCESS "RW" 270 // ----------------------------------------------------------------------------- 271 // Field : RESETS_WDSEL_TBMAN 272 #define RESETS_WDSEL_TBMAN_RESET _u(0x0) 273 #define RESETS_WDSEL_TBMAN_BITS _u(0x00400000) 274 #define RESETS_WDSEL_TBMAN_MSB _u(22) 275 #define RESETS_WDSEL_TBMAN_LSB _u(22) 276 #define RESETS_WDSEL_TBMAN_ACCESS "RW" 277 // ----------------------------------------------------------------------------- 278 // Field : RESETS_WDSEL_SYSINFO 279 #define RESETS_WDSEL_SYSINFO_RESET _u(0x0) 280 #define RESETS_WDSEL_SYSINFO_BITS _u(0x00200000) 281 #define RESETS_WDSEL_SYSINFO_MSB _u(21) 282 #define RESETS_WDSEL_SYSINFO_LSB _u(21) 283 #define RESETS_WDSEL_SYSINFO_ACCESS "RW" 284 // ----------------------------------------------------------------------------- 285 // Field : RESETS_WDSEL_SYSCFG 286 #define RESETS_WDSEL_SYSCFG_RESET _u(0x0) 287 #define RESETS_WDSEL_SYSCFG_BITS _u(0x00100000) 288 #define RESETS_WDSEL_SYSCFG_MSB _u(20) 289 #define RESETS_WDSEL_SYSCFG_LSB _u(20) 290 #define RESETS_WDSEL_SYSCFG_ACCESS "RW" 291 // ----------------------------------------------------------------------------- 292 // Field : RESETS_WDSEL_SPI1 293 #define RESETS_WDSEL_SPI1_RESET _u(0x0) 294 #define RESETS_WDSEL_SPI1_BITS _u(0x00080000) 295 #define RESETS_WDSEL_SPI1_MSB _u(19) 296 #define RESETS_WDSEL_SPI1_LSB _u(19) 297 #define RESETS_WDSEL_SPI1_ACCESS "RW" 298 // ----------------------------------------------------------------------------- 299 // Field : RESETS_WDSEL_SPI0 300 #define RESETS_WDSEL_SPI0_RESET _u(0x0) 301 #define RESETS_WDSEL_SPI0_BITS _u(0x00040000) 302 #define RESETS_WDSEL_SPI0_MSB _u(18) 303 #define RESETS_WDSEL_SPI0_LSB _u(18) 304 #define RESETS_WDSEL_SPI0_ACCESS "RW" 305 // ----------------------------------------------------------------------------- 306 // Field : RESETS_WDSEL_SHA256 307 #define RESETS_WDSEL_SHA256_RESET _u(0x0) 308 #define RESETS_WDSEL_SHA256_BITS _u(0x00020000) 309 #define RESETS_WDSEL_SHA256_MSB _u(17) 310 #define RESETS_WDSEL_SHA256_LSB _u(17) 311 #define RESETS_WDSEL_SHA256_ACCESS "RW" 312 // ----------------------------------------------------------------------------- 313 // Field : RESETS_WDSEL_PWM 314 #define RESETS_WDSEL_PWM_RESET _u(0x0) 315 #define RESETS_WDSEL_PWM_BITS _u(0x00010000) 316 #define RESETS_WDSEL_PWM_MSB _u(16) 317 #define RESETS_WDSEL_PWM_LSB _u(16) 318 #define RESETS_WDSEL_PWM_ACCESS "RW" 319 // ----------------------------------------------------------------------------- 320 // Field : RESETS_WDSEL_PLL_USB 321 #define RESETS_WDSEL_PLL_USB_RESET _u(0x0) 322 #define RESETS_WDSEL_PLL_USB_BITS _u(0x00008000) 323 #define RESETS_WDSEL_PLL_USB_MSB _u(15) 324 #define RESETS_WDSEL_PLL_USB_LSB _u(15) 325 #define RESETS_WDSEL_PLL_USB_ACCESS "RW" 326 // ----------------------------------------------------------------------------- 327 // Field : RESETS_WDSEL_PLL_SYS 328 #define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) 329 #define RESETS_WDSEL_PLL_SYS_BITS _u(0x00004000) 330 #define RESETS_WDSEL_PLL_SYS_MSB _u(14) 331 #define RESETS_WDSEL_PLL_SYS_LSB _u(14) 332 #define RESETS_WDSEL_PLL_SYS_ACCESS "RW" 333 // ----------------------------------------------------------------------------- 334 // Field : RESETS_WDSEL_PIO2 335 #define RESETS_WDSEL_PIO2_RESET _u(0x0) 336 #define RESETS_WDSEL_PIO2_BITS _u(0x00002000) 337 #define RESETS_WDSEL_PIO2_MSB _u(13) 338 #define RESETS_WDSEL_PIO2_LSB _u(13) 339 #define RESETS_WDSEL_PIO2_ACCESS "RW" 340 // ----------------------------------------------------------------------------- 341 // Field : RESETS_WDSEL_PIO1 342 #define RESETS_WDSEL_PIO1_RESET _u(0x0) 343 #define RESETS_WDSEL_PIO1_BITS _u(0x00001000) 344 #define RESETS_WDSEL_PIO1_MSB _u(12) 345 #define RESETS_WDSEL_PIO1_LSB _u(12) 346 #define RESETS_WDSEL_PIO1_ACCESS "RW" 347 // ----------------------------------------------------------------------------- 348 // Field : RESETS_WDSEL_PIO0 349 #define RESETS_WDSEL_PIO0_RESET _u(0x0) 350 #define RESETS_WDSEL_PIO0_BITS _u(0x00000800) 351 #define RESETS_WDSEL_PIO0_MSB _u(11) 352 #define RESETS_WDSEL_PIO0_LSB _u(11) 353 #define RESETS_WDSEL_PIO0_ACCESS "RW" 354 // ----------------------------------------------------------------------------- 355 // Field : RESETS_WDSEL_PADS_QSPI 356 #define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) 357 #define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000400) 358 #define RESETS_WDSEL_PADS_QSPI_MSB _u(10) 359 #define RESETS_WDSEL_PADS_QSPI_LSB _u(10) 360 #define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" 361 // ----------------------------------------------------------------------------- 362 // Field : RESETS_WDSEL_PADS_BANK0 363 #define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) 364 #define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000200) 365 #define RESETS_WDSEL_PADS_BANK0_MSB _u(9) 366 #define RESETS_WDSEL_PADS_BANK0_LSB _u(9) 367 #define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" 368 // ----------------------------------------------------------------------------- 369 // Field : RESETS_WDSEL_JTAG 370 #define RESETS_WDSEL_JTAG_RESET _u(0x0) 371 #define RESETS_WDSEL_JTAG_BITS _u(0x00000100) 372 #define RESETS_WDSEL_JTAG_MSB _u(8) 373 #define RESETS_WDSEL_JTAG_LSB _u(8) 374 #define RESETS_WDSEL_JTAG_ACCESS "RW" 375 // ----------------------------------------------------------------------------- 376 // Field : RESETS_WDSEL_IO_QSPI 377 #define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) 378 #define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000080) 379 #define RESETS_WDSEL_IO_QSPI_MSB _u(7) 380 #define RESETS_WDSEL_IO_QSPI_LSB _u(7) 381 #define RESETS_WDSEL_IO_QSPI_ACCESS "RW" 382 // ----------------------------------------------------------------------------- 383 // Field : RESETS_WDSEL_IO_BANK0 384 #define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) 385 #define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000040) 386 #define RESETS_WDSEL_IO_BANK0_MSB _u(6) 387 #define RESETS_WDSEL_IO_BANK0_LSB _u(6) 388 #define RESETS_WDSEL_IO_BANK0_ACCESS "RW" 389 // ----------------------------------------------------------------------------- 390 // Field : RESETS_WDSEL_I2C1 391 #define RESETS_WDSEL_I2C1_RESET _u(0x0) 392 #define RESETS_WDSEL_I2C1_BITS _u(0x00000020) 393 #define RESETS_WDSEL_I2C1_MSB _u(5) 394 #define RESETS_WDSEL_I2C1_LSB _u(5) 395 #define RESETS_WDSEL_I2C1_ACCESS "RW" 396 // ----------------------------------------------------------------------------- 397 // Field : RESETS_WDSEL_I2C0 398 #define RESETS_WDSEL_I2C0_RESET _u(0x0) 399 #define RESETS_WDSEL_I2C0_BITS _u(0x00000010) 400 #define RESETS_WDSEL_I2C0_MSB _u(4) 401 #define RESETS_WDSEL_I2C0_LSB _u(4) 402 #define RESETS_WDSEL_I2C0_ACCESS "RW" 403 // ----------------------------------------------------------------------------- 404 // Field : RESETS_WDSEL_HSTX 405 #define RESETS_WDSEL_HSTX_RESET _u(0x0) 406 #define RESETS_WDSEL_HSTX_BITS _u(0x00000008) 407 #define RESETS_WDSEL_HSTX_MSB _u(3) 408 #define RESETS_WDSEL_HSTX_LSB _u(3) 409 #define RESETS_WDSEL_HSTX_ACCESS "RW" 410 // ----------------------------------------------------------------------------- 411 // Field : RESETS_WDSEL_DMA 412 #define RESETS_WDSEL_DMA_RESET _u(0x0) 413 #define RESETS_WDSEL_DMA_BITS _u(0x00000004) 414 #define RESETS_WDSEL_DMA_MSB _u(2) 415 #define RESETS_WDSEL_DMA_LSB _u(2) 416 #define RESETS_WDSEL_DMA_ACCESS "RW" 417 // ----------------------------------------------------------------------------- 418 // Field : RESETS_WDSEL_BUSCTRL 419 #define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) 420 #define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) 421 #define RESETS_WDSEL_BUSCTRL_MSB _u(1) 422 #define RESETS_WDSEL_BUSCTRL_LSB _u(1) 423 #define RESETS_WDSEL_BUSCTRL_ACCESS "RW" 424 // ----------------------------------------------------------------------------- 425 // Field : RESETS_WDSEL_ADC 426 #define RESETS_WDSEL_ADC_RESET _u(0x0) 427 #define RESETS_WDSEL_ADC_BITS _u(0x00000001) 428 #define RESETS_WDSEL_ADC_MSB _u(0) 429 #define RESETS_WDSEL_ADC_LSB _u(0) 430 #define RESETS_WDSEL_ADC_ACCESS "RW" 431 // ============================================================================= 432 // Register : RESETS_RESET_DONE 433 #define RESETS_RESET_DONE_OFFSET _u(0x00000008) 434 #define RESETS_RESET_DONE_BITS _u(0x1fffffff) 435 #define RESETS_RESET_DONE_RESET _u(0x00000000) 436 // ----------------------------------------------------------------------------- 437 // Field : RESETS_RESET_DONE_USBCTRL 438 #define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) 439 #define RESETS_RESET_DONE_USBCTRL_BITS _u(0x10000000) 440 #define RESETS_RESET_DONE_USBCTRL_MSB _u(28) 441 #define RESETS_RESET_DONE_USBCTRL_LSB _u(28) 442 #define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" 443 // ----------------------------------------------------------------------------- 444 // Field : RESETS_RESET_DONE_UART1 445 #define RESETS_RESET_DONE_UART1_RESET _u(0x0) 446 #define RESETS_RESET_DONE_UART1_BITS _u(0x08000000) 447 #define RESETS_RESET_DONE_UART1_MSB _u(27) 448 #define RESETS_RESET_DONE_UART1_LSB _u(27) 449 #define RESETS_RESET_DONE_UART1_ACCESS "RO" 450 // ----------------------------------------------------------------------------- 451 // Field : RESETS_RESET_DONE_UART0 452 #define RESETS_RESET_DONE_UART0_RESET _u(0x0) 453 #define RESETS_RESET_DONE_UART0_BITS _u(0x04000000) 454 #define RESETS_RESET_DONE_UART0_MSB _u(26) 455 #define RESETS_RESET_DONE_UART0_LSB _u(26) 456 #define RESETS_RESET_DONE_UART0_ACCESS "RO" 457 // ----------------------------------------------------------------------------- 458 // Field : RESETS_RESET_DONE_TRNG 459 #define RESETS_RESET_DONE_TRNG_RESET _u(0x0) 460 #define RESETS_RESET_DONE_TRNG_BITS _u(0x02000000) 461 #define RESETS_RESET_DONE_TRNG_MSB _u(25) 462 #define RESETS_RESET_DONE_TRNG_LSB _u(25) 463 #define RESETS_RESET_DONE_TRNG_ACCESS "RO" 464 // ----------------------------------------------------------------------------- 465 // Field : RESETS_RESET_DONE_TIMER1 466 #define RESETS_RESET_DONE_TIMER1_RESET _u(0x0) 467 #define RESETS_RESET_DONE_TIMER1_BITS _u(0x01000000) 468 #define RESETS_RESET_DONE_TIMER1_MSB _u(24) 469 #define RESETS_RESET_DONE_TIMER1_LSB _u(24) 470 #define RESETS_RESET_DONE_TIMER1_ACCESS "RO" 471 // ----------------------------------------------------------------------------- 472 // Field : RESETS_RESET_DONE_TIMER0 473 #define RESETS_RESET_DONE_TIMER0_RESET _u(0x0) 474 #define RESETS_RESET_DONE_TIMER0_BITS _u(0x00800000) 475 #define RESETS_RESET_DONE_TIMER0_MSB _u(23) 476 #define RESETS_RESET_DONE_TIMER0_LSB _u(23) 477 #define RESETS_RESET_DONE_TIMER0_ACCESS "RO" 478 // ----------------------------------------------------------------------------- 479 // Field : RESETS_RESET_DONE_TBMAN 480 #define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) 481 #define RESETS_RESET_DONE_TBMAN_BITS _u(0x00400000) 482 #define RESETS_RESET_DONE_TBMAN_MSB _u(22) 483 #define RESETS_RESET_DONE_TBMAN_LSB _u(22) 484 #define RESETS_RESET_DONE_TBMAN_ACCESS "RO" 485 // ----------------------------------------------------------------------------- 486 // Field : RESETS_RESET_DONE_SYSINFO 487 #define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) 488 #define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00200000) 489 #define RESETS_RESET_DONE_SYSINFO_MSB _u(21) 490 #define RESETS_RESET_DONE_SYSINFO_LSB _u(21) 491 #define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" 492 // ----------------------------------------------------------------------------- 493 // Field : RESETS_RESET_DONE_SYSCFG 494 #define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) 495 #define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00100000) 496 #define RESETS_RESET_DONE_SYSCFG_MSB _u(20) 497 #define RESETS_RESET_DONE_SYSCFG_LSB _u(20) 498 #define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" 499 // ----------------------------------------------------------------------------- 500 // Field : RESETS_RESET_DONE_SPI1 501 #define RESETS_RESET_DONE_SPI1_RESET _u(0x0) 502 #define RESETS_RESET_DONE_SPI1_BITS _u(0x00080000) 503 #define RESETS_RESET_DONE_SPI1_MSB _u(19) 504 #define RESETS_RESET_DONE_SPI1_LSB _u(19) 505 #define RESETS_RESET_DONE_SPI1_ACCESS "RO" 506 // ----------------------------------------------------------------------------- 507 // Field : RESETS_RESET_DONE_SPI0 508 #define RESETS_RESET_DONE_SPI0_RESET _u(0x0) 509 #define RESETS_RESET_DONE_SPI0_BITS _u(0x00040000) 510 #define RESETS_RESET_DONE_SPI0_MSB _u(18) 511 #define RESETS_RESET_DONE_SPI0_LSB _u(18) 512 #define RESETS_RESET_DONE_SPI0_ACCESS "RO" 513 // ----------------------------------------------------------------------------- 514 // Field : RESETS_RESET_DONE_SHA256 515 #define RESETS_RESET_DONE_SHA256_RESET _u(0x0) 516 #define RESETS_RESET_DONE_SHA256_BITS _u(0x00020000) 517 #define RESETS_RESET_DONE_SHA256_MSB _u(17) 518 #define RESETS_RESET_DONE_SHA256_LSB _u(17) 519 #define RESETS_RESET_DONE_SHA256_ACCESS "RO" 520 // ----------------------------------------------------------------------------- 521 // Field : RESETS_RESET_DONE_PWM 522 #define RESETS_RESET_DONE_PWM_RESET _u(0x0) 523 #define RESETS_RESET_DONE_PWM_BITS _u(0x00010000) 524 #define RESETS_RESET_DONE_PWM_MSB _u(16) 525 #define RESETS_RESET_DONE_PWM_LSB _u(16) 526 #define RESETS_RESET_DONE_PWM_ACCESS "RO" 527 // ----------------------------------------------------------------------------- 528 // Field : RESETS_RESET_DONE_PLL_USB 529 #define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) 530 #define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00008000) 531 #define RESETS_RESET_DONE_PLL_USB_MSB _u(15) 532 #define RESETS_RESET_DONE_PLL_USB_LSB _u(15) 533 #define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" 534 // ----------------------------------------------------------------------------- 535 // Field : RESETS_RESET_DONE_PLL_SYS 536 #define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) 537 #define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00004000) 538 #define RESETS_RESET_DONE_PLL_SYS_MSB _u(14) 539 #define RESETS_RESET_DONE_PLL_SYS_LSB _u(14) 540 #define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" 541 // ----------------------------------------------------------------------------- 542 // Field : RESETS_RESET_DONE_PIO2 543 #define RESETS_RESET_DONE_PIO2_RESET _u(0x0) 544 #define RESETS_RESET_DONE_PIO2_BITS _u(0x00002000) 545 #define RESETS_RESET_DONE_PIO2_MSB _u(13) 546 #define RESETS_RESET_DONE_PIO2_LSB _u(13) 547 #define RESETS_RESET_DONE_PIO2_ACCESS "RO" 548 // ----------------------------------------------------------------------------- 549 // Field : RESETS_RESET_DONE_PIO1 550 #define RESETS_RESET_DONE_PIO1_RESET _u(0x0) 551 #define RESETS_RESET_DONE_PIO1_BITS _u(0x00001000) 552 #define RESETS_RESET_DONE_PIO1_MSB _u(12) 553 #define RESETS_RESET_DONE_PIO1_LSB _u(12) 554 #define RESETS_RESET_DONE_PIO1_ACCESS "RO" 555 // ----------------------------------------------------------------------------- 556 // Field : RESETS_RESET_DONE_PIO0 557 #define RESETS_RESET_DONE_PIO0_RESET _u(0x0) 558 #define RESETS_RESET_DONE_PIO0_BITS _u(0x00000800) 559 #define RESETS_RESET_DONE_PIO0_MSB _u(11) 560 #define RESETS_RESET_DONE_PIO0_LSB _u(11) 561 #define RESETS_RESET_DONE_PIO0_ACCESS "RO" 562 // ----------------------------------------------------------------------------- 563 // Field : RESETS_RESET_DONE_PADS_QSPI 564 #define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) 565 #define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000400) 566 #define RESETS_RESET_DONE_PADS_QSPI_MSB _u(10) 567 #define RESETS_RESET_DONE_PADS_QSPI_LSB _u(10) 568 #define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" 569 // ----------------------------------------------------------------------------- 570 // Field : RESETS_RESET_DONE_PADS_BANK0 571 #define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) 572 #define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000200) 573 #define RESETS_RESET_DONE_PADS_BANK0_MSB _u(9) 574 #define RESETS_RESET_DONE_PADS_BANK0_LSB _u(9) 575 #define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" 576 // ----------------------------------------------------------------------------- 577 // Field : RESETS_RESET_DONE_JTAG 578 #define RESETS_RESET_DONE_JTAG_RESET _u(0x0) 579 #define RESETS_RESET_DONE_JTAG_BITS _u(0x00000100) 580 #define RESETS_RESET_DONE_JTAG_MSB _u(8) 581 #define RESETS_RESET_DONE_JTAG_LSB _u(8) 582 #define RESETS_RESET_DONE_JTAG_ACCESS "RO" 583 // ----------------------------------------------------------------------------- 584 // Field : RESETS_RESET_DONE_IO_QSPI 585 #define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) 586 #define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000080) 587 #define RESETS_RESET_DONE_IO_QSPI_MSB _u(7) 588 #define RESETS_RESET_DONE_IO_QSPI_LSB _u(7) 589 #define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" 590 // ----------------------------------------------------------------------------- 591 // Field : RESETS_RESET_DONE_IO_BANK0 592 #define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) 593 #define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000040) 594 #define RESETS_RESET_DONE_IO_BANK0_MSB _u(6) 595 #define RESETS_RESET_DONE_IO_BANK0_LSB _u(6) 596 #define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" 597 // ----------------------------------------------------------------------------- 598 // Field : RESETS_RESET_DONE_I2C1 599 #define RESETS_RESET_DONE_I2C1_RESET _u(0x0) 600 #define RESETS_RESET_DONE_I2C1_BITS _u(0x00000020) 601 #define RESETS_RESET_DONE_I2C1_MSB _u(5) 602 #define RESETS_RESET_DONE_I2C1_LSB _u(5) 603 #define RESETS_RESET_DONE_I2C1_ACCESS "RO" 604 // ----------------------------------------------------------------------------- 605 // Field : RESETS_RESET_DONE_I2C0 606 #define RESETS_RESET_DONE_I2C0_RESET _u(0x0) 607 #define RESETS_RESET_DONE_I2C0_BITS _u(0x00000010) 608 #define RESETS_RESET_DONE_I2C0_MSB _u(4) 609 #define RESETS_RESET_DONE_I2C0_LSB _u(4) 610 #define RESETS_RESET_DONE_I2C0_ACCESS "RO" 611 // ----------------------------------------------------------------------------- 612 // Field : RESETS_RESET_DONE_HSTX 613 #define RESETS_RESET_DONE_HSTX_RESET _u(0x0) 614 #define RESETS_RESET_DONE_HSTX_BITS _u(0x00000008) 615 #define RESETS_RESET_DONE_HSTX_MSB _u(3) 616 #define RESETS_RESET_DONE_HSTX_LSB _u(3) 617 #define RESETS_RESET_DONE_HSTX_ACCESS "RO" 618 // ----------------------------------------------------------------------------- 619 // Field : RESETS_RESET_DONE_DMA 620 #define RESETS_RESET_DONE_DMA_RESET _u(0x0) 621 #define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) 622 #define RESETS_RESET_DONE_DMA_MSB _u(2) 623 #define RESETS_RESET_DONE_DMA_LSB _u(2) 624 #define RESETS_RESET_DONE_DMA_ACCESS "RO" 625 // ----------------------------------------------------------------------------- 626 // Field : RESETS_RESET_DONE_BUSCTRL 627 #define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) 628 #define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) 629 #define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) 630 #define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) 631 #define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" 632 // ----------------------------------------------------------------------------- 633 // Field : RESETS_RESET_DONE_ADC 634 #define RESETS_RESET_DONE_ADC_RESET _u(0x0) 635 #define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) 636 #define RESETS_RESET_DONE_ADC_MSB _u(0) 637 #define RESETS_RESET_DONE_ADC_LSB _u(0) 638 #define RESETS_RESET_DONE_ADC_ACCESS "RO" 639 // ============================================================================= 640 #endif // _HARDWARE_REGS_RESETS_H 641 642
