1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : PADS_QSPI 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_PADS_QSPI_H 14 #define _HARDWARE_REGS_PADS_QSPI_H 15 // ============================================================================= 16 // Register : PADS_QSPI_VOLTAGE_SELECT 17 // Description : Voltage select. Per bank control 18 // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) 19 // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) 20 #define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) 21 #define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) 22 #define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) 23 #define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) 24 #define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) 25 #define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" 26 #define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) 27 #define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) 28 // ============================================================================= 29 // Register : PADS_QSPI_GPIO_QSPI_SCLK 30 #define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004) 31 #define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000001ff) 32 #define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000156) 33 // ----------------------------------------------------------------------------- 34 // Field : PADS_QSPI_GPIO_QSPI_SCLK_ISO 35 // Description : Pad isolation control. Remove this once the pad is configured 36 // by software. 37 #define PADS_QSPI_GPIO_QSPI_SCLK_ISO_RESET _u(0x1) 38 #define PADS_QSPI_GPIO_QSPI_SCLK_ISO_BITS _u(0x00000100) 39 #define PADS_QSPI_GPIO_QSPI_SCLK_ISO_MSB _u(8) 40 #define PADS_QSPI_GPIO_QSPI_SCLK_ISO_LSB _u(8) 41 #define PADS_QSPI_GPIO_QSPI_SCLK_ISO_ACCESS "RW" 42 // ----------------------------------------------------------------------------- 43 // Field : PADS_QSPI_GPIO_QSPI_SCLK_OD 44 // Description : Output disable. Has priority over output enable from 45 // peripherals 46 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0) 47 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080) 48 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7) 49 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7) 50 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" 51 // ----------------------------------------------------------------------------- 52 // Field : PADS_QSPI_GPIO_QSPI_SCLK_IE 53 // Description : Input enable 54 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1) 55 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040) 56 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6) 57 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6) 58 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" 59 // ----------------------------------------------------------------------------- 60 // Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE 61 // Description : Drive strength. 62 // 0x0 -> 2mA 63 // 0x1 -> 4mA 64 // 0x2 -> 8mA 65 // 0x3 -> 12mA 66 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) 67 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) 68 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) 69 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) 70 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" 71 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) 72 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) 73 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) 74 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) 75 // ----------------------------------------------------------------------------- 76 // Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE 77 // Description : Pull up enable 78 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0) 79 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008) 80 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3) 81 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3) 82 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" 83 // ----------------------------------------------------------------------------- 84 // Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE 85 // Description : Pull down enable 86 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1) 87 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004) 88 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2) 89 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2) 90 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" 91 // ----------------------------------------------------------------------------- 92 // Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT 93 // Description : Enable schmitt trigger 94 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1) 95 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002) 96 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1) 97 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1) 98 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" 99 // ----------------------------------------------------------------------------- 100 // Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST 101 // Description : Slew rate control. 1 = Fast, 0 = Slow 102 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0) 103 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001) 104 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0) 105 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0) 106 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" 107 // ============================================================================= 108 // Register : PADS_QSPI_GPIO_QSPI_SD0 109 #define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008) 110 #define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000001ff) 111 #define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000156) 112 // ----------------------------------------------------------------------------- 113 // Field : PADS_QSPI_GPIO_QSPI_SD0_ISO 114 // Description : Pad isolation control. Remove this once the pad is configured 115 // by software. 116 #define PADS_QSPI_GPIO_QSPI_SD0_ISO_RESET _u(0x1) 117 #define PADS_QSPI_GPIO_QSPI_SD0_ISO_BITS _u(0x00000100) 118 #define PADS_QSPI_GPIO_QSPI_SD0_ISO_MSB _u(8) 119 #define PADS_QSPI_GPIO_QSPI_SD0_ISO_LSB _u(8) 120 #define PADS_QSPI_GPIO_QSPI_SD0_ISO_ACCESS "RW" 121 // ----------------------------------------------------------------------------- 122 // Field : PADS_QSPI_GPIO_QSPI_SD0_OD 123 // Description : Output disable. Has priority over output enable from 124 // peripherals 125 #define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0) 126 #define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080) 127 #define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7) 128 #define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7) 129 #define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" 130 // ----------------------------------------------------------------------------- 131 // Field : PADS_QSPI_GPIO_QSPI_SD0_IE 132 // Description : Input enable 133 #define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1) 134 #define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040) 135 #define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6) 136 #define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6) 137 #define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" 138 // ----------------------------------------------------------------------------- 139 // Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE 140 // Description : Drive strength. 141 // 0x0 -> 2mA 142 // 0x1 -> 4mA 143 // 0x2 -> 8mA 144 // 0x3 -> 12mA 145 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) 146 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) 147 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) 148 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) 149 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" 150 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) 151 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) 152 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) 153 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) 154 // ----------------------------------------------------------------------------- 155 // Field : PADS_QSPI_GPIO_QSPI_SD0_PUE 156 // Description : Pull up enable 157 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0) 158 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008) 159 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3) 160 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3) 161 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : PADS_QSPI_GPIO_QSPI_SD0_PDE 164 // Description : Pull down enable 165 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x1) 166 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004) 167 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2) 168 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2) 169 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" 170 // ----------------------------------------------------------------------------- 171 // Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT 172 // Description : Enable schmitt trigger 173 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1) 174 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002) 175 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1) 176 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1) 177 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" 178 // ----------------------------------------------------------------------------- 179 // Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST 180 // Description : Slew rate control. 1 = Fast, 0 = Slow 181 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0) 182 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001) 183 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0) 184 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0) 185 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" 186 // ============================================================================= 187 // Register : PADS_QSPI_GPIO_QSPI_SD1 188 #define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c) 189 #define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000001ff) 190 #define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000156) 191 // ----------------------------------------------------------------------------- 192 // Field : PADS_QSPI_GPIO_QSPI_SD1_ISO 193 // Description : Pad isolation control. Remove this once the pad is configured 194 // by software. 195 #define PADS_QSPI_GPIO_QSPI_SD1_ISO_RESET _u(0x1) 196 #define PADS_QSPI_GPIO_QSPI_SD1_ISO_BITS _u(0x00000100) 197 #define PADS_QSPI_GPIO_QSPI_SD1_ISO_MSB _u(8) 198 #define PADS_QSPI_GPIO_QSPI_SD1_ISO_LSB _u(8) 199 #define PADS_QSPI_GPIO_QSPI_SD1_ISO_ACCESS "RW" 200 // ----------------------------------------------------------------------------- 201 // Field : PADS_QSPI_GPIO_QSPI_SD1_OD 202 // Description : Output disable. Has priority over output enable from 203 // peripherals 204 #define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0) 205 #define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080) 206 #define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7) 207 #define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7) 208 #define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" 209 // ----------------------------------------------------------------------------- 210 // Field : PADS_QSPI_GPIO_QSPI_SD1_IE 211 // Description : Input enable 212 #define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1) 213 #define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040) 214 #define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6) 215 #define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6) 216 #define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" 217 // ----------------------------------------------------------------------------- 218 // Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE 219 // Description : Drive strength. 220 // 0x0 -> 2mA 221 // 0x1 -> 4mA 222 // 0x2 -> 8mA 223 // 0x3 -> 12mA 224 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) 225 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) 226 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) 227 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) 228 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" 229 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) 230 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) 231 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) 232 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) 233 // ----------------------------------------------------------------------------- 234 // Field : PADS_QSPI_GPIO_QSPI_SD1_PUE 235 // Description : Pull up enable 236 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0) 237 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008) 238 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3) 239 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3) 240 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" 241 // ----------------------------------------------------------------------------- 242 // Field : PADS_QSPI_GPIO_QSPI_SD1_PDE 243 // Description : Pull down enable 244 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x1) 245 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004) 246 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2) 247 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2) 248 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" 249 // ----------------------------------------------------------------------------- 250 // Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT 251 // Description : Enable schmitt trigger 252 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1) 253 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002) 254 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1) 255 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1) 256 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" 257 // ----------------------------------------------------------------------------- 258 // Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST 259 // Description : Slew rate control. 1 = Fast, 0 = Slow 260 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0) 261 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001) 262 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0) 263 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0) 264 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" 265 // ============================================================================= 266 // Register : PADS_QSPI_GPIO_QSPI_SD2 267 #define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010) 268 #define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000001ff) 269 #define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x0000015a) 270 // ----------------------------------------------------------------------------- 271 // Field : PADS_QSPI_GPIO_QSPI_SD2_ISO 272 // Description : Pad isolation control. Remove this once the pad is configured 273 // by software. 274 #define PADS_QSPI_GPIO_QSPI_SD2_ISO_RESET _u(0x1) 275 #define PADS_QSPI_GPIO_QSPI_SD2_ISO_BITS _u(0x00000100) 276 #define PADS_QSPI_GPIO_QSPI_SD2_ISO_MSB _u(8) 277 #define PADS_QSPI_GPIO_QSPI_SD2_ISO_LSB _u(8) 278 #define PADS_QSPI_GPIO_QSPI_SD2_ISO_ACCESS "RW" 279 // ----------------------------------------------------------------------------- 280 // Field : PADS_QSPI_GPIO_QSPI_SD2_OD 281 // Description : Output disable. Has priority over output enable from 282 // peripherals 283 #define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0) 284 #define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080) 285 #define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7) 286 #define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7) 287 #define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" 288 // ----------------------------------------------------------------------------- 289 // Field : PADS_QSPI_GPIO_QSPI_SD2_IE 290 // Description : Input enable 291 #define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1) 292 #define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040) 293 #define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6) 294 #define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6) 295 #define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" 296 // ----------------------------------------------------------------------------- 297 // Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE 298 // Description : Drive strength. 299 // 0x0 -> 2mA 300 // 0x1 -> 4mA 301 // 0x2 -> 8mA 302 // 0x3 -> 12mA 303 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) 304 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) 305 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) 306 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) 307 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" 308 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) 309 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) 310 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) 311 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) 312 // ----------------------------------------------------------------------------- 313 // Field : PADS_QSPI_GPIO_QSPI_SD2_PUE 314 // Description : Pull up enable 315 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x1) 316 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008) 317 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3) 318 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3) 319 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" 320 // ----------------------------------------------------------------------------- 321 // Field : PADS_QSPI_GPIO_QSPI_SD2_PDE 322 // Description : Pull down enable 323 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0) 324 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004) 325 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2) 326 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2) 327 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" 328 // ----------------------------------------------------------------------------- 329 // Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT 330 // Description : Enable schmitt trigger 331 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1) 332 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002) 333 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1) 334 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1) 335 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" 336 // ----------------------------------------------------------------------------- 337 // Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST 338 // Description : Slew rate control. 1 = Fast, 0 = Slow 339 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0) 340 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001) 341 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0) 342 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0) 343 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" 344 // ============================================================================= 345 // Register : PADS_QSPI_GPIO_QSPI_SD3 346 #define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014) 347 #define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000001ff) 348 #define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x0000015a) 349 // ----------------------------------------------------------------------------- 350 // Field : PADS_QSPI_GPIO_QSPI_SD3_ISO 351 // Description : Pad isolation control. Remove this once the pad is configured 352 // by software. 353 #define PADS_QSPI_GPIO_QSPI_SD3_ISO_RESET _u(0x1) 354 #define PADS_QSPI_GPIO_QSPI_SD3_ISO_BITS _u(0x00000100) 355 #define PADS_QSPI_GPIO_QSPI_SD3_ISO_MSB _u(8) 356 #define PADS_QSPI_GPIO_QSPI_SD3_ISO_LSB _u(8) 357 #define PADS_QSPI_GPIO_QSPI_SD3_ISO_ACCESS "RW" 358 // ----------------------------------------------------------------------------- 359 // Field : PADS_QSPI_GPIO_QSPI_SD3_OD 360 // Description : Output disable. Has priority over output enable from 361 // peripherals 362 #define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0) 363 #define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080) 364 #define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7) 365 #define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7) 366 #define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" 367 // ----------------------------------------------------------------------------- 368 // Field : PADS_QSPI_GPIO_QSPI_SD3_IE 369 // Description : Input enable 370 #define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1) 371 #define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040) 372 #define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6) 373 #define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6) 374 #define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" 375 // ----------------------------------------------------------------------------- 376 // Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE 377 // Description : Drive strength. 378 // 0x0 -> 2mA 379 // 0x1 -> 4mA 380 // 0x2 -> 8mA 381 // 0x3 -> 12mA 382 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) 383 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) 384 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) 385 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) 386 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" 387 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) 388 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) 389 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) 390 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) 391 // ----------------------------------------------------------------------------- 392 // Field : PADS_QSPI_GPIO_QSPI_SD3_PUE 393 // Description : Pull up enable 394 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x1) 395 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008) 396 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3) 397 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3) 398 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" 399 // ----------------------------------------------------------------------------- 400 // Field : PADS_QSPI_GPIO_QSPI_SD3_PDE 401 // Description : Pull down enable 402 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0) 403 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004) 404 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2) 405 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2) 406 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" 407 // ----------------------------------------------------------------------------- 408 // Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT 409 // Description : Enable schmitt trigger 410 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1) 411 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002) 412 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1) 413 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1) 414 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" 415 // ----------------------------------------------------------------------------- 416 // Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST 417 // Description : Slew rate control. 1 = Fast, 0 = Slow 418 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0) 419 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001) 420 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0) 421 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0) 422 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" 423 // ============================================================================= 424 // Register : PADS_QSPI_GPIO_QSPI_SS 425 #define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018) 426 #define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000001ff) 427 #define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000015a) 428 // ----------------------------------------------------------------------------- 429 // Field : PADS_QSPI_GPIO_QSPI_SS_ISO 430 // Description : Pad isolation control. Remove this once the pad is configured 431 // by software. 432 #define PADS_QSPI_GPIO_QSPI_SS_ISO_RESET _u(0x1) 433 #define PADS_QSPI_GPIO_QSPI_SS_ISO_BITS _u(0x00000100) 434 #define PADS_QSPI_GPIO_QSPI_SS_ISO_MSB _u(8) 435 #define PADS_QSPI_GPIO_QSPI_SS_ISO_LSB _u(8) 436 #define PADS_QSPI_GPIO_QSPI_SS_ISO_ACCESS "RW" 437 // ----------------------------------------------------------------------------- 438 // Field : PADS_QSPI_GPIO_QSPI_SS_OD 439 // Description : Output disable. Has priority over output enable from 440 // peripherals 441 #define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0) 442 #define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080) 443 #define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7) 444 #define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7) 445 #define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" 446 // ----------------------------------------------------------------------------- 447 // Field : PADS_QSPI_GPIO_QSPI_SS_IE 448 // Description : Input enable 449 #define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1) 450 #define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040) 451 #define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6) 452 #define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6) 453 #define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" 454 // ----------------------------------------------------------------------------- 455 // Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE 456 // Description : Drive strength. 457 // 0x0 -> 2mA 458 // 0x1 -> 4mA 459 // 0x2 -> 8mA 460 // 0x3 -> 12mA 461 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) 462 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) 463 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) 464 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) 465 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" 466 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) 467 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) 468 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) 469 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) 470 // ----------------------------------------------------------------------------- 471 // Field : PADS_QSPI_GPIO_QSPI_SS_PUE 472 // Description : Pull up enable 473 #define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1) 474 #define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008) 475 #define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3) 476 #define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3) 477 #define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" 478 // ----------------------------------------------------------------------------- 479 // Field : PADS_QSPI_GPIO_QSPI_SS_PDE 480 // Description : Pull down enable 481 #define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0) 482 #define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004) 483 #define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2) 484 #define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2) 485 #define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" 486 // ----------------------------------------------------------------------------- 487 // Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT 488 // Description : Enable schmitt trigger 489 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1) 490 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002) 491 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1) 492 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1) 493 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" 494 // ----------------------------------------------------------------------------- 495 // Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST 496 // Description : Slew rate control. 1 = Fast, 0 = Slow 497 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0) 498 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001) 499 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0) 500 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) 501 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" 502 // ============================================================================= 503 #endif // _HARDWARE_REGS_PADS_QSPI_H 504 505
