1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef _DREQ_H
9 #define _DREQ_H
10 
11 /**
12  * \file rp2350/dreq.h
13  */
14 
15 #ifdef __ASSEMBLER__
16 #define DREQ_PIO0_TX0 0
17 #define DREQ_PIO0_TX1 1
18 #define DREQ_PIO0_TX2 2
19 #define DREQ_PIO0_TX3 3
20 #define DREQ_PIO0_RX0 4
21 #define DREQ_PIO0_RX1 5
22 #define DREQ_PIO0_RX2 6
23 #define DREQ_PIO0_RX3 7
24 #define DREQ_PIO1_TX0 8
25 #define DREQ_PIO1_TX1 9
26 #define DREQ_PIO1_TX2 10
27 #define DREQ_PIO1_TX3 11
28 #define DREQ_PIO1_RX0 12
29 #define DREQ_PIO1_RX1 13
30 #define DREQ_PIO1_RX2 14
31 #define DREQ_PIO1_RX3 15
32 #define DREQ_PIO2_TX0 16
33 #define DREQ_PIO2_TX1 17
34 #define DREQ_PIO2_TX2 18
35 #define DREQ_PIO2_TX3 19
36 #define DREQ_PIO2_RX0 20
37 #define DREQ_PIO2_RX1 21
38 #define DREQ_PIO2_RX2 22
39 #define DREQ_PIO2_RX3 23
40 #define DREQ_SPI0_TX 24
41 #define DREQ_SPI0_RX 25
42 #define DREQ_SPI1_TX 26
43 #define DREQ_SPI1_RX 27
44 #define DREQ_UART0_TX 28
45 #define DREQ_UART0_RX 29
46 #define DREQ_UART1_TX 30
47 #define DREQ_UART1_RX 31
48 #define DREQ_PWM_WRAP0 32
49 #define DREQ_PWM_WRAP1 33
50 #define DREQ_PWM_WRAP2 34
51 #define DREQ_PWM_WRAP3 35
52 #define DREQ_PWM_WRAP4 36
53 #define DREQ_PWM_WRAP5 37
54 #define DREQ_PWM_WRAP6 38
55 #define DREQ_PWM_WRAP7 39
56 #define DREQ_PWM_WRAP8 40
57 #define DREQ_PWM_WRAP9 41
58 #define DREQ_PWM_WRAP10 42
59 #define DREQ_PWM_WRAP11 43
60 #define DREQ_I2C0_TX 44
61 #define DREQ_I2C0_RX 45
62 #define DREQ_I2C1_TX 46
63 #define DREQ_I2C1_RX 47
64 #define DREQ_ADC 48
65 #define DREQ_XIP_STREAM 49
66 #define DREQ_XIP_QMITX 50
67 #define DREQ_XIP_QMIRX 51
68 #define DREQ_HSTX 52
69 #define DREQ_CORESIGHT 53
70 #define DREQ_SHA256 54
71 #define DREQ_DMA_TIMER0 59
72 #define DREQ_DMA_TIMER1 60
73 #define DREQ_DMA_TIMER2 61
74 #define DREQ_DMA_TIMER3 62
75 #define DREQ_FORCE 63
76 #else
77 /**
78  * \brief DREQ numbers for DMA pacing on RP2350 (used as typedef \ref dreq_num_t)
79  * \ingroup hardware_dma
80  */
81 typedef enum dreq_num_rp2350 {
82     DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ
83     DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ
84     DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ
85     DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ
86     DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ
87     DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ
88     DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ
89     DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ
90     DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ
91     DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ
92     DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ
93     DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ
94     DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ
95     DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ
96     DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ
97     DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ
98     DREQ_PIO2_TX0 = 16, ///< Select PIO2's TX FIFO 0 as DREQ
99     DREQ_PIO2_TX1 = 17, ///< Select PIO2's TX FIFO 1 as DREQ
100     DREQ_PIO2_TX2 = 18, ///< Select PIO2's TX FIFO 2 as DREQ
101     DREQ_PIO2_TX3 = 19, ///< Select PIO2's TX FIFO 3 as DREQ
102     DREQ_PIO2_RX0 = 20, ///< Select PIO2's RX FIFO 0 as DREQ
103     DREQ_PIO2_RX1 = 21, ///< Select PIO2's RX FIFO 1 as DREQ
104     DREQ_PIO2_RX2 = 22, ///< Select PIO2's RX FIFO 2 as DREQ
105     DREQ_PIO2_RX3 = 23, ///< Select PIO2's RX FIFO 3 as DREQ
106     DREQ_SPI0_TX = 24, ///< Select SPI0's TX FIFO as DREQ
107     DREQ_SPI0_RX = 25, ///< Select SPI0's RX FIFO as DREQ
108     DREQ_SPI1_TX = 26, ///< Select SPI1's TX FIFO as DREQ
109     DREQ_SPI1_RX = 27, ///< Select SPI1's RX FIFO as DREQ
110     DREQ_UART0_TX = 28, ///< Select UART0's TX FIFO as DREQ
111     DREQ_UART0_RX = 29, ///< Select UART0's RX FIFO as DREQ
112     DREQ_UART1_TX = 30, ///< Select UART1's TX FIFO as DREQ
113     DREQ_UART1_RX = 31, ///< Select UART1's RX FIFO as DREQ
114     DREQ_PWM_WRAP0 = 32, ///< Select PWM Counter 0's Wrap Value as DREQ
115     DREQ_PWM_WRAP1 = 33, ///< Select PWM Counter 1's Wrap Value as DREQ
116     DREQ_PWM_WRAP2 = 34, ///< Select PWM Counter 2's Wrap Value as DREQ
117     DREQ_PWM_WRAP3 = 35, ///< Select PWM Counter 3's Wrap Value as DREQ
118     DREQ_PWM_WRAP4 = 36, ///< Select PWM Counter 4's Wrap Value as DREQ
119     DREQ_PWM_WRAP5 = 37, ///< Select PWM Counter 5's Wrap Value as DREQ
120     DREQ_PWM_WRAP6 = 38, ///< Select PWM Counter 6's Wrap Value as DREQ
121     DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ
122     DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ
123     DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ
124     DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ
125     DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ
126     DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ
127     DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ
128     DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ
129     DREQ_I2C1_RX = 47, ///< Select I2C1's RX FIFO as DREQ
130     DREQ_ADC = 48, ///< Select the ADC as DREQ
131     DREQ_XIP_STREAM = 49, ///< Select the XIP Streaming FIFO as DREQ
132     DREQ_XIP_QMITX = 50, ///< Select XIP_QMITX as DREQ
133     DREQ_XIP_QMIRX = 51, ///< Select XIP_QMIRX as DREQ
134     DREQ_HSTX = 52, ///< Select HSTX as DREQ
135     DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ
136     DREQ_SHA256 = 54, ///< Select SHA256 as DREQ
137     DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
138     DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
139     DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
140     DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
141     DREQ_FORCE = 63, ///< Select FORCE as DREQ
142     DREQ_COUNT
143 } dreq_num_t;
144 #endif
145 
146 #endif // _DREQ_H
147 
148