1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef _HARDWARE_STRUCTS_XIP_H
9 #define _HARDWARE_STRUCTS_XIP_H
10 
11 /**
12  * \file rp2040/xip.h
13  */
14 
15 #include "hardware/address_mapped.h"
16 #include "hardware/regs/xip.h"
17 
18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
19 //
20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21 // _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
22 //
23 // Bit-field descriptions are of the form:
24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25 
26 typedef struct {
27     _REG_(XIP_CTRL_OFFSET) // XIP_CTRL
28     // Cache control
29     // 0x00000008 [3]     POWER_DOWN   (0) When 1, the cache memories are powered down
30     // 0x00000002 [1]     ERR_BADWRITE (1) When 1, writes to any alias other than 0x0 (caching,...
31     // 0x00000001 [0]     EN           (1) When 1, enable the cache
32     io_rw_32 ctrl;
33 
34     _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
35     // Cache Flush control
36     // 0x00000001 [0]     FLUSH        (0) Write 1 to flush the cache
37     io_wo_32 flush;
38 
39     _REG_(XIP_STAT_OFFSET) // XIP_STAT
40     // Cache Status
41     // 0x00000004 [2]     FIFO_FULL    (0) When 1, indicates the XIP streaming FIFO is completely full
42     // 0x00000002 [1]     FIFO_EMPTY   (1) When 1, indicates the XIP streaming FIFO is completely empty
43     // 0x00000001 [0]     FLUSH_READY  (0) Reads as 0 while a cache flush is in progress, and 1 otherwise
44     io_ro_32 stat;
45 
46     _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
47     // Cache Hit counter
48     // 0xffffffff [31:0]  CTR_HIT      (0x00000000) A 32 bit saturating counter that increments upon each...
49     io_rw_32 ctr_hit;
50 
51     _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
52     // Cache Access counter
53     // 0xffffffff [31:0]  CTR_ACC      (0x00000000) A 32 bit saturating counter that increments upon each...
54     io_rw_32 ctr_acc;
55 
56     _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
57     // FIFO stream address
58     // 0xfffffffc [31:2]  STREAM_ADDR  (0x00000000) The address of the next word to be streamed from flash...
59     io_rw_32 stream_addr;
60 
61     _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
62     // FIFO stream control
63     // 0x003fffff [21:0]  STREAM_CTR   (0x000000) Write a nonzero value to start a streaming read
64     io_rw_32 stream_ctr;
65 
66     _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
67     // FIFO stream data
68     // 0xffffffff [31:0]  STREAM_FIFO  (0x00000000) Streamed data is buffered here, for retrieval by the system DMA
69     io_ro_32 stream_fifo;
70 } xip_ctrl_hw_t;
71 
72 #define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE)
73 static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, "");
74 
75 #endif // _HARDWARE_STRUCTS_XIP_H
76 
77