1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_SYSCFG_H 9 #define _HARDWARE_STRUCTS_SYSCFG_H 10 11 /** 12 * \file rp2040/syscfg.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/syscfg.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK 28 // Processor core 0 NMI source mask 29 // 0xffffffff [31:0] PROC0_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ 30 io_rw_32 proc0_nmi_mask; 31 32 _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK 33 // Processor core 1 NMI source mask 34 // 0xffffffff [31:0] PROC1_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ 35 io_rw_32 proc1_nmi_mask; 36 37 _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG 38 // Configuration for processors 39 // 0xf0000000 [31:28] PROC1_DAP_INSTID (0x1) Configure proc1 DAP instance ID 40 // 0x0f000000 [27:24] PROC0_DAP_INSTID (0x0) Configure proc0 DAP instance ID 41 // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted 42 // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted 43 io_rw_32 proc_config; 44 45 _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS 46 // For each bit, if 1, bypass the input synchronizer between that GPIO + 47 // 0x3fffffff [29:0] PROC_IN_SYNC_BYPASS (0x00000000) 48 io_rw_32 proc_in_sync_bypass; 49 50 _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI 51 // For each bit, if 1, bypass the input synchronizer between that GPIO + 52 // 0x0000003f [5:0] PROC_IN_SYNC_BYPASS_HI (0x00) 53 io_rw_32 proc_in_sync_bypass_hi; 54 55 _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE 56 // Directly control the SWD debug port of either processor 57 // 0x00000080 [7] PROC1_ATTACH (0) Attach processor 1 debug port to syscfg controls, and... 58 // 0x00000040 [6] PROC1_SWCLK (1) Directly drive processor 1 SWCLK, if PROC1_ATTACH is set 59 // 0x00000020 [5] PROC1_SWDI (1) Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set 60 // 0x00000010 [4] PROC1_SWDO (-) Observe the value of processor 1 SWDIO output 61 // 0x00000008 [3] PROC0_ATTACH (0) Attach processor 0 debug port to syscfg controls, and... 62 // 0x00000004 [2] PROC0_SWCLK (1) Directly drive processor 0 SWCLK, if PROC0_ATTACH is set 63 // 0x00000002 [1] PROC0_SWDI (1) Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set 64 // 0x00000001 [0] PROC0_SWDO (-) Observe the value of processor 0 SWDIO output 65 io_rw_32 dbgforce; 66 67 _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN 68 // Control power downs to memories 69 // 0x00000080 [7] ROM (0) 70 // 0x00000040 [6] USB (0) 71 // 0x00000020 [5] SRAM5 (0) 72 // 0x00000010 [4] SRAM4 (0) 73 // 0x00000008 [3] SRAM3 (0) 74 // 0x00000004 [2] SRAM2 (0) 75 // 0x00000002 [1] SRAM1 (0) 76 // 0x00000001 [0] SRAM0 (0) 77 io_rw_32 mempowerdown; 78 } syscfg_hw_t; 79 80 #define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) 81 static_assert(sizeof (syscfg_hw_t) == 0x001c, ""); 82 83 #endif // _HARDWARE_STRUCTS_SYSCFG_H 84 85
