1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef _HARDWARE_STRUCTS_RTC_H
9 #define _HARDWARE_STRUCTS_RTC_H
10 
11 /**
12  * \file rp2040/rtc.h
13  */
14 
15 #include "hardware/address_mapped.h"
16 #include "hardware/regs/rtc.h"
17 
18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
19 //
20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21 // _REG_(x) will link to the corresponding register in hardware/regs/rtc.h.
22 //
23 // Bit-field descriptions are of the form:
24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25 
26 typedef struct {
27     _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
28     // Divider minus 1 for the 1 second counter
29     // 0x0000ffff [15:0]  CLKDIV_M1    (0x0000)
30     io_rw_32 clkdiv_m1;
31 
32     _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
33     // RTC setup register 0
34     // 0x00fff000 [23:12] YEAR         (0x000) Year
35     // 0x00000f00 [11:8]  MONTH        (0x0) Month (1
36     // 0x0000001f [4:0]   DAY          (0x00) Day of the month (1
37     io_rw_32 setup_0;
38 
39     _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
40     // RTC setup register 1
41     // 0x07000000 [26:24] DOTW         (0x0) Day of the week: 1-Monday
42     // 0x001f0000 [20:16] HOUR         (0x00) Hours
43     // 0x00003f00 [13:8]  MIN          (0x00) Minutes
44     // 0x0000003f [5:0]   SEC          (0x00) Seconds
45     io_rw_32 setup_1;
46 
47     _REG_(RTC_CTRL_OFFSET) // RTC_CTRL
48     // RTC Control and status
49     // 0x00000100 [8]     FORCE_NOTLEAPYEAR (0) If set, leapyear is forced off
50     // 0x00000010 [4]     LOAD         (0) Load RTC
51     // 0x00000002 [1]     RTC_ACTIVE   (-) RTC enabled (running)
52     // 0x00000001 [0]     RTC_ENABLE   (0) Enable RTC
53     io_rw_32 ctrl;
54 
55     _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
56     // Interrupt setup register 0
57     // 0x20000000 [29]    MATCH_ACTIVE (-)
58     // 0x10000000 [28]    MATCH_ENA    (0) Global match enable
59     // 0x04000000 [26]    YEAR_ENA     (0) Enable year matching
60     // 0x02000000 [25]    MONTH_ENA    (0) Enable month matching
61     // 0x01000000 [24]    DAY_ENA      (0) Enable day matching
62     // 0x00fff000 [23:12] YEAR         (0x000) Year
63     // 0x00000f00 [11:8]  MONTH        (0x0) Month (1
64     // 0x0000001f [4:0]   DAY          (0x00) Day of the month (1
65     io_rw_32 irq_setup_0;
66 
67     _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
68     // Interrupt setup register 1
69     // 0x80000000 [31]    DOTW_ENA     (0) Enable day of the week matching
70     // 0x40000000 [30]    HOUR_ENA     (0) Enable hour matching
71     // 0x20000000 [29]    MIN_ENA      (0) Enable minute matching
72     // 0x10000000 [28]    SEC_ENA      (0) Enable second matching
73     // 0x07000000 [26:24] DOTW         (0x0) Day of the week
74     // 0x001f0000 [20:16] HOUR         (0x00) Hours
75     // 0x00003f00 [13:8]  MIN          (0x00) Minutes
76     // 0x0000003f [5:0]   SEC          (0x00) Seconds
77     io_rw_32 irq_setup_1;
78 
79     _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
80     // RTC register 1
81     // 0x00fff000 [23:12] YEAR         (-) Year
82     // 0x00000f00 [11:8]  MONTH        (-) Month (1
83     // 0x0000001f [4:0]   DAY          (-) Day of the month (1
84     io_ro_32 rtc_1;
85 
86     _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
87     // RTC register 0 +
88     // 0x07000000 [26:24] DOTW         (-) Day of the week
89     // 0x001f0000 [20:16] HOUR         (-) Hours
90     // 0x00003f00 [13:8]  MIN          (-) Minutes
91     // 0x0000003f [5:0]   SEC          (-) Seconds
92     io_ro_32 rtc_0;
93 
94     _REG_(RTC_INTR_OFFSET) // RTC_INTR
95     // Raw Interrupts
96     // 0x00000001 [0]     RTC          (0)
97     io_ro_32 intr;
98 
99     _REG_(RTC_INTE_OFFSET) // RTC_INTE
100     // Interrupt Enable
101     // 0x00000001 [0]     RTC          (0)
102     io_rw_32 inte;
103 
104     _REG_(RTC_INTF_OFFSET) // RTC_INTF
105     // Interrupt Force
106     // 0x00000001 [0]     RTC          (0)
107     io_rw_32 intf;
108 
109     _REG_(RTC_INTS_OFFSET) // RTC_INTS
110     // Interrupt status after masking & forcing
111     // 0x00000001 [0]     RTC          (0)
112     io_ro_32 ints;
113 } rtc_hw_t;
114 
115 #define rtc_hw ((rtc_hw_t *)RTC_BASE)
116 static_assert(sizeof (rtc_hw_t) == 0x0030, "");
117 
118 #endif // _HARDWARE_STRUCTS_RTC_H
119 
120