1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_RESETS_H 9 #define _HARDWARE_STRUCTS_RESETS_H 10 11 /** 12 * \file rp2040/resets.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/resets.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/resets.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 /** \brief Resettable component numbers on RP2040 (used as typedef \ref reset_num_t) 27 * \ingroup hardware_resets 28 */ 29 typedef enum reset_num_rp2040 { 30 RESET_ADC = 0, ///< Select ADC to be reset 31 RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset 32 RESET_DMA = 2, ///< Select DMA to be reset 33 RESET_I2C0 = 3, ///< Select I2C0 to be reset 34 RESET_I2C1 = 4, ///< Select I2C1 to be reset 35 RESET_IO_BANK0 = 5, ///< Select IO_BANK0 to be reset 36 RESET_IO_QSPI = 6, ///< Select IO_QSPI to be reset 37 RESET_JTAG = 7, ///< Select JTAG to be reset 38 RESET_PADS_BANK0 = 8, ///< Select PADS_BANK0 to be reset 39 RESET_PADS_QSPI = 9, ///< Select PADS_QSPI to be reset 40 RESET_PIO0 = 10, ///< Select PIO0 to be reset 41 RESET_PIO1 = 11, ///< Select PIO1 to be reset 42 RESET_PLL_SYS = 12, ///< Select PLL_SYS to be reset 43 RESET_PLL_USB = 13, ///< Select PLL_USB to be reset 44 RESET_PWM = 14, ///< Select PWM to be reset 45 RESET_RTC = 15, ///< Select RTC to be reset 46 RESET_SPI0 = 16, ///< Select SPI0 to be reset 47 RESET_SPI1 = 17, ///< Select SPI1 to be reset 48 RESET_SYSCFG = 18, ///< Select SYSCFG to be reset 49 RESET_SYSINFO = 19, ///< Select SYSINFO to be reset 50 RESET_TBMAN = 20, ///< Select TBMAN to be reset 51 RESET_TIMER = 21, ///< Select TIMER to be reset 52 RESET_UART0 = 22, ///< Select UART0 to be reset 53 RESET_UART1 = 23, ///< Select UART1 to be reset 54 RESET_USBCTRL = 24, ///< Select USBCTRL to be reset 55 RESET_COUNT 56 } reset_num_t; 57 58 /// \tag::resets_hw[] 59 typedef struct { 60 _REG_(RESETS_RESET_OFFSET) // RESETS_RESET 61 // Reset control. 62 // 0x01000000 [24] USBCTRL (1) 63 // 0x00800000 [23] UART1 (1) 64 // 0x00400000 [22] UART0 (1) 65 // 0x00200000 [21] TIMER (1) 66 // 0x00100000 [20] TBMAN (1) 67 // 0x00080000 [19] SYSINFO (1) 68 // 0x00040000 [18] SYSCFG (1) 69 // 0x00020000 [17] SPI1 (1) 70 // 0x00010000 [16] SPI0 (1) 71 // 0x00008000 [15] RTC (1) 72 // 0x00004000 [14] PWM (1) 73 // 0x00002000 [13] PLL_USB (1) 74 // 0x00001000 [12] PLL_SYS (1) 75 // 0x00000800 [11] PIO1 (1) 76 // 0x00000400 [10] PIO0 (1) 77 // 0x00000200 [9] PADS_QSPI (1) 78 // 0x00000100 [8] PADS_BANK0 (1) 79 // 0x00000080 [7] JTAG (1) 80 // 0x00000040 [6] IO_QSPI (1) 81 // 0x00000020 [5] IO_BANK0 (1) 82 // 0x00000010 [4] I2C1 (1) 83 // 0x00000008 [3] I2C0 (1) 84 // 0x00000004 [2] DMA (1) 85 // 0x00000002 [1] BUSCTRL (1) 86 // 0x00000001 [0] ADC (1) 87 io_rw_32 reset; 88 89 _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL 90 // Watchdog select. 91 // 0x01000000 [24] USBCTRL (0) 92 // 0x00800000 [23] UART1 (0) 93 // 0x00400000 [22] UART0 (0) 94 // 0x00200000 [21] TIMER (0) 95 // 0x00100000 [20] TBMAN (0) 96 // 0x00080000 [19] SYSINFO (0) 97 // 0x00040000 [18] SYSCFG (0) 98 // 0x00020000 [17] SPI1 (0) 99 // 0x00010000 [16] SPI0 (0) 100 // 0x00008000 [15] RTC (0) 101 // 0x00004000 [14] PWM (0) 102 // 0x00002000 [13] PLL_USB (0) 103 // 0x00001000 [12] PLL_SYS (0) 104 // 0x00000800 [11] PIO1 (0) 105 // 0x00000400 [10] PIO0 (0) 106 // 0x00000200 [9] PADS_QSPI (0) 107 // 0x00000100 [8] PADS_BANK0 (0) 108 // 0x00000080 [7] JTAG (0) 109 // 0x00000040 [6] IO_QSPI (0) 110 // 0x00000020 [5] IO_BANK0 (0) 111 // 0x00000010 [4] I2C1 (0) 112 // 0x00000008 [3] I2C0 (0) 113 // 0x00000004 [2] DMA (0) 114 // 0x00000002 [1] BUSCTRL (0) 115 // 0x00000001 [0] ADC (0) 116 io_rw_32 wdsel; 117 118 _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE 119 // Reset done. 120 // 0x01000000 [24] USBCTRL (0) 121 // 0x00800000 [23] UART1 (0) 122 // 0x00400000 [22] UART0 (0) 123 // 0x00200000 [21] TIMER (0) 124 // 0x00100000 [20] TBMAN (0) 125 // 0x00080000 [19] SYSINFO (0) 126 // 0x00040000 [18] SYSCFG (0) 127 // 0x00020000 [17] SPI1 (0) 128 // 0x00010000 [16] SPI0 (0) 129 // 0x00008000 [15] RTC (0) 130 // 0x00004000 [14] PWM (0) 131 // 0x00002000 [13] PLL_USB (0) 132 // 0x00001000 [12] PLL_SYS (0) 133 // 0x00000800 [11] PIO1 (0) 134 // 0x00000400 [10] PIO0 (0) 135 // 0x00000200 [9] PADS_QSPI (0) 136 // 0x00000100 [8] PADS_BANK0 (0) 137 // 0x00000080 [7] JTAG (0) 138 // 0x00000040 [6] IO_QSPI (0) 139 // 0x00000020 [5] IO_BANK0 (0) 140 // 0x00000010 [4] I2C1 (0) 141 // 0x00000008 [3] I2C0 (0) 142 // 0x00000004 [2] DMA (0) 143 // 0x00000002 [1] BUSCTRL (0) 144 // 0x00000001 [0] ADC (0) 145 io_ro_32 reset_done; 146 } resets_hw_t; 147 /// \end::resets_hw[] 148 149 #define resets_hw ((resets_hw_t *)RESETS_BASE) 150 static_assert(sizeof (resets_hw_t) == 0x000c, ""); 151 152 #endif // _HARDWARE_STRUCTS_RESETS_H 153 154
