1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef _HARDWARE_STRUCTS_IO_QSPI_H
9 #define _HARDWARE_STRUCTS_IO_QSPI_H
10 
11 /**
12  * \file rp2040/io_qspi.h
13  */
14 
15 #include "hardware/address_mapped.h"
16 #include "hardware/regs/io_qspi.h"
17 
18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
19 //
20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21 // _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
22 //
23 // Bit-field descriptions are of the form:
24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25 
26 /**
27  * \brief QSPI pin function selectors on RP2040 (used as typedef \ref gpio_function1_t)
28  */
29 typedef enum gpio_function1_rp2040 {
30     GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function
31     GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function
32     GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function
33 } gpio_function1_t;
34 
35 typedef struct {
36     _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
37     // GPIO status
38     // 0x04000000 [26]    IRQTOPROC    (0) interrupt to processors, after override is applied
39     // 0x01000000 [24]    IRQFROMPAD   (0) interrupt from pad before override is applied
40     // 0x00080000 [19]    INTOPERI     (0) input signal to peripheral, after override is applied
41     // 0x00020000 [17]    INFROMPAD    (0) input signal from pad, before override is applied
42     // 0x00002000 [13]    OETOPAD      (0) output enable to pad after register override is applied
43     // 0x00001000 [12]    OEFROMPERI   (0) output enable from selected peripheral, before register...
44     // 0x00000200 [9]     OUTTOPAD     (0) output signal to pad after register override is applied
45     // 0x00000100 [8]     OUTFROMPERI  (0) output signal from selected peripheral, before register...
46     io_ro_32 status;
47 
48     _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
49     // GPIO control including function select and overrides
50     // 0x30000000 [29:28] IRQOVER      (0x0)
51     // 0x00030000 [17:16] INOVER       (0x0)
52     // 0x00003000 [13:12] OEOVER       (0x0)
53     // 0x00000300 [9:8]   OUTOVER      (0x0)
54     // 0x0000001f [4:0]   FUNCSEL      (0x1f) 0-31 -> selects pin function according to the gpio table +
55     io_rw_32 ctrl;
56 } io_qspi_status_ctrl_hw_t;
57 
58 typedef struct {
59     _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
60     // Interrupt Enable for proc0
61     // 0x00800000 [23]    GPIO_QSPI_SD3_EDGE_HIGH (0)
62     // 0x00400000 [22]    GPIO_QSPI_SD3_EDGE_LOW (0)
63     // 0x00200000 [21]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
64     // 0x00100000 [20]    GPIO_QSPI_SD3_LEVEL_LOW (0)
65     // 0x00080000 [19]    GPIO_QSPI_SD2_EDGE_HIGH (0)
66     // 0x00040000 [18]    GPIO_QSPI_SD2_EDGE_LOW (0)
67     // 0x00020000 [17]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
68     // 0x00010000 [16]    GPIO_QSPI_SD2_LEVEL_LOW (0)
69     // 0x00008000 [15]    GPIO_QSPI_SD1_EDGE_HIGH (0)
70     // 0x00004000 [14]    GPIO_QSPI_SD1_EDGE_LOW (0)
71     // 0x00002000 [13]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
72     // 0x00001000 [12]    GPIO_QSPI_SD1_LEVEL_LOW (0)
73     // 0x00000800 [11]    GPIO_QSPI_SD0_EDGE_HIGH (0)
74     // 0x00000400 [10]    GPIO_QSPI_SD0_EDGE_LOW (0)
75     // 0x00000200 [9]     GPIO_QSPI_SD0_LEVEL_HIGH (0)
76     // 0x00000100 [8]     GPIO_QSPI_SD0_LEVEL_LOW (0)
77     // 0x00000080 [7]     GPIO_QSPI_SS_EDGE_HIGH (0)
78     // 0x00000040 [6]     GPIO_QSPI_SS_EDGE_LOW (0)
79     // 0x00000020 [5]     GPIO_QSPI_SS_LEVEL_HIGH (0)
80     // 0x00000010 [4]     GPIO_QSPI_SS_LEVEL_LOW (0)
81     // 0x00000008 [3]     GPIO_QSPI_SCLK_EDGE_HIGH (0)
82     // 0x00000004 [2]     GPIO_QSPI_SCLK_EDGE_LOW (0)
83     // 0x00000002 [1]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
84     // 0x00000001 [0]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
85     io_rw_32 inte;
86 
87     _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
88     // Interrupt Force for proc0
89     // 0x00800000 [23]    GPIO_QSPI_SD3_EDGE_HIGH (0)
90     // 0x00400000 [22]    GPIO_QSPI_SD3_EDGE_LOW (0)
91     // 0x00200000 [21]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
92     // 0x00100000 [20]    GPIO_QSPI_SD3_LEVEL_LOW (0)
93     // 0x00080000 [19]    GPIO_QSPI_SD2_EDGE_HIGH (0)
94     // 0x00040000 [18]    GPIO_QSPI_SD2_EDGE_LOW (0)
95     // 0x00020000 [17]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
96     // 0x00010000 [16]    GPIO_QSPI_SD2_LEVEL_LOW (0)
97     // 0x00008000 [15]    GPIO_QSPI_SD1_EDGE_HIGH (0)
98     // 0x00004000 [14]    GPIO_QSPI_SD1_EDGE_LOW (0)
99     // 0x00002000 [13]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
100     // 0x00001000 [12]    GPIO_QSPI_SD1_LEVEL_LOW (0)
101     // 0x00000800 [11]    GPIO_QSPI_SD0_EDGE_HIGH (0)
102     // 0x00000400 [10]    GPIO_QSPI_SD0_EDGE_LOW (0)
103     // 0x00000200 [9]     GPIO_QSPI_SD0_LEVEL_HIGH (0)
104     // 0x00000100 [8]     GPIO_QSPI_SD0_LEVEL_LOW (0)
105     // 0x00000080 [7]     GPIO_QSPI_SS_EDGE_HIGH (0)
106     // 0x00000040 [6]     GPIO_QSPI_SS_EDGE_LOW (0)
107     // 0x00000020 [5]     GPIO_QSPI_SS_LEVEL_HIGH (0)
108     // 0x00000010 [4]     GPIO_QSPI_SS_LEVEL_LOW (0)
109     // 0x00000008 [3]     GPIO_QSPI_SCLK_EDGE_HIGH (0)
110     // 0x00000004 [2]     GPIO_QSPI_SCLK_EDGE_LOW (0)
111     // 0x00000002 [1]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
112     // 0x00000001 [0]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
113     io_rw_32 intf;
114 
115     _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
116     // Interrupt status after masking & forcing for proc0
117     // 0x00800000 [23]    GPIO_QSPI_SD3_EDGE_HIGH (0)
118     // 0x00400000 [22]    GPIO_QSPI_SD3_EDGE_LOW (0)
119     // 0x00200000 [21]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
120     // 0x00100000 [20]    GPIO_QSPI_SD3_LEVEL_LOW (0)
121     // 0x00080000 [19]    GPIO_QSPI_SD2_EDGE_HIGH (0)
122     // 0x00040000 [18]    GPIO_QSPI_SD2_EDGE_LOW (0)
123     // 0x00020000 [17]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
124     // 0x00010000 [16]    GPIO_QSPI_SD2_LEVEL_LOW (0)
125     // 0x00008000 [15]    GPIO_QSPI_SD1_EDGE_HIGH (0)
126     // 0x00004000 [14]    GPIO_QSPI_SD1_EDGE_LOW (0)
127     // 0x00002000 [13]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
128     // 0x00001000 [12]    GPIO_QSPI_SD1_LEVEL_LOW (0)
129     // 0x00000800 [11]    GPIO_QSPI_SD0_EDGE_HIGH (0)
130     // 0x00000400 [10]    GPIO_QSPI_SD0_EDGE_LOW (0)
131     // 0x00000200 [9]     GPIO_QSPI_SD0_LEVEL_HIGH (0)
132     // 0x00000100 [8]     GPIO_QSPI_SD0_LEVEL_LOW (0)
133     // 0x00000080 [7]     GPIO_QSPI_SS_EDGE_HIGH (0)
134     // 0x00000040 [6]     GPIO_QSPI_SS_EDGE_LOW (0)
135     // 0x00000020 [5]     GPIO_QSPI_SS_LEVEL_HIGH (0)
136     // 0x00000010 [4]     GPIO_QSPI_SS_LEVEL_LOW (0)
137     // 0x00000008 [3]     GPIO_QSPI_SCLK_EDGE_HIGH (0)
138     // 0x00000004 [2]     GPIO_QSPI_SCLK_EDGE_LOW (0)
139     // 0x00000002 [1]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
140     // 0x00000001 [0]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
141     io_ro_32 ints;
142 } io_qspi_irq_ctrl_hw_t;
143 
144 typedef struct {
145     io_qspi_status_ctrl_hw_t io[6];
146 
147     _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
148     // Raw Interrupts
149     // 0x00800000 [23]    GPIO_QSPI_SD3_EDGE_HIGH (0)
150     // 0x00400000 [22]    GPIO_QSPI_SD3_EDGE_LOW (0)
151     // 0x00200000 [21]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
152     // 0x00100000 [20]    GPIO_QSPI_SD3_LEVEL_LOW (0)
153     // 0x00080000 [19]    GPIO_QSPI_SD2_EDGE_HIGH (0)
154     // 0x00040000 [18]    GPIO_QSPI_SD2_EDGE_LOW (0)
155     // 0x00020000 [17]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
156     // 0x00010000 [16]    GPIO_QSPI_SD2_LEVEL_LOW (0)
157     // 0x00008000 [15]    GPIO_QSPI_SD1_EDGE_HIGH (0)
158     // 0x00004000 [14]    GPIO_QSPI_SD1_EDGE_LOW (0)
159     // 0x00002000 [13]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
160     // 0x00001000 [12]    GPIO_QSPI_SD1_LEVEL_LOW (0)
161     // 0x00000800 [11]    GPIO_QSPI_SD0_EDGE_HIGH (0)
162     // 0x00000400 [10]    GPIO_QSPI_SD0_EDGE_LOW (0)
163     // 0x00000200 [9]     GPIO_QSPI_SD0_LEVEL_HIGH (0)
164     // 0x00000100 [8]     GPIO_QSPI_SD0_LEVEL_LOW (0)
165     // 0x00000080 [7]     GPIO_QSPI_SS_EDGE_HIGH (0)
166     // 0x00000040 [6]     GPIO_QSPI_SS_EDGE_LOW (0)
167     // 0x00000020 [5]     GPIO_QSPI_SS_LEVEL_HIGH (0)
168     // 0x00000010 [4]     GPIO_QSPI_SS_LEVEL_LOW (0)
169     // 0x00000008 [3]     GPIO_QSPI_SCLK_EDGE_HIGH (0)
170     // 0x00000004 [2]     GPIO_QSPI_SCLK_EDGE_LOW (0)
171     // 0x00000002 [1]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
172     // 0x00000001 [0]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
173     io_rw_32 intr;
174 
175     union {
176         struct {
177             io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
178             io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
179             io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
180         };
181         io_qspi_irq_ctrl_hw_t irq_ctrl[3];
182     };
183 } io_qspi_hw_t;
184 
185 #define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
186 static_assert(sizeof (io_qspi_hw_t) == 0x0058, "");
187 
188 #endif // _HARDWARE_STRUCTS_IO_QSPI_H
189 
190