1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : XOSC
10 // Version        : 1
11 // Bus type       : apb
12 // Description    : Controls the crystal oscillator
13 // =============================================================================
14 #ifndef _HARDWARE_REGS_XOSC_H
15 #define _HARDWARE_REGS_XOSC_H
16 // =============================================================================
17 // Register    : XOSC_CTRL
18 // Description : Crystal Oscillator Control
19 #define XOSC_CTRL_OFFSET _u(0x00000000)
20 #define XOSC_CTRL_BITS   _u(0x00ffffff)
21 #define XOSC_CTRL_RESET  _u(0x00000000)
22 // -----------------------------------------------------------------------------
23 // Field       : XOSC_CTRL_ENABLE
24 // Description : On power-up this field is initialised to DISABLE and the chip
25 //               runs from the ROSC.
26 //               If the chip has subsequently been programmed to run from the
27 //               XOSC then DISABLE may lock-up the chip. If this is a concern
28 //               then run the clk_ref from the ROSC and enable the clk_sys RESUS
29 //               feature.
30 //               The 12-bit code is intended to give some protection against
31 //               accidental writes. An invalid setting will enable the
32 //               oscillator.
33 //               0xd1e -> DISABLE
34 //               0xfab -> ENABLE
35 #define XOSC_CTRL_ENABLE_RESET  "-"
36 #define XOSC_CTRL_ENABLE_BITS   _u(0x00fff000)
37 #define XOSC_CTRL_ENABLE_MSB    _u(23)
38 #define XOSC_CTRL_ENABLE_LSB    _u(12)
39 #define XOSC_CTRL_ENABLE_ACCESS "RW"
40 #define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
41 #define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
42 // -----------------------------------------------------------------------------
43 // Field       : XOSC_CTRL_FREQ_RANGE
44 // Description : Frequency range. An invalid setting will retain the previous
45 //               value. The actual value being used can be read from
46 //               STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed.
47 //               0xaa0 -> 1_15MHZ
48 //               0xaa1 -> RESERVED_1
49 //               0xaa2 -> RESERVED_2
50 //               0xaa3 -> RESERVED_3
51 #define XOSC_CTRL_FREQ_RANGE_RESET  "-"
52 #define XOSC_CTRL_FREQ_RANGE_BITS   _u(0x00000fff)
53 #define XOSC_CTRL_FREQ_RANGE_MSB    _u(11)
54 #define XOSC_CTRL_FREQ_RANGE_LSB    _u(0)
55 #define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
56 #define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
57 #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1)
58 #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2)
59 #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3)
60 // =============================================================================
61 // Register    : XOSC_STATUS
62 // Description : Crystal Oscillator Status
63 #define XOSC_STATUS_OFFSET _u(0x00000004)
64 #define XOSC_STATUS_BITS   _u(0x81001003)
65 #define XOSC_STATUS_RESET  _u(0x00000000)
66 // -----------------------------------------------------------------------------
67 // Field       : XOSC_STATUS_STABLE
68 // Description : Oscillator is running and stable
69 #define XOSC_STATUS_STABLE_RESET  _u(0x0)
70 #define XOSC_STATUS_STABLE_BITS   _u(0x80000000)
71 #define XOSC_STATUS_STABLE_MSB    _u(31)
72 #define XOSC_STATUS_STABLE_LSB    _u(31)
73 #define XOSC_STATUS_STABLE_ACCESS "RO"
74 // -----------------------------------------------------------------------------
75 // Field       : XOSC_STATUS_BADWRITE
76 // Description : An invalid value has been written to CTRL_ENABLE or
77 //               CTRL_FREQ_RANGE or DORMANT
78 #define XOSC_STATUS_BADWRITE_RESET  _u(0x0)
79 #define XOSC_STATUS_BADWRITE_BITS   _u(0x01000000)
80 #define XOSC_STATUS_BADWRITE_MSB    _u(24)
81 #define XOSC_STATUS_BADWRITE_LSB    _u(24)
82 #define XOSC_STATUS_BADWRITE_ACCESS "WC"
83 // -----------------------------------------------------------------------------
84 // Field       : XOSC_STATUS_ENABLED
85 // Description : Oscillator is enabled but not necessarily running and stable,
86 //               resets to 0
87 #define XOSC_STATUS_ENABLED_RESET  "-"
88 #define XOSC_STATUS_ENABLED_BITS   _u(0x00001000)
89 #define XOSC_STATUS_ENABLED_MSB    _u(12)
90 #define XOSC_STATUS_ENABLED_LSB    _u(12)
91 #define XOSC_STATUS_ENABLED_ACCESS "RO"
92 // -----------------------------------------------------------------------------
93 // Field       : XOSC_STATUS_FREQ_RANGE
94 // Description : The current frequency range setting, always reads 0
95 //               0x0 -> 1_15MHZ
96 //               0x1 -> RESERVED_1
97 //               0x2 -> RESERVED_2
98 //               0x3 -> RESERVED_3
99 #define XOSC_STATUS_FREQ_RANGE_RESET  "-"
100 #define XOSC_STATUS_FREQ_RANGE_BITS   _u(0x00000003)
101 #define XOSC_STATUS_FREQ_RANGE_MSB    _u(1)
102 #define XOSC_STATUS_FREQ_RANGE_LSB    _u(0)
103 #define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
104 #define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
105 #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1)
106 #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2)
107 #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3)
108 // =============================================================================
109 // Register    : XOSC_DORMANT
110 // Description : Crystal Oscillator pause control
111 //               This is used to save power by pausing the XOSC
112 //               On power-up this field is initialised to WAKE
113 //               An invalid write will also select WAKE
114 //               Warning: stop the PLLs before selecting dormant mode
115 //               Warning: setup the irq before selecting dormant mode
116 //               0x636f6d61 -> dormant
117 //               0x77616b65 -> WAKE
118 #define XOSC_DORMANT_OFFSET _u(0x00000008)
119 #define XOSC_DORMANT_BITS   _u(0xffffffff)
120 #define XOSC_DORMANT_RESET  "-"
121 #define XOSC_DORMANT_MSB    _u(31)
122 #define XOSC_DORMANT_LSB    _u(0)
123 #define XOSC_DORMANT_ACCESS "RW"
124 #define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
125 #define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
126 // =============================================================================
127 // Register    : XOSC_STARTUP
128 // Description : Controls the startup delay
129 #define XOSC_STARTUP_OFFSET _u(0x0000000c)
130 #define XOSC_STARTUP_BITS   _u(0x00103fff)
131 #define XOSC_STARTUP_RESET  _u(0x00000000)
132 // -----------------------------------------------------------------------------
133 // Field       : XOSC_STARTUP_X4
134 // Description : Multiplies the startup_delay by 4. This is of little value to
135 //               the user given that the delay can be programmed directly.
136 #define XOSC_STARTUP_X4_RESET  "-"
137 #define XOSC_STARTUP_X4_BITS   _u(0x00100000)
138 #define XOSC_STARTUP_X4_MSB    _u(20)
139 #define XOSC_STARTUP_X4_LSB    _u(20)
140 #define XOSC_STARTUP_X4_ACCESS "RW"
141 // -----------------------------------------------------------------------------
142 // Field       : XOSC_STARTUP_DELAY
143 // Description : in multiples of 256*xtal_period. The reset value of 0xc4
144 //               corresponds to approx 50 000 cycles.
145 #define XOSC_STARTUP_DELAY_RESET  "-"
146 #define XOSC_STARTUP_DELAY_BITS   _u(0x00003fff)
147 #define XOSC_STARTUP_DELAY_MSB    _u(13)
148 #define XOSC_STARTUP_DELAY_LSB    _u(0)
149 #define XOSC_STARTUP_DELAY_ACCESS "RW"
150 // =============================================================================
151 // Register    : XOSC_COUNT
152 // Description : A down counter running at the xosc frequency which counts to
153 //               zero and stops.
154 //               To start the counter write a non-zero value.
155 //               Can be used for short software pauses when setting up time
156 //               sensitive hardware.
157 #define XOSC_COUNT_OFFSET _u(0x0000001c)
158 #define XOSC_COUNT_BITS   _u(0x000000ff)
159 #define XOSC_COUNT_RESET  _u(0x00000000)
160 #define XOSC_COUNT_MSB    _u(7)
161 #define XOSC_COUNT_LSB    _u(0)
162 #define XOSC_COUNT_ACCESS "RW"
163 // =============================================================================
164 #endif // _HARDWARE_REGS_XOSC_H
165 
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