1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : TIMER
10 // Version        : 1
11 // Bus type       : apb
12 // Description    : Controls time and alarms
13 //                  time is a 64 bit value indicating the time in usec since
14 //                  power-on
15 //                  timeh is the top 32 bits of time & timel is the bottom 32
16 //                  bits
17 //                  to change time write to timelw before timehw
18 //                  to read time read from timelr before timehr
19 //                  An alarm is set by setting alarm_enable and writing to the
20 //                  corresponding alarm register
21 //                  When an alarm is pending, the corresponding alarm_running
22 //                  signal will be high
23 //                  An alarm can be cancelled before it has finished by clearing
24 //                  the alarm_enable
25 //                  When an alarm fires, the corresponding alarm_irq is set and
26 //                  alarm_running is cleared
27 //                  To clear the interrupt write a 1 to the corresponding
28 //                  alarm_irq
29 // =============================================================================
30 #ifndef _HARDWARE_REGS_TIMER_H
31 #define _HARDWARE_REGS_TIMER_H
32 // =============================================================================
33 // Register    : TIMER_TIMEHW
34 // Description : Write to bits 63:32 of time
35 //               always write timelw before timehw
36 #define TIMER_TIMEHW_OFFSET _u(0x00000000)
37 #define TIMER_TIMEHW_BITS   _u(0xffffffff)
38 #define TIMER_TIMEHW_RESET  _u(0x00000000)
39 #define TIMER_TIMEHW_MSB    _u(31)
40 #define TIMER_TIMEHW_LSB    _u(0)
41 #define TIMER_TIMEHW_ACCESS "WF"
42 // =============================================================================
43 // Register    : TIMER_TIMELW
44 // Description : Write to bits 31:0 of time
45 //               writes do not get copied to time until timehw is written
46 #define TIMER_TIMELW_OFFSET _u(0x00000004)
47 #define TIMER_TIMELW_BITS   _u(0xffffffff)
48 #define TIMER_TIMELW_RESET  _u(0x00000000)
49 #define TIMER_TIMELW_MSB    _u(31)
50 #define TIMER_TIMELW_LSB    _u(0)
51 #define TIMER_TIMELW_ACCESS "WF"
52 // =============================================================================
53 // Register    : TIMER_TIMEHR
54 // Description : Read from bits 63:32 of time
55 //               always read timelr before timehr
56 #define TIMER_TIMEHR_OFFSET _u(0x00000008)
57 #define TIMER_TIMEHR_BITS   _u(0xffffffff)
58 #define TIMER_TIMEHR_RESET  _u(0x00000000)
59 #define TIMER_TIMEHR_MSB    _u(31)
60 #define TIMER_TIMEHR_LSB    _u(0)
61 #define TIMER_TIMEHR_ACCESS "RO"
62 // =============================================================================
63 // Register    : TIMER_TIMELR
64 // Description : Read from bits 31:0 of time
65 #define TIMER_TIMELR_OFFSET _u(0x0000000c)
66 #define TIMER_TIMELR_BITS   _u(0xffffffff)
67 #define TIMER_TIMELR_RESET  _u(0x00000000)
68 #define TIMER_TIMELR_MSB    _u(31)
69 #define TIMER_TIMELR_LSB    _u(0)
70 #define TIMER_TIMELR_ACCESS "RO"
71 // =============================================================================
72 // Register    : TIMER_ALARM0
73 // Description : Arm alarm 0, and configure the time it will fire.
74 //               Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
75 //               The alarm will disarm itself once it fires, and can
76 //               be disarmed early using the ARMED status register.
77 #define TIMER_ALARM0_OFFSET _u(0x00000010)
78 #define TIMER_ALARM0_BITS   _u(0xffffffff)
79 #define TIMER_ALARM0_RESET  _u(0x00000000)
80 #define TIMER_ALARM0_MSB    _u(31)
81 #define TIMER_ALARM0_LSB    _u(0)
82 #define TIMER_ALARM0_ACCESS "RW"
83 // =============================================================================
84 // Register    : TIMER_ALARM1
85 // Description : Arm alarm 1, and configure the time it will fire.
86 //               Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
87 //               The alarm will disarm itself once it fires, and can
88 //               be disarmed early using the ARMED status register.
89 #define TIMER_ALARM1_OFFSET _u(0x00000014)
90 #define TIMER_ALARM1_BITS   _u(0xffffffff)
91 #define TIMER_ALARM1_RESET  _u(0x00000000)
92 #define TIMER_ALARM1_MSB    _u(31)
93 #define TIMER_ALARM1_LSB    _u(0)
94 #define TIMER_ALARM1_ACCESS "RW"
95 // =============================================================================
96 // Register    : TIMER_ALARM2
97 // Description : Arm alarm 2, and configure the time it will fire.
98 //               Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
99 //               The alarm will disarm itself once it fires, and can
100 //               be disarmed early using the ARMED status register.
101 #define TIMER_ALARM2_OFFSET _u(0x00000018)
102 #define TIMER_ALARM2_BITS   _u(0xffffffff)
103 #define TIMER_ALARM2_RESET  _u(0x00000000)
104 #define TIMER_ALARM2_MSB    _u(31)
105 #define TIMER_ALARM2_LSB    _u(0)
106 #define TIMER_ALARM2_ACCESS "RW"
107 // =============================================================================
108 // Register    : TIMER_ALARM3
109 // Description : Arm alarm 3, and configure the time it will fire.
110 //               Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
111 //               The alarm will disarm itself once it fires, and can
112 //               be disarmed early using the ARMED status register.
113 #define TIMER_ALARM3_OFFSET _u(0x0000001c)
114 #define TIMER_ALARM3_BITS   _u(0xffffffff)
115 #define TIMER_ALARM3_RESET  _u(0x00000000)
116 #define TIMER_ALARM3_MSB    _u(31)
117 #define TIMER_ALARM3_LSB    _u(0)
118 #define TIMER_ALARM3_ACCESS "RW"
119 // =============================================================================
120 // Register    : TIMER_ARMED
121 // Description : Indicates the armed/disarmed status of each alarm.
122 //               A write to the corresponding ALARMx register arms the alarm.
123 //               Alarms automatically disarm upon firing, but writing ones here
124 //               will disarm immediately without waiting to fire.
125 #define TIMER_ARMED_OFFSET _u(0x00000020)
126 #define TIMER_ARMED_BITS   _u(0x0000000f)
127 #define TIMER_ARMED_RESET  _u(0x00000000)
128 #define TIMER_ARMED_MSB    _u(3)
129 #define TIMER_ARMED_LSB    _u(0)
130 #define TIMER_ARMED_ACCESS "WC"
131 // =============================================================================
132 // Register    : TIMER_TIMERAWH
133 // Description : Raw read from bits 63:32 of time (no side effects)
134 #define TIMER_TIMERAWH_OFFSET _u(0x00000024)
135 #define TIMER_TIMERAWH_BITS   _u(0xffffffff)
136 #define TIMER_TIMERAWH_RESET  _u(0x00000000)
137 #define TIMER_TIMERAWH_MSB    _u(31)
138 #define TIMER_TIMERAWH_LSB    _u(0)
139 #define TIMER_TIMERAWH_ACCESS "RO"
140 // =============================================================================
141 // Register    : TIMER_TIMERAWL
142 // Description : Raw read from bits 31:0 of time (no side effects)
143 #define TIMER_TIMERAWL_OFFSET _u(0x00000028)
144 #define TIMER_TIMERAWL_BITS   _u(0xffffffff)
145 #define TIMER_TIMERAWL_RESET  _u(0x00000000)
146 #define TIMER_TIMERAWL_MSB    _u(31)
147 #define TIMER_TIMERAWL_LSB    _u(0)
148 #define TIMER_TIMERAWL_ACCESS "RO"
149 // =============================================================================
150 // Register    : TIMER_DBGPAUSE
151 // Description : Set bits high to enable pause when the corresponding debug
152 //               ports are active
153 #define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
154 #define TIMER_DBGPAUSE_BITS   _u(0x00000006)
155 #define TIMER_DBGPAUSE_RESET  _u(0x00000007)
156 // -----------------------------------------------------------------------------
157 // Field       : TIMER_DBGPAUSE_DBG1
158 // Description : Pause when processor 1 is in debug mode
159 #define TIMER_DBGPAUSE_DBG1_RESET  _u(0x1)
160 #define TIMER_DBGPAUSE_DBG1_BITS   _u(0x00000004)
161 #define TIMER_DBGPAUSE_DBG1_MSB    _u(2)
162 #define TIMER_DBGPAUSE_DBG1_LSB    _u(2)
163 #define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
164 // -----------------------------------------------------------------------------
165 // Field       : TIMER_DBGPAUSE_DBG0
166 // Description : Pause when processor 0 is in debug mode
167 #define TIMER_DBGPAUSE_DBG0_RESET  _u(0x1)
168 #define TIMER_DBGPAUSE_DBG0_BITS   _u(0x00000002)
169 #define TIMER_DBGPAUSE_DBG0_MSB    _u(1)
170 #define TIMER_DBGPAUSE_DBG0_LSB    _u(1)
171 #define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
172 // =============================================================================
173 // Register    : TIMER_PAUSE
174 // Description : Set high to pause the timer
175 #define TIMER_PAUSE_OFFSET _u(0x00000030)
176 #define TIMER_PAUSE_BITS   _u(0x00000001)
177 #define TIMER_PAUSE_RESET  _u(0x00000000)
178 #define TIMER_PAUSE_MSB    _u(0)
179 #define TIMER_PAUSE_LSB    _u(0)
180 #define TIMER_PAUSE_ACCESS "RW"
181 // =============================================================================
182 // Register    : TIMER_INTR
183 // Description : Raw Interrupts
184 #define TIMER_INTR_OFFSET _u(0x00000034)
185 #define TIMER_INTR_BITS   _u(0x0000000f)
186 #define TIMER_INTR_RESET  _u(0x00000000)
187 // -----------------------------------------------------------------------------
188 // Field       : TIMER_INTR_ALARM_3
189 #define TIMER_INTR_ALARM_3_RESET  _u(0x0)
190 #define TIMER_INTR_ALARM_3_BITS   _u(0x00000008)
191 #define TIMER_INTR_ALARM_3_MSB    _u(3)
192 #define TIMER_INTR_ALARM_3_LSB    _u(3)
193 #define TIMER_INTR_ALARM_3_ACCESS "WC"
194 // -----------------------------------------------------------------------------
195 // Field       : TIMER_INTR_ALARM_2
196 #define TIMER_INTR_ALARM_2_RESET  _u(0x0)
197 #define TIMER_INTR_ALARM_2_BITS   _u(0x00000004)
198 #define TIMER_INTR_ALARM_2_MSB    _u(2)
199 #define TIMER_INTR_ALARM_2_LSB    _u(2)
200 #define TIMER_INTR_ALARM_2_ACCESS "WC"
201 // -----------------------------------------------------------------------------
202 // Field       : TIMER_INTR_ALARM_1
203 #define TIMER_INTR_ALARM_1_RESET  _u(0x0)
204 #define TIMER_INTR_ALARM_1_BITS   _u(0x00000002)
205 #define TIMER_INTR_ALARM_1_MSB    _u(1)
206 #define TIMER_INTR_ALARM_1_LSB    _u(1)
207 #define TIMER_INTR_ALARM_1_ACCESS "WC"
208 // -----------------------------------------------------------------------------
209 // Field       : TIMER_INTR_ALARM_0
210 #define TIMER_INTR_ALARM_0_RESET  _u(0x0)
211 #define TIMER_INTR_ALARM_0_BITS   _u(0x00000001)
212 #define TIMER_INTR_ALARM_0_MSB    _u(0)
213 #define TIMER_INTR_ALARM_0_LSB    _u(0)
214 #define TIMER_INTR_ALARM_0_ACCESS "WC"
215 // =============================================================================
216 // Register    : TIMER_INTE
217 // Description : Interrupt Enable
218 #define TIMER_INTE_OFFSET _u(0x00000038)
219 #define TIMER_INTE_BITS   _u(0x0000000f)
220 #define TIMER_INTE_RESET  _u(0x00000000)
221 // -----------------------------------------------------------------------------
222 // Field       : TIMER_INTE_ALARM_3
223 #define TIMER_INTE_ALARM_3_RESET  _u(0x0)
224 #define TIMER_INTE_ALARM_3_BITS   _u(0x00000008)
225 #define TIMER_INTE_ALARM_3_MSB    _u(3)
226 #define TIMER_INTE_ALARM_3_LSB    _u(3)
227 #define TIMER_INTE_ALARM_3_ACCESS "RW"
228 // -----------------------------------------------------------------------------
229 // Field       : TIMER_INTE_ALARM_2
230 #define TIMER_INTE_ALARM_2_RESET  _u(0x0)
231 #define TIMER_INTE_ALARM_2_BITS   _u(0x00000004)
232 #define TIMER_INTE_ALARM_2_MSB    _u(2)
233 #define TIMER_INTE_ALARM_2_LSB    _u(2)
234 #define TIMER_INTE_ALARM_2_ACCESS "RW"
235 // -----------------------------------------------------------------------------
236 // Field       : TIMER_INTE_ALARM_1
237 #define TIMER_INTE_ALARM_1_RESET  _u(0x0)
238 #define TIMER_INTE_ALARM_1_BITS   _u(0x00000002)
239 #define TIMER_INTE_ALARM_1_MSB    _u(1)
240 #define TIMER_INTE_ALARM_1_LSB    _u(1)
241 #define TIMER_INTE_ALARM_1_ACCESS "RW"
242 // -----------------------------------------------------------------------------
243 // Field       : TIMER_INTE_ALARM_0
244 #define TIMER_INTE_ALARM_0_RESET  _u(0x0)
245 #define TIMER_INTE_ALARM_0_BITS   _u(0x00000001)
246 #define TIMER_INTE_ALARM_0_MSB    _u(0)
247 #define TIMER_INTE_ALARM_0_LSB    _u(0)
248 #define TIMER_INTE_ALARM_0_ACCESS "RW"
249 // =============================================================================
250 // Register    : TIMER_INTF
251 // Description : Interrupt Force
252 #define TIMER_INTF_OFFSET _u(0x0000003c)
253 #define TIMER_INTF_BITS   _u(0x0000000f)
254 #define TIMER_INTF_RESET  _u(0x00000000)
255 // -----------------------------------------------------------------------------
256 // Field       : TIMER_INTF_ALARM_3
257 #define TIMER_INTF_ALARM_3_RESET  _u(0x0)
258 #define TIMER_INTF_ALARM_3_BITS   _u(0x00000008)
259 #define TIMER_INTF_ALARM_3_MSB    _u(3)
260 #define TIMER_INTF_ALARM_3_LSB    _u(3)
261 #define TIMER_INTF_ALARM_3_ACCESS "RW"
262 // -----------------------------------------------------------------------------
263 // Field       : TIMER_INTF_ALARM_2
264 #define TIMER_INTF_ALARM_2_RESET  _u(0x0)
265 #define TIMER_INTF_ALARM_2_BITS   _u(0x00000004)
266 #define TIMER_INTF_ALARM_2_MSB    _u(2)
267 #define TIMER_INTF_ALARM_2_LSB    _u(2)
268 #define TIMER_INTF_ALARM_2_ACCESS "RW"
269 // -----------------------------------------------------------------------------
270 // Field       : TIMER_INTF_ALARM_1
271 #define TIMER_INTF_ALARM_1_RESET  _u(0x0)
272 #define TIMER_INTF_ALARM_1_BITS   _u(0x00000002)
273 #define TIMER_INTF_ALARM_1_MSB    _u(1)
274 #define TIMER_INTF_ALARM_1_LSB    _u(1)
275 #define TIMER_INTF_ALARM_1_ACCESS "RW"
276 // -----------------------------------------------------------------------------
277 // Field       : TIMER_INTF_ALARM_0
278 #define TIMER_INTF_ALARM_0_RESET  _u(0x0)
279 #define TIMER_INTF_ALARM_0_BITS   _u(0x00000001)
280 #define TIMER_INTF_ALARM_0_MSB    _u(0)
281 #define TIMER_INTF_ALARM_0_LSB    _u(0)
282 #define TIMER_INTF_ALARM_0_ACCESS "RW"
283 // =============================================================================
284 // Register    : TIMER_INTS
285 // Description : Interrupt status after masking & forcing
286 #define TIMER_INTS_OFFSET _u(0x00000040)
287 #define TIMER_INTS_BITS   _u(0x0000000f)
288 #define TIMER_INTS_RESET  _u(0x00000000)
289 // -----------------------------------------------------------------------------
290 // Field       : TIMER_INTS_ALARM_3
291 #define TIMER_INTS_ALARM_3_RESET  _u(0x0)
292 #define TIMER_INTS_ALARM_3_BITS   _u(0x00000008)
293 #define TIMER_INTS_ALARM_3_MSB    _u(3)
294 #define TIMER_INTS_ALARM_3_LSB    _u(3)
295 #define TIMER_INTS_ALARM_3_ACCESS "RO"
296 // -----------------------------------------------------------------------------
297 // Field       : TIMER_INTS_ALARM_2
298 #define TIMER_INTS_ALARM_2_RESET  _u(0x0)
299 #define TIMER_INTS_ALARM_2_BITS   _u(0x00000004)
300 #define TIMER_INTS_ALARM_2_MSB    _u(2)
301 #define TIMER_INTS_ALARM_2_LSB    _u(2)
302 #define TIMER_INTS_ALARM_2_ACCESS "RO"
303 // -----------------------------------------------------------------------------
304 // Field       : TIMER_INTS_ALARM_1
305 #define TIMER_INTS_ALARM_1_RESET  _u(0x0)
306 #define TIMER_INTS_ALARM_1_BITS   _u(0x00000002)
307 #define TIMER_INTS_ALARM_1_MSB    _u(1)
308 #define TIMER_INTS_ALARM_1_LSB    _u(1)
309 #define TIMER_INTS_ALARM_1_ACCESS "RO"
310 // -----------------------------------------------------------------------------
311 // Field       : TIMER_INTS_ALARM_0
312 #define TIMER_INTS_ALARM_0_RESET  _u(0x0)
313 #define TIMER_INTS_ALARM_0_BITS   _u(0x00000001)
314 #define TIMER_INTS_ALARM_0_MSB    _u(0)
315 #define TIMER_INTS_ALARM_0_LSB    _u(0)
316 #define TIMER_INTS_ALARM_0_ACCESS "RO"
317 // =============================================================================
318 #endif // _HARDWARE_REGS_TIMER_H
319 
320