1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : SYSCFG 10 // Version : 1 11 // Bus type : apb 12 // Description : Register block for various chip control signals 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_SYSCFG_H 15 #define _HARDWARE_REGS_SYSCFG_H 16 // ============================================================================= 17 // Register : SYSCFG_PROC0_NMI_MASK 18 // Description : Processor core 0 NMI source mask 19 // Set a bit high to enable NMI from that IRQ 20 #define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000) 21 #define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff) 22 #define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000) 23 #define SYSCFG_PROC0_NMI_MASK_MSB _u(31) 24 #define SYSCFG_PROC0_NMI_MASK_LSB _u(0) 25 #define SYSCFG_PROC0_NMI_MASK_ACCESS "RW" 26 // ============================================================================= 27 // Register : SYSCFG_PROC1_NMI_MASK 28 // Description : Processor core 1 NMI source mask 29 // Set a bit high to enable NMI from that IRQ 30 #define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004) 31 #define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff) 32 #define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000) 33 #define SYSCFG_PROC1_NMI_MASK_MSB _u(31) 34 #define SYSCFG_PROC1_NMI_MASK_LSB _u(0) 35 #define SYSCFG_PROC1_NMI_MASK_ACCESS "RW" 36 // ============================================================================= 37 // Register : SYSCFG_PROC_CONFIG 38 // Description : Configuration for processors 39 #define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008) 40 #define SYSCFG_PROC_CONFIG_BITS _u(0xff000003) 41 #define SYSCFG_PROC_CONFIG_RESET _u(0x10000000) 42 // ----------------------------------------------------------------------------- 43 // Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID 44 // Description : Configure proc1 DAP instance ID. 45 // Recommend that this is NOT changed until you require debug 46 // access in multi-chip environment 47 // WARNING: do not set to 15 as this is reserved for RescueDP 48 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1) 49 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000) 50 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31) 51 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28) 52 #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW" 53 // ----------------------------------------------------------------------------- 54 // Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID 55 // Description : Configure proc0 DAP instance ID. 56 // Recommend that this is NOT changed until you require debug 57 // access in multi-chip environment 58 // WARNING: do not set to 15 as this is reserved for RescueDP 59 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0) 60 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000) 61 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27) 62 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24) 63 #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW" 64 // ----------------------------------------------------------------------------- 65 // Field : SYSCFG_PROC_CONFIG_PROC1_HALTED 66 // Description : Indication that proc1 has halted 67 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0) 68 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002) 69 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1) 70 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1) 71 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" 72 // ----------------------------------------------------------------------------- 73 // Field : SYSCFG_PROC_CONFIG_PROC0_HALTED 74 // Description : Indication that proc0 has halted 75 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0) 76 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001) 77 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0) 78 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0) 79 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" 80 // ============================================================================= 81 // Register : SYSCFG_PROC_IN_SYNC_BYPASS 82 // Description : For each bit, if 1, bypass the input synchronizer between that 83 // GPIO 84 // and the GPIO input register in the SIO. The input synchronizers 85 // should 86 // generally be unbypassed, to avoid injecting metastabilities 87 // into processors. 88 // If you're feeling brave, you can bypass to save two cycles of 89 // input 90 // latency. This register applies to GPIO 0...29. 91 #define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c) 92 #define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff) 93 #define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000) 94 #define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29) 95 #define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0) 96 #define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW" 97 // ============================================================================= 98 // Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI 99 // Description : For each bit, if 1, bypass the input synchronizer between that 100 // GPIO 101 // and the GPIO input register in the SIO. The input synchronizers 102 // should 103 // generally be unbypassed, to avoid injecting metastabilities 104 // into processors. 105 // If you're feeling brave, you can bypass to save two cycles of 106 // input 107 // latency. This register applies to GPIO 30...35 (the QSPI IOs). 108 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010) 109 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f) 110 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000) 111 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5) 112 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0) 113 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW" 114 // ============================================================================= 115 // Register : SYSCFG_DBGFORCE 116 // Description : Directly control the SWD debug port of either processor 117 #define SYSCFG_DBGFORCE_OFFSET _u(0x00000014) 118 #define SYSCFG_DBGFORCE_BITS _u(0x000000ff) 119 #define SYSCFG_DBGFORCE_RESET _u(0x00000066) 120 // ----------------------------------------------------------------------------- 121 // Field : SYSCFG_DBGFORCE_PROC1_ATTACH 122 // Description : Attach processor 1 debug port to syscfg controls, and 123 // disconnect it from external SWD pads. 124 #define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0) 125 #define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080) 126 #define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7) 127 #define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7) 128 #define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW" 129 // ----------------------------------------------------------------------------- 130 // Field : SYSCFG_DBGFORCE_PROC1_SWCLK 131 // Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set 132 #define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1) 133 #define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040) 134 #define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6) 135 #define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6) 136 #define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW" 137 // ----------------------------------------------------------------------------- 138 // Field : SYSCFG_DBGFORCE_PROC1_SWDI 139 // Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set 140 #define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1) 141 #define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020) 142 #define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5) 143 #define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5) 144 #define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW" 145 // ----------------------------------------------------------------------------- 146 // Field : SYSCFG_DBGFORCE_PROC1_SWDO 147 // Description : Observe the value of processor 1 SWDIO output. 148 #define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-" 149 #define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010) 150 #define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4) 151 #define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4) 152 #define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO" 153 // ----------------------------------------------------------------------------- 154 // Field : SYSCFG_DBGFORCE_PROC0_ATTACH 155 // Description : Attach processor 0 debug port to syscfg controls, and 156 // disconnect it from external SWD pads. 157 #define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0) 158 #define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008) 159 #define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3) 160 #define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3) 161 #define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : SYSCFG_DBGFORCE_PROC0_SWCLK 164 // Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set 165 #define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1) 166 #define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004) 167 #define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2) 168 #define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2) 169 #define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW" 170 // ----------------------------------------------------------------------------- 171 // Field : SYSCFG_DBGFORCE_PROC0_SWDI 172 // Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set 173 #define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1) 174 #define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002) 175 #define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1) 176 #define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1) 177 #define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW" 178 // ----------------------------------------------------------------------------- 179 // Field : SYSCFG_DBGFORCE_PROC0_SWDO 180 // Description : Observe the value of processor 0 SWDIO output. 181 #define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-" 182 #define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001) 183 #define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0) 184 #define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0) 185 #define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO" 186 // ============================================================================= 187 // Register : SYSCFG_MEMPOWERDOWN 188 // Description : Control power downs to memories. Set high to power down 189 // memories. 190 // Use with extreme caution 191 #define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018) 192 #define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff) 193 #define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) 194 // ----------------------------------------------------------------------------- 195 // Field : SYSCFG_MEMPOWERDOWN_ROM 196 #define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) 197 #define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080) 198 #define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7) 199 #define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7) 200 #define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" 201 // ----------------------------------------------------------------------------- 202 // Field : SYSCFG_MEMPOWERDOWN_USB 203 #define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) 204 #define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040) 205 #define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6) 206 #define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6) 207 #define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" 208 // ----------------------------------------------------------------------------- 209 // Field : SYSCFG_MEMPOWERDOWN_SRAM5 210 #define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) 211 #define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) 212 #define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) 213 #define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5) 214 #define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" 215 // ----------------------------------------------------------------------------- 216 // Field : SYSCFG_MEMPOWERDOWN_SRAM4 217 #define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) 218 #define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) 219 #define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) 220 #define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4) 221 #define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" 222 // ----------------------------------------------------------------------------- 223 // Field : SYSCFG_MEMPOWERDOWN_SRAM3 224 #define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) 225 #define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) 226 #define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) 227 #define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3) 228 #define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" 229 // ----------------------------------------------------------------------------- 230 // Field : SYSCFG_MEMPOWERDOWN_SRAM2 231 #define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) 232 #define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) 233 #define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) 234 #define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2) 235 #define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" 236 // ----------------------------------------------------------------------------- 237 // Field : SYSCFG_MEMPOWERDOWN_SRAM1 238 #define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) 239 #define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) 240 #define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) 241 #define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1) 242 #define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" 243 // ----------------------------------------------------------------------------- 244 // Field : SYSCFG_MEMPOWERDOWN_SRAM0 245 #define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) 246 #define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) 247 #define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) 248 #define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) 249 #define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" 250 // ============================================================================= 251 #endif // _HARDWARE_REGS_SYSCFG_H 252 253