1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : SPI 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_SPI_H 14 #define _HARDWARE_REGS_SPI_H 15 // ============================================================================= 16 // Register : SPI_SSPCR0 17 // Description : Control register 0, SSPCR0 on page 3-4 18 #define SPI_SSPCR0_OFFSET _u(0x00000000) 19 #define SPI_SSPCR0_BITS _u(0x0000ffff) 20 #define SPI_SSPCR0_RESET _u(0x00000000) 21 // ----------------------------------------------------------------------------- 22 // Field : SPI_SSPCR0_SCR 23 // Description : Serial clock rate. The value SCR is used to generate the 24 // transmit and receive bit rate of the PrimeCell SSP. The bit 25 // rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even 26 // value from 2-254, programmed through the SSPCPSR register and 27 // SCR is a value from 0-255. 28 #define SPI_SSPCR0_SCR_RESET _u(0x00) 29 #define SPI_SSPCR0_SCR_BITS _u(0x0000ff00) 30 #define SPI_SSPCR0_SCR_MSB _u(15) 31 #define SPI_SSPCR0_SCR_LSB _u(8) 32 #define SPI_SSPCR0_SCR_ACCESS "RW" 33 // ----------------------------------------------------------------------------- 34 // Field : SPI_SSPCR0_SPH 35 // Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. 36 // See Motorola SPI frame format on page 2-10. 37 #define SPI_SSPCR0_SPH_RESET _u(0x0) 38 #define SPI_SSPCR0_SPH_BITS _u(0x00000080) 39 #define SPI_SSPCR0_SPH_MSB _u(7) 40 #define SPI_SSPCR0_SPH_LSB _u(7) 41 #define SPI_SSPCR0_SPH_ACCESS "RW" 42 // ----------------------------------------------------------------------------- 43 // Field : SPI_SSPCR0_SPO 44 // Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format 45 // only. See Motorola SPI frame format on page 2-10. 46 #define SPI_SSPCR0_SPO_RESET _u(0x0) 47 #define SPI_SSPCR0_SPO_BITS _u(0x00000040) 48 #define SPI_SSPCR0_SPO_MSB _u(6) 49 #define SPI_SSPCR0_SPO_LSB _u(6) 50 #define SPI_SSPCR0_SPO_ACCESS "RW" 51 // ----------------------------------------------------------------------------- 52 // Field : SPI_SSPCR0_FRF 53 // Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous 54 // serial frame format. 10 National Microwire frame format. 11 55 // Reserved, undefined operation. 56 #define SPI_SSPCR0_FRF_RESET _u(0x0) 57 #define SPI_SSPCR0_FRF_BITS _u(0x00000030) 58 #define SPI_SSPCR0_FRF_MSB _u(5) 59 #define SPI_SSPCR0_FRF_LSB _u(4) 60 #define SPI_SSPCR0_FRF_ACCESS "RW" 61 // ----------------------------------------------------------------------------- 62 // Field : SPI_SSPCR0_DSS 63 // Description : Data Size Select: 0000 Reserved, undefined operation. 0001 64 // Reserved, undefined operation. 0010 Reserved, undefined 65 // operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 66 // 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit 67 // data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 68 // 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. 69 #define SPI_SSPCR0_DSS_RESET _u(0x0) 70 #define SPI_SSPCR0_DSS_BITS _u(0x0000000f) 71 #define SPI_SSPCR0_DSS_MSB _u(3) 72 #define SPI_SSPCR0_DSS_LSB _u(0) 73 #define SPI_SSPCR0_DSS_ACCESS "RW" 74 // ============================================================================= 75 // Register : SPI_SSPCR1 76 // Description : Control register 1, SSPCR1 on page 3-5 77 #define SPI_SSPCR1_OFFSET _u(0x00000004) 78 #define SPI_SSPCR1_BITS _u(0x0000000f) 79 #define SPI_SSPCR1_RESET _u(0x00000000) 80 // ----------------------------------------------------------------------------- 81 // Field : SPI_SSPCR1_SOD 82 // Description : Slave-mode output disable. This bit is relevant only in the 83 // slave mode, MS=1. In multiple-slave systems, it is possible for 84 // an PrimeCell SSP master to broadcast a message to all slaves in 85 // the system while ensuring that only one slave drives data onto 86 // its serial output line. In such systems the RXD lines from 87 // multiple slaves could be tied together. To operate in such 88 // systems, the SOD bit can be set if the PrimeCell SSP slave is 89 // not supposed to drive the SSPTXD line: 0 SSP can drive the 90 // SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD 91 // output in slave mode. 92 #define SPI_SSPCR1_SOD_RESET _u(0x0) 93 #define SPI_SSPCR1_SOD_BITS _u(0x00000008) 94 #define SPI_SSPCR1_SOD_MSB _u(3) 95 #define SPI_SSPCR1_SOD_LSB _u(3) 96 #define SPI_SSPCR1_SOD_ACCESS "RW" 97 // ----------------------------------------------------------------------------- 98 // Field : SPI_SSPCR1_MS 99 // Description : Master or slave mode select. This bit can be modified only when 100 // the PrimeCell SSP is disabled, SSE=0: 0 Device configured as 101 // master, default. 1 Device configured as slave. 102 #define SPI_SSPCR1_MS_RESET _u(0x0) 103 #define SPI_SSPCR1_MS_BITS _u(0x00000004) 104 #define SPI_SSPCR1_MS_MSB _u(2) 105 #define SPI_SSPCR1_MS_LSB _u(2) 106 #define SPI_SSPCR1_MS_ACCESS "RW" 107 // ----------------------------------------------------------------------------- 108 // Field : SPI_SSPCR1_SSE 109 // Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP 110 // operation enabled. 111 #define SPI_SSPCR1_SSE_RESET _u(0x0) 112 #define SPI_SSPCR1_SSE_BITS _u(0x00000002) 113 #define SPI_SSPCR1_SSE_MSB _u(1) 114 #define SPI_SSPCR1_SSE_LSB _u(1) 115 #define SPI_SSPCR1_SSE_ACCESS "RW" 116 // ----------------------------------------------------------------------------- 117 // Field : SPI_SSPCR1_LBM 118 // Description : Loop back mode: 0 Normal serial port operation enabled. 1 119 // Output of transmit serial shifter is connected to input of 120 // receive serial shifter internally. 121 #define SPI_SSPCR1_LBM_RESET _u(0x0) 122 #define SPI_SSPCR1_LBM_BITS _u(0x00000001) 123 #define SPI_SSPCR1_LBM_MSB _u(0) 124 #define SPI_SSPCR1_LBM_LSB _u(0) 125 #define SPI_SSPCR1_LBM_ACCESS "RW" 126 // ============================================================================= 127 // Register : SPI_SSPDR 128 // Description : Data register, SSPDR on page 3-6 129 #define SPI_SSPDR_OFFSET _u(0x00000008) 130 #define SPI_SSPDR_BITS _u(0x0000ffff) 131 #define SPI_SSPDR_RESET "-" 132 // ----------------------------------------------------------------------------- 133 // Field : SPI_SSPDR_DATA 134 // Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. 135 // You must right-justify data when the PrimeCell SSP is 136 // programmed for a data size that is less than 16 bits. Unused 137 // bits at the top are ignored by transmit logic. The receive 138 // logic automatically right-justifies. 139 #define SPI_SSPDR_DATA_RESET "-" 140 #define SPI_SSPDR_DATA_BITS _u(0x0000ffff) 141 #define SPI_SSPDR_DATA_MSB _u(15) 142 #define SPI_SSPDR_DATA_LSB _u(0) 143 #define SPI_SSPDR_DATA_ACCESS "RWF" 144 // ============================================================================= 145 // Register : SPI_SSPSR 146 // Description : Status register, SSPSR on page 3-7 147 #define SPI_SSPSR_OFFSET _u(0x0000000c) 148 #define SPI_SSPSR_BITS _u(0x0000001f) 149 #define SPI_SSPSR_RESET _u(0x00000003) 150 // ----------------------------------------------------------------------------- 151 // Field : SPI_SSPSR_BSY 152 // Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently 153 // transmitting and/or receiving a frame or the transmit FIFO is 154 // not empty. 155 #define SPI_SSPSR_BSY_RESET _u(0x0) 156 #define SPI_SSPSR_BSY_BITS _u(0x00000010) 157 #define SPI_SSPSR_BSY_MSB _u(4) 158 #define SPI_SSPSR_BSY_LSB _u(4) 159 #define SPI_SSPSR_BSY_ACCESS "RO" 160 // ----------------------------------------------------------------------------- 161 // Field : SPI_SSPSR_RFF 162 // Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive 163 // FIFO is full. 164 #define SPI_SSPSR_RFF_RESET _u(0x0) 165 #define SPI_SSPSR_RFF_BITS _u(0x00000008) 166 #define SPI_SSPSR_RFF_MSB _u(3) 167 #define SPI_SSPSR_RFF_LSB _u(3) 168 #define SPI_SSPSR_RFF_ACCESS "RO" 169 // ----------------------------------------------------------------------------- 170 // Field : SPI_SSPSR_RNE 171 // Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive 172 // FIFO is not empty. 173 #define SPI_SSPSR_RNE_RESET _u(0x0) 174 #define SPI_SSPSR_RNE_BITS _u(0x00000004) 175 #define SPI_SSPSR_RNE_MSB _u(2) 176 #define SPI_SSPSR_RNE_LSB _u(2) 177 #define SPI_SSPSR_RNE_ACCESS "RO" 178 // ----------------------------------------------------------------------------- 179 // Field : SPI_SSPSR_TNF 180 // Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit 181 // FIFO is not full. 182 #define SPI_SSPSR_TNF_RESET _u(0x1) 183 #define SPI_SSPSR_TNF_BITS _u(0x00000002) 184 #define SPI_SSPSR_TNF_MSB _u(1) 185 #define SPI_SSPSR_TNF_LSB _u(1) 186 #define SPI_SSPSR_TNF_ACCESS "RO" 187 // ----------------------------------------------------------------------------- 188 // Field : SPI_SSPSR_TFE 189 // Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 190 // Transmit FIFO is empty. 191 #define SPI_SSPSR_TFE_RESET _u(0x1) 192 #define SPI_SSPSR_TFE_BITS _u(0x00000001) 193 #define SPI_SSPSR_TFE_MSB _u(0) 194 #define SPI_SSPSR_TFE_LSB _u(0) 195 #define SPI_SSPSR_TFE_ACCESS "RO" 196 // ============================================================================= 197 // Register : SPI_SSPCPSR 198 // Description : Clock prescale register, SSPCPSR on page 3-8 199 #define SPI_SSPCPSR_OFFSET _u(0x00000010) 200 #define SPI_SSPCPSR_BITS _u(0x000000ff) 201 #define SPI_SSPCPSR_RESET _u(0x00000000) 202 // ----------------------------------------------------------------------------- 203 // Field : SPI_SSPCPSR_CPSDVSR 204 // Description : Clock prescale divisor. Must be an even number from 2-254, 205 // depending on the frequency of SSPCLK. The least significant bit 206 // always returns zero on reads. 207 #define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00) 208 #define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff) 209 #define SPI_SSPCPSR_CPSDVSR_MSB _u(7) 210 #define SPI_SSPCPSR_CPSDVSR_LSB _u(0) 211 #define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" 212 // ============================================================================= 213 // Register : SPI_SSPIMSC 214 // Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 215 #define SPI_SSPIMSC_OFFSET _u(0x00000014) 216 #define SPI_SSPIMSC_BITS _u(0x0000000f) 217 #define SPI_SSPIMSC_RESET _u(0x00000000) 218 // ----------------------------------------------------------------------------- 219 // Field : SPI_SSPIMSC_TXIM 220 // Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or 221 // less condition interrupt is masked. 1 Transmit FIFO half empty 222 // or less condition interrupt is not masked. 223 #define SPI_SSPIMSC_TXIM_RESET _u(0x0) 224 #define SPI_SSPIMSC_TXIM_BITS _u(0x00000008) 225 #define SPI_SSPIMSC_TXIM_MSB _u(3) 226 #define SPI_SSPIMSC_TXIM_LSB _u(3) 227 #define SPI_SSPIMSC_TXIM_ACCESS "RW" 228 // ----------------------------------------------------------------------------- 229 // Field : SPI_SSPIMSC_RXIM 230 // Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less 231 // condition interrupt is masked. 1 Receive FIFO half full or less 232 // condition interrupt is not masked. 233 #define SPI_SSPIMSC_RXIM_RESET _u(0x0) 234 #define SPI_SSPIMSC_RXIM_BITS _u(0x00000004) 235 #define SPI_SSPIMSC_RXIM_MSB _u(2) 236 #define SPI_SSPIMSC_RXIM_LSB _u(2) 237 #define SPI_SSPIMSC_RXIM_ACCESS "RW" 238 // ----------------------------------------------------------------------------- 239 // Field : SPI_SSPIMSC_RTIM 240 // Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no 241 // read prior to timeout period interrupt is masked. 1 Receive 242 // FIFO not empty and no read prior to timeout period interrupt is 243 // not masked. 244 #define SPI_SSPIMSC_RTIM_RESET _u(0x0) 245 #define SPI_SSPIMSC_RTIM_BITS _u(0x00000002) 246 #define SPI_SSPIMSC_RTIM_MSB _u(1) 247 #define SPI_SSPIMSC_RTIM_LSB _u(1) 248 #define SPI_SSPIMSC_RTIM_ACCESS "RW" 249 // ----------------------------------------------------------------------------- 250 // Field : SPI_SSPIMSC_RORIM 251 // Description : Receive overrun interrupt mask: 0 Receive FIFO written to while 252 // full condition interrupt is masked. 1 Receive FIFO written to 253 // while full condition interrupt is not masked. 254 #define SPI_SSPIMSC_RORIM_RESET _u(0x0) 255 #define SPI_SSPIMSC_RORIM_BITS _u(0x00000001) 256 #define SPI_SSPIMSC_RORIM_MSB _u(0) 257 #define SPI_SSPIMSC_RORIM_LSB _u(0) 258 #define SPI_SSPIMSC_RORIM_ACCESS "RW" 259 // ============================================================================= 260 // Register : SPI_SSPRIS 261 // Description : Raw interrupt status register, SSPRIS on page 3-10 262 #define SPI_SSPRIS_OFFSET _u(0x00000018) 263 #define SPI_SSPRIS_BITS _u(0x0000000f) 264 #define SPI_SSPRIS_RESET _u(0x00000008) 265 // ----------------------------------------------------------------------------- 266 // Field : SPI_SSPRIS_TXRIS 267 // Description : Gives the raw interrupt state, prior to masking, of the 268 // SSPTXINTR interrupt 269 #define SPI_SSPRIS_TXRIS_RESET _u(0x1) 270 #define SPI_SSPRIS_TXRIS_BITS _u(0x00000008) 271 #define SPI_SSPRIS_TXRIS_MSB _u(3) 272 #define SPI_SSPRIS_TXRIS_LSB _u(3) 273 #define SPI_SSPRIS_TXRIS_ACCESS "RO" 274 // ----------------------------------------------------------------------------- 275 // Field : SPI_SSPRIS_RXRIS 276 // Description : Gives the raw interrupt state, prior to masking, of the 277 // SSPRXINTR interrupt 278 #define SPI_SSPRIS_RXRIS_RESET _u(0x0) 279 #define SPI_SSPRIS_RXRIS_BITS _u(0x00000004) 280 #define SPI_SSPRIS_RXRIS_MSB _u(2) 281 #define SPI_SSPRIS_RXRIS_LSB _u(2) 282 #define SPI_SSPRIS_RXRIS_ACCESS "RO" 283 // ----------------------------------------------------------------------------- 284 // Field : SPI_SSPRIS_RTRIS 285 // Description : Gives the raw interrupt state, prior to masking, of the 286 // SSPRTINTR interrupt 287 #define SPI_SSPRIS_RTRIS_RESET _u(0x0) 288 #define SPI_SSPRIS_RTRIS_BITS _u(0x00000002) 289 #define SPI_SSPRIS_RTRIS_MSB _u(1) 290 #define SPI_SSPRIS_RTRIS_LSB _u(1) 291 #define SPI_SSPRIS_RTRIS_ACCESS "RO" 292 // ----------------------------------------------------------------------------- 293 // Field : SPI_SSPRIS_RORRIS 294 // Description : Gives the raw interrupt state, prior to masking, of the 295 // SSPRORINTR interrupt 296 #define SPI_SSPRIS_RORRIS_RESET _u(0x0) 297 #define SPI_SSPRIS_RORRIS_BITS _u(0x00000001) 298 #define SPI_SSPRIS_RORRIS_MSB _u(0) 299 #define SPI_SSPRIS_RORRIS_LSB _u(0) 300 #define SPI_SSPRIS_RORRIS_ACCESS "RO" 301 // ============================================================================= 302 // Register : SPI_SSPMIS 303 // Description : Masked interrupt status register, SSPMIS on page 3-11 304 #define SPI_SSPMIS_OFFSET _u(0x0000001c) 305 #define SPI_SSPMIS_BITS _u(0x0000000f) 306 #define SPI_SSPMIS_RESET _u(0x00000000) 307 // ----------------------------------------------------------------------------- 308 // Field : SPI_SSPMIS_TXMIS 309 // Description : Gives the transmit FIFO masked interrupt state, after masking, 310 // of the SSPTXINTR interrupt 311 #define SPI_SSPMIS_TXMIS_RESET _u(0x0) 312 #define SPI_SSPMIS_TXMIS_BITS _u(0x00000008) 313 #define SPI_SSPMIS_TXMIS_MSB _u(3) 314 #define SPI_SSPMIS_TXMIS_LSB _u(3) 315 #define SPI_SSPMIS_TXMIS_ACCESS "RO" 316 // ----------------------------------------------------------------------------- 317 // Field : SPI_SSPMIS_RXMIS 318 // Description : Gives the receive FIFO masked interrupt state, after masking, 319 // of the SSPRXINTR interrupt 320 #define SPI_SSPMIS_RXMIS_RESET _u(0x0) 321 #define SPI_SSPMIS_RXMIS_BITS _u(0x00000004) 322 #define SPI_SSPMIS_RXMIS_MSB _u(2) 323 #define SPI_SSPMIS_RXMIS_LSB _u(2) 324 #define SPI_SSPMIS_RXMIS_ACCESS "RO" 325 // ----------------------------------------------------------------------------- 326 // Field : SPI_SSPMIS_RTMIS 327 // Description : Gives the receive timeout masked interrupt state, after 328 // masking, of the SSPRTINTR interrupt 329 #define SPI_SSPMIS_RTMIS_RESET _u(0x0) 330 #define SPI_SSPMIS_RTMIS_BITS _u(0x00000002) 331 #define SPI_SSPMIS_RTMIS_MSB _u(1) 332 #define SPI_SSPMIS_RTMIS_LSB _u(1) 333 #define SPI_SSPMIS_RTMIS_ACCESS "RO" 334 // ----------------------------------------------------------------------------- 335 // Field : SPI_SSPMIS_RORMIS 336 // Description : Gives the receive over run masked interrupt status, after 337 // masking, of the SSPRORINTR interrupt 338 #define SPI_SSPMIS_RORMIS_RESET _u(0x0) 339 #define SPI_SSPMIS_RORMIS_BITS _u(0x00000001) 340 #define SPI_SSPMIS_RORMIS_MSB _u(0) 341 #define SPI_SSPMIS_RORMIS_LSB _u(0) 342 #define SPI_SSPMIS_RORMIS_ACCESS "RO" 343 // ============================================================================= 344 // Register : SPI_SSPICR 345 // Description : Interrupt clear register, SSPICR on page 3-11 346 #define SPI_SSPICR_OFFSET _u(0x00000020) 347 #define SPI_SSPICR_BITS _u(0x00000003) 348 #define SPI_SSPICR_RESET _u(0x00000000) 349 // ----------------------------------------------------------------------------- 350 // Field : SPI_SSPICR_RTIC 351 // Description : Clears the SSPRTINTR interrupt 352 #define SPI_SSPICR_RTIC_RESET _u(0x0) 353 #define SPI_SSPICR_RTIC_BITS _u(0x00000002) 354 #define SPI_SSPICR_RTIC_MSB _u(1) 355 #define SPI_SSPICR_RTIC_LSB _u(1) 356 #define SPI_SSPICR_RTIC_ACCESS "WC" 357 // ----------------------------------------------------------------------------- 358 // Field : SPI_SSPICR_RORIC 359 // Description : Clears the SSPRORINTR interrupt 360 #define SPI_SSPICR_RORIC_RESET _u(0x0) 361 #define SPI_SSPICR_RORIC_BITS _u(0x00000001) 362 #define SPI_SSPICR_RORIC_MSB _u(0) 363 #define SPI_SSPICR_RORIC_LSB _u(0) 364 #define SPI_SSPICR_RORIC_ACCESS "WC" 365 // ============================================================================= 366 // Register : SPI_SSPDMACR 367 // Description : DMA control register, SSPDMACR on page 3-12 368 #define SPI_SSPDMACR_OFFSET _u(0x00000024) 369 #define SPI_SSPDMACR_BITS _u(0x00000003) 370 #define SPI_SSPDMACR_RESET _u(0x00000000) 371 // ----------------------------------------------------------------------------- 372 // Field : SPI_SSPDMACR_TXDMAE 373 // Description : Transmit DMA Enable. If this bit is set to 1, DMA for the 374 // transmit FIFO is enabled. 375 #define SPI_SSPDMACR_TXDMAE_RESET _u(0x0) 376 #define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002) 377 #define SPI_SSPDMACR_TXDMAE_MSB _u(1) 378 #define SPI_SSPDMACR_TXDMAE_LSB _u(1) 379 #define SPI_SSPDMACR_TXDMAE_ACCESS "RW" 380 // ----------------------------------------------------------------------------- 381 // Field : SPI_SSPDMACR_RXDMAE 382 // Description : Receive DMA Enable. If this bit is set to 1, DMA for the 383 // receive FIFO is enabled. 384 #define SPI_SSPDMACR_RXDMAE_RESET _u(0x0) 385 #define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001) 386 #define SPI_SSPDMACR_RXDMAE_MSB _u(0) 387 #define SPI_SSPDMACR_RXDMAE_LSB _u(0) 388 #define SPI_SSPDMACR_RXDMAE_ACCESS "RW" 389 // ============================================================================= 390 // Register : SPI_SSPPERIPHID0 391 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 392 // 3-13 393 #define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0) 394 #define SPI_SSPPERIPHID0_BITS _u(0x000000ff) 395 #define SPI_SSPPERIPHID0_RESET _u(0x00000022) 396 // ----------------------------------------------------------------------------- 397 // Field : SPI_SSPPERIPHID0_PARTNUMBER0 398 // Description : These bits read back as 0x22 399 #define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22) 400 #define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) 401 #define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7) 402 #define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0) 403 #define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" 404 // ============================================================================= 405 // Register : SPI_SSPPERIPHID1 406 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 407 // 3-13 408 #define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4) 409 #define SPI_SSPPERIPHID1_BITS _u(0x000000ff) 410 #define SPI_SSPPERIPHID1_RESET _u(0x00000010) 411 // ----------------------------------------------------------------------------- 412 // Field : SPI_SSPPERIPHID1_DESIGNER0 413 // Description : These bits read back as 0x1 414 #define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1) 415 #define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0) 416 #define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7) 417 #define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4) 418 #define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" 419 // ----------------------------------------------------------------------------- 420 // Field : SPI_SSPPERIPHID1_PARTNUMBER1 421 // Description : These bits read back as 0x0 422 #define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0) 423 #define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) 424 #define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3) 425 #define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0) 426 #define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" 427 // ============================================================================= 428 // Register : SPI_SSPPERIPHID2 429 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 430 // 3-13 431 #define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8) 432 #define SPI_SSPPERIPHID2_BITS _u(0x000000ff) 433 #define SPI_SSPPERIPHID2_RESET _u(0x00000034) 434 // ----------------------------------------------------------------------------- 435 // Field : SPI_SSPPERIPHID2_REVISION 436 // Description : These bits return the peripheral revision 437 #define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3) 438 #define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0) 439 #define SPI_SSPPERIPHID2_REVISION_MSB _u(7) 440 #define SPI_SSPPERIPHID2_REVISION_LSB _u(4) 441 #define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" 442 // ----------------------------------------------------------------------------- 443 // Field : SPI_SSPPERIPHID2_DESIGNER1 444 // Description : These bits read back as 0x4 445 #define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4) 446 #define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f) 447 #define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3) 448 #define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0) 449 #define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" 450 // ============================================================================= 451 // Register : SPI_SSPPERIPHID3 452 // Description : Peripheral identification registers, SSPPeriphID0-3 on page 453 // 3-13 454 #define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec) 455 #define SPI_SSPPERIPHID3_BITS _u(0x000000ff) 456 #define SPI_SSPPERIPHID3_RESET _u(0x00000000) 457 // ----------------------------------------------------------------------------- 458 // Field : SPI_SSPPERIPHID3_CONFIGURATION 459 // Description : These bits read back as 0x00 460 #define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00) 461 #define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) 462 #define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7) 463 #define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0) 464 #define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" 465 // ============================================================================= 466 // Register : SPI_SSPPCELLID0 467 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 468 #define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0) 469 #define SPI_SSPPCELLID0_BITS _u(0x000000ff) 470 #define SPI_SSPPCELLID0_RESET _u(0x0000000d) 471 // ----------------------------------------------------------------------------- 472 // Field : SPI_SSPPCELLID0_SSPPCELLID0 473 // Description : These bits read back as 0x0D 474 #define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d) 475 #define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff) 476 #define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7) 477 #define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0) 478 #define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" 479 // ============================================================================= 480 // Register : SPI_SSPPCELLID1 481 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 482 #define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4) 483 #define SPI_SSPPCELLID1_BITS _u(0x000000ff) 484 #define SPI_SSPPCELLID1_RESET _u(0x000000f0) 485 // ----------------------------------------------------------------------------- 486 // Field : SPI_SSPPCELLID1_SSPPCELLID1 487 // Description : These bits read back as 0xF0 488 #define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0) 489 #define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff) 490 #define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7) 491 #define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0) 492 #define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" 493 // ============================================================================= 494 // Register : SPI_SSPPCELLID2 495 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 496 #define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8) 497 #define SPI_SSPPCELLID2_BITS _u(0x000000ff) 498 #define SPI_SSPPCELLID2_RESET _u(0x00000005) 499 // ----------------------------------------------------------------------------- 500 // Field : SPI_SSPPCELLID2_SSPPCELLID2 501 // Description : These bits read back as 0x05 502 #define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05) 503 #define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff) 504 #define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7) 505 #define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0) 506 #define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" 507 // ============================================================================= 508 // Register : SPI_SSPPCELLID3 509 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 510 #define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc) 511 #define SPI_SSPPCELLID3_BITS _u(0x000000ff) 512 #define SPI_SSPPCELLID3_RESET _u(0x000000b1) 513 // ----------------------------------------------------------------------------- 514 // Field : SPI_SSPPCELLID3_SSPPCELLID3 515 // Description : These bits read back as 0xB1 516 #define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1) 517 #define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff) 518 #define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7) 519 #define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) 520 #define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" 521 // ============================================================================= 522 #endif // _HARDWARE_REGS_SPI_H 523 524