1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : PSM 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_PSM_H 14 #define _HARDWARE_REGS_PSM_H 15 // ============================================================================= 16 // Register : PSM_FRCE_ON 17 // Description : Force block out of reset (i.e. power it on) 18 #define PSM_FRCE_ON_OFFSET _u(0x00000000) 19 #define PSM_FRCE_ON_BITS _u(0x0001ffff) 20 #define PSM_FRCE_ON_RESET _u(0x00000000) 21 // ----------------------------------------------------------------------------- 22 // Field : PSM_FRCE_ON_PROC1 23 #define PSM_FRCE_ON_PROC1_RESET _u(0x0) 24 #define PSM_FRCE_ON_PROC1_BITS _u(0x00010000) 25 #define PSM_FRCE_ON_PROC1_MSB _u(16) 26 #define PSM_FRCE_ON_PROC1_LSB _u(16) 27 #define PSM_FRCE_ON_PROC1_ACCESS "RW" 28 // ----------------------------------------------------------------------------- 29 // Field : PSM_FRCE_ON_PROC0 30 #define PSM_FRCE_ON_PROC0_RESET _u(0x0) 31 #define PSM_FRCE_ON_PROC0_BITS _u(0x00008000) 32 #define PSM_FRCE_ON_PROC0_MSB _u(15) 33 #define PSM_FRCE_ON_PROC0_LSB _u(15) 34 #define PSM_FRCE_ON_PROC0_ACCESS "RW" 35 // ----------------------------------------------------------------------------- 36 // Field : PSM_FRCE_ON_SIO 37 #define PSM_FRCE_ON_SIO_RESET _u(0x0) 38 #define PSM_FRCE_ON_SIO_BITS _u(0x00004000) 39 #define PSM_FRCE_ON_SIO_MSB _u(14) 40 #define PSM_FRCE_ON_SIO_LSB _u(14) 41 #define PSM_FRCE_ON_SIO_ACCESS "RW" 42 // ----------------------------------------------------------------------------- 43 // Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET 44 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0) 45 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000) 46 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13) 47 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13) 48 #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" 49 // ----------------------------------------------------------------------------- 50 // Field : PSM_FRCE_ON_XIP 51 #define PSM_FRCE_ON_XIP_RESET _u(0x0) 52 #define PSM_FRCE_ON_XIP_BITS _u(0x00001000) 53 #define PSM_FRCE_ON_XIP_MSB _u(12) 54 #define PSM_FRCE_ON_XIP_LSB _u(12) 55 #define PSM_FRCE_ON_XIP_ACCESS "RW" 56 // ----------------------------------------------------------------------------- 57 // Field : PSM_FRCE_ON_SRAM5 58 #define PSM_FRCE_ON_SRAM5_RESET _u(0x0) 59 #define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800) 60 #define PSM_FRCE_ON_SRAM5_MSB _u(11) 61 #define PSM_FRCE_ON_SRAM5_LSB _u(11) 62 #define PSM_FRCE_ON_SRAM5_ACCESS "RW" 63 // ----------------------------------------------------------------------------- 64 // Field : PSM_FRCE_ON_SRAM4 65 #define PSM_FRCE_ON_SRAM4_RESET _u(0x0) 66 #define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400) 67 #define PSM_FRCE_ON_SRAM4_MSB _u(10) 68 #define PSM_FRCE_ON_SRAM4_LSB _u(10) 69 #define PSM_FRCE_ON_SRAM4_ACCESS "RW" 70 // ----------------------------------------------------------------------------- 71 // Field : PSM_FRCE_ON_SRAM3 72 #define PSM_FRCE_ON_SRAM3_RESET _u(0x0) 73 #define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200) 74 #define PSM_FRCE_ON_SRAM3_MSB _u(9) 75 #define PSM_FRCE_ON_SRAM3_LSB _u(9) 76 #define PSM_FRCE_ON_SRAM3_ACCESS "RW" 77 // ----------------------------------------------------------------------------- 78 // Field : PSM_FRCE_ON_SRAM2 79 #define PSM_FRCE_ON_SRAM2_RESET _u(0x0) 80 #define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100) 81 #define PSM_FRCE_ON_SRAM2_MSB _u(8) 82 #define PSM_FRCE_ON_SRAM2_LSB _u(8) 83 #define PSM_FRCE_ON_SRAM2_ACCESS "RW" 84 // ----------------------------------------------------------------------------- 85 // Field : PSM_FRCE_ON_SRAM1 86 #define PSM_FRCE_ON_SRAM1_RESET _u(0x0) 87 #define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080) 88 #define PSM_FRCE_ON_SRAM1_MSB _u(7) 89 #define PSM_FRCE_ON_SRAM1_LSB _u(7) 90 #define PSM_FRCE_ON_SRAM1_ACCESS "RW" 91 // ----------------------------------------------------------------------------- 92 // Field : PSM_FRCE_ON_SRAM0 93 #define PSM_FRCE_ON_SRAM0_RESET _u(0x0) 94 #define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040) 95 #define PSM_FRCE_ON_SRAM0_MSB _u(6) 96 #define PSM_FRCE_ON_SRAM0_LSB _u(6) 97 #define PSM_FRCE_ON_SRAM0_ACCESS "RW" 98 // ----------------------------------------------------------------------------- 99 // Field : PSM_FRCE_ON_ROM 100 #define PSM_FRCE_ON_ROM_RESET _u(0x0) 101 #define PSM_FRCE_ON_ROM_BITS _u(0x00000020) 102 #define PSM_FRCE_ON_ROM_MSB _u(5) 103 #define PSM_FRCE_ON_ROM_LSB _u(5) 104 #define PSM_FRCE_ON_ROM_ACCESS "RW" 105 // ----------------------------------------------------------------------------- 106 // Field : PSM_FRCE_ON_BUSFABRIC 107 #define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) 108 #define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010) 109 #define PSM_FRCE_ON_BUSFABRIC_MSB _u(4) 110 #define PSM_FRCE_ON_BUSFABRIC_LSB _u(4) 111 #define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" 112 // ----------------------------------------------------------------------------- 113 // Field : PSM_FRCE_ON_RESETS 114 #define PSM_FRCE_ON_RESETS_RESET _u(0x0) 115 #define PSM_FRCE_ON_RESETS_BITS _u(0x00000008) 116 #define PSM_FRCE_ON_RESETS_MSB _u(3) 117 #define PSM_FRCE_ON_RESETS_LSB _u(3) 118 #define PSM_FRCE_ON_RESETS_ACCESS "RW" 119 // ----------------------------------------------------------------------------- 120 // Field : PSM_FRCE_ON_CLOCKS 121 #define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) 122 #define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004) 123 #define PSM_FRCE_ON_CLOCKS_MSB _u(2) 124 #define PSM_FRCE_ON_CLOCKS_LSB _u(2) 125 #define PSM_FRCE_ON_CLOCKS_ACCESS "RW" 126 // ----------------------------------------------------------------------------- 127 // Field : PSM_FRCE_ON_XOSC 128 #define PSM_FRCE_ON_XOSC_RESET _u(0x0) 129 #define PSM_FRCE_ON_XOSC_BITS _u(0x00000002) 130 #define PSM_FRCE_ON_XOSC_MSB _u(1) 131 #define PSM_FRCE_ON_XOSC_LSB _u(1) 132 #define PSM_FRCE_ON_XOSC_ACCESS "RW" 133 // ----------------------------------------------------------------------------- 134 // Field : PSM_FRCE_ON_ROSC 135 #define PSM_FRCE_ON_ROSC_RESET _u(0x0) 136 #define PSM_FRCE_ON_ROSC_BITS _u(0x00000001) 137 #define PSM_FRCE_ON_ROSC_MSB _u(0) 138 #define PSM_FRCE_ON_ROSC_LSB _u(0) 139 #define PSM_FRCE_ON_ROSC_ACCESS "RW" 140 // ============================================================================= 141 // Register : PSM_FRCE_OFF 142 // Description : Force into reset (i.e. power it off) 143 #define PSM_FRCE_OFF_OFFSET _u(0x00000004) 144 #define PSM_FRCE_OFF_BITS _u(0x0001ffff) 145 #define PSM_FRCE_OFF_RESET _u(0x00000000) 146 // ----------------------------------------------------------------------------- 147 // Field : PSM_FRCE_OFF_PROC1 148 #define PSM_FRCE_OFF_PROC1_RESET _u(0x0) 149 #define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000) 150 #define PSM_FRCE_OFF_PROC1_MSB _u(16) 151 #define PSM_FRCE_OFF_PROC1_LSB _u(16) 152 #define PSM_FRCE_OFF_PROC1_ACCESS "RW" 153 // ----------------------------------------------------------------------------- 154 // Field : PSM_FRCE_OFF_PROC0 155 #define PSM_FRCE_OFF_PROC0_RESET _u(0x0) 156 #define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000) 157 #define PSM_FRCE_OFF_PROC0_MSB _u(15) 158 #define PSM_FRCE_OFF_PROC0_LSB _u(15) 159 #define PSM_FRCE_OFF_PROC0_ACCESS "RW" 160 // ----------------------------------------------------------------------------- 161 // Field : PSM_FRCE_OFF_SIO 162 #define PSM_FRCE_OFF_SIO_RESET _u(0x0) 163 #define PSM_FRCE_OFF_SIO_BITS _u(0x00004000) 164 #define PSM_FRCE_OFF_SIO_MSB _u(14) 165 #define PSM_FRCE_OFF_SIO_LSB _u(14) 166 #define PSM_FRCE_OFF_SIO_ACCESS "RW" 167 // ----------------------------------------------------------------------------- 168 // Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET 169 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0) 170 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000) 171 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13) 172 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13) 173 #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" 174 // ----------------------------------------------------------------------------- 175 // Field : PSM_FRCE_OFF_XIP 176 #define PSM_FRCE_OFF_XIP_RESET _u(0x0) 177 #define PSM_FRCE_OFF_XIP_BITS _u(0x00001000) 178 #define PSM_FRCE_OFF_XIP_MSB _u(12) 179 #define PSM_FRCE_OFF_XIP_LSB _u(12) 180 #define PSM_FRCE_OFF_XIP_ACCESS "RW" 181 // ----------------------------------------------------------------------------- 182 // Field : PSM_FRCE_OFF_SRAM5 183 #define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) 184 #define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800) 185 #define PSM_FRCE_OFF_SRAM5_MSB _u(11) 186 #define PSM_FRCE_OFF_SRAM5_LSB _u(11) 187 #define PSM_FRCE_OFF_SRAM5_ACCESS "RW" 188 // ----------------------------------------------------------------------------- 189 // Field : PSM_FRCE_OFF_SRAM4 190 #define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) 191 #define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400) 192 #define PSM_FRCE_OFF_SRAM4_MSB _u(10) 193 #define PSM_FRCE_OFF_SRAM4_LSB _u(10) 194 #define PSM_FRCE_OFF_SRAM4_ACCESS "RW" 195 // ----------------------------------------------------------------------------- 196 // Field : PSM_FRCE_OFF_SRAM3 197 #define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) 198 #define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200) 199 #define PSM_FRCE_OFF_SRAM3_MSB _u(9) 200 #define PSM_FRCE_OFF_SRAM3_LSB _u(9) 201 #define PSM_FRCE_OFF_SRAM3_ACCESS "RW" 202 // ----------------------------------------------------------------------------- 203 // Field : PSM_FRCE_OFF_SRAM2 204 #define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) 205 #define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100) 206 #define PSM_FRCE_OFF_SRAM2_MSB _u(8) 207 #define PSM_FRCE_OFF_SRAM2_LSB _u(8) 208 #define PSM_FRCE_OFF_SRAM2_ACCESS "RW" 209 // ----------------------------------------------------------------------------- 210 // Field : PSM_FRCE_OFF_SRAM1 211 #define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) 212 #define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080) 213 #define PSM_FRCE_OFF_SRAM1_MSB _u(7) 214 #define PSM_FRCE_OFF_SRAM1_LSB _u(7) 215 #define PSM_FRCE_OFF_SRAM1_ACCESS "RW" 216 // ----------------------------------------------------------------------------- 217 // Field : PSM_FRCE_OFF_SRAM0 218 #define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) 219 #define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040) 220 #define PSM_FRCE_OFF_SRAM0_MSB _u(6) 221 #define PSM_FRCE_OFF_SRAM0_LSB _u(6) 222 #define PSM_FRCE_OFF_SRAM0_ACCESS "RW" 223 // ----------------------------------------------------------------------------- 224 // Field : PSM_FRCE_OFF_ROM 225 #define PSM_FRCE_OFF_ROM_RESET _u(0x0) 226 #define PSM_FRCE_OFF_ROM_BITS _u(0x00000020) 227 #define PSM_FRCE_OFF_ROM_MSB _u(5) 228 #define PSM_FRCE_OFF_ROM_LSB _u(5) 229 #define PSM_FRCE_OFF_ROM_ACCESS "RW" 230 // ----------------------------------------------------------------------------- 231 // Field : PSM_FRCE_OFF_BUSFABRIC 232 #define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) 233 #define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010) 234 #define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4) 235 #define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4) 236 #define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" 237 // ----------------------------------------------------------------------------- 238 // Field : PSM_FRCE_OFF_RESETS 239 #define PSM_FRCE_OFF_RESETS_RESET _u(0x0) 240 #define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008) 241 #define PSM_FRCE_OFF_RESETS_MSB _u(3) 242 #define PSM_FRCE_OFF_RESETS_LSB _u(3) 243 #define PSM_FRCE_OFF_RESETS_ACCESS "RW" 244 // ----------------------------------------------------------------------------- 245 // Field : PSM_FRCE_OFF_CLOCKS 246 #define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) 247 #define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004) 248 #define PSM_FRCE_OFF_CLOCKS_MSB _u(2) 249 #define PSM_FRCE_OFF_CLOCKS_LSB _u(2) 250 #define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" 251 // ----------------------------------------------------------------------------- 252 // Field : PSM_FRCE_OFF_XOSC 253 #define PSM_FRCE_OFF_XOSC_RESET _u(0x0) 254 #define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002) 255 #define PSM_FRCE_OFF_XOSC_MSB _u(1) 256 #define PSM_FRCE_OFF_XOSC_LSB _u(1) 257 #define PSM_FRCE_OFF_XOSC_ACCESS "RW" 258 // ----------------------------------------------------------------------------- 259 // Field : PSM_FRCE_OFF_ROSC 260 #define PSM_FRCE_OFF_ROSC_RESET _u(0x0) 261 #define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001) 262 #define PSM_FRCE_OFF_ROSC_MSB _u(0) 263 #define PSM_FRCE_OFF_ROSC_LSB _u(0) 264 #define PSM_FRCE_OFF_ROSC_ACCESS "RW" 265 // ============================================================================= 266 // Register : PSM_WDSEL 267 // Description : Set to 1 if this peripheral should be reset when the watchdog 268 // fires. 269 #define PSM_WDSEL_OFFSET _u(0x00000008) 270 #define PSM_WDSEL_BITS _u(0x0001ffff) 271 #define PSM_WDSEL_RESET _u(0x00000000) 272 // ----------------------------------------------------------------------------- 273 // Field : PSM_WDSEL_PROC1 274 #define PSM_WDSEL_PROC1_RESET _u(0x0) 275 #define PSM_WDSEL_PROC1_BITS _u(0x00010000) 276 #define PSM_WDSEL_PROC1_MSB _u(16) 277 #define PSM_WDSEL_PROC1_LSB _u(16) 278 #define PSM_WDSEL_PROC1_ACCESS "RW" 279 // ----------------------------------------------------------------------------- 280 // Field : PSM_WDSEL_PROC0 281 #define PSM_WDSEL_PROC0_RESET _u(0x0) 282 #define PSM_WDSEL_PROC0_BITS _u(0x00008000) 283 #define PSM_WDSEL_PROC0_MSB _u(15) 284 #define PSM_WDSEL_PROC0_LSB _u(15) 285 #define PSM_WDSEL_PROC0_ACCESS "RW" 286 // ----------------------------------------------------------------------------- 287 // Field : PSM_WDSEL_SIO 288 #define PSM_WDSEL_SIO_RESET _u(0x0) 289 #define PSM_WDSEL_SIO_BITS _u(0x00004000) 290 #define PSM_WDSEL_SIO_MSB _u(14) 291 #define PSM_WDSEL_SIO_LSB _u(14) 292 #define PSM_WDSEL_SIO_ACCESS "RW" 293 // ----------------------------------------------------------------------------- 294 // Field : PSM_WDSEL_VREG_AND_CHIP_RESET 295 #define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0) 296 #define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000) 297 #define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13) 298 #define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13) 299 #define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" 300 // ----------------------------------------------------------------------------- 301 // Field : PSM_WDSEL_XIP 302 #define PSM_WDSEL_XIP_RESET _u(0x0) 303 #define PSM_WDSEL_XIP_BITS _u(0x00001000) 304 #define PSM_WDSEL_XIP_MSB _u(12) 305 #define PSM_WDSEL_XIP_LSB _u(12) 306 #define PSM_WDSEL_XIP_ACCESS "RW" 307 // ----------------------------------------------------------------------------- 308 // Field : PSM_WDSEL_SRAM5 309 #define PSM_WDSEL_SRAM5_RESET _u(0x0) 310 #define PSM_WDSEL_SRAM5_BITS _u(0x00000800) 311 #define PSM_WDSEL_SRAM5_MSB _u(11) 312 #define PSM_WDSEL_SRAM5_LSB _u(11) 313 #define PSM_WDSEL_SRAM5_ACCESS "RW" 314 // ----------------------------------------------------------------------------- 315 // Field : PSM_WDSEL_SRAM4 316 #define PSM_WDSEL_SRAM4_RESET _u(0x0) 317 #define PSM_WDSEL_SRAM4_BITS _u(0x00000400) 318 #define PSM_WDSEL_SRAM4_MSB _u(10) 319 #define PSM_WDSEL_SRAM4_LSB _u(10) 320 #define PSM_WDSEL_SRAM4_ACCESS "RW" 321 // ----------------------------------------------------------------------------- 322 // Field : PSM_WDSEL_SRAM3 323 #define PSM_WDSEL_SRAM3_RESET _u(0x0) 324 #define PSM_WDSEL_SRAM3_BITS _u(0x00000200) 325 #define PSM_WDSEL_SRAM3_MSB _u(9) 326 #define PSM_WDSEL_SRAM3_LSB _u(9) 327 #define PSM_WDSEL_SRAM3_ACCESS "RW" 328 // ----------------------------------------------------------------------------- 329 // Field : PSM_WDSEL_SRAM2 330 #define PSM_WDSEL_SRAM2_RESET _u(0x0) 331 #define PSM_WDSEL_SRAM2_BITS _u(0x00000100) 332 #define PSM_WDSEL_SRAM2_MSB _u(8) 333 #define PSM_WDSEL_SRAM2_LSB _u(8) 334 #define PSM_WDSEL_SRAM2_ACCESS "RW" 335 // ----------------------------------------------------------------------------- 336 // Field : PSM_WDSEL_SRAM1 337 #define PSM_WDSEL_SRAM1_RESET _u(0x0) 338 #define PSM_WDSEL_SRAM1_BITS _u(0x00000080) 339 #define PSM_WDSEL_SRAM1_MSB _u(7) 340 #define PSM_WDSEL_SRAM1_LSB _u(7) 341 #define PSM_WDSEL_SRAM1_ACCESS "RW" 342 // ----------------------------------------------------------------------------- 343 // Field : PSM_WDSEL_SRAM0 344 #define PSM_WDSEL_SRAM0_RESET _u(0x0) 345 #define PSM_WDSEL_SRAM0_BITS _u(0x00000040) 346 #define PSM_WDSEL_SRAM0_MSB _u(6) 347 #define PSM_WDSEL_SRAM0_LSB _u(6) 348 #define PSM_WDSEL_SRAM0_ACCESS "RW" 349 // ----------------------------------------------------------------------------- 350 // Field : PSM_WDSEL_ROM 351 #define PSM_WDSEL_ROM_RESET _u(0x0) 352 #define PSM_WDSEL_ROM_BITS _u(0x00000020) 353 #define PSM_WDSEL_ROM_MSB _u(5) 354 #define PSM_WDSEL_ROM_LSB _u(5) 355 #define PSM_WDSEL_ROM_ACCESS "RW" 356 // ----------------------------------------------------------------------------- 357 // Field : PSM_WDSEL_BUSFABRIC 358 #define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) 359 #define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010) 360 #define PSM_WDSEL_BUSFABRIC_MSB _u(4) 361 #define PSM_WDSEL_BUSFABRIC_LSB _u(4) 362 #define PSM_WDSEL_BUSFABRIC_ACCESS "RW" 363 // ----------------------------------------------------------------------------- 364 // Field : PSM_WDSEL_RESETS 365 #define PSM_WDSEL_RESETS_RESET _u(0x0) 366 #define PSM_WDSEL_RESETS_BITS _u(0x00000008) 367 #define PSM_WDSEL_RESETS_MSB _u(3) 368 #define PSM_WDSEL_RESETS_LSB _u(3) 369 #define PSM_WDSEL_RESETS_ACCESS "RW" 370 // ----------------------------------------------------------------------------- 371 // Field : PSM_WDSEL_CLOCKS 372 #define PSM_WDSEL_CLOCKS_RESET _u(0x0) 373 #define PSM_WDSEL_CLOCKS_BITS _u(0x00000004) 374 #define PSM_WDSEL_CLOCKS_MSB _u(2) 375 #define PSM_WDSEL_CLOCKS_LSB _u(2) 376 #define PSM_WDSEL_CLOCKS_ACCESS "RW" 377 // ----------------------------------------------------------------------------- 378 // Field : PSM_WDSEL_XOSC 379 #define PSM_WDSEL_XOSC_RESET _u(0x0) 380 #define PSM_WDSEL_XOSC_BITS _u(0x00000002) 381 #define PSM_WDSEL_XOSC_MSB _u(1) 382 #define PSM_WDSEL_XOSC_LSB _u(1) 383 #define PSM_WDSEL_XOSC_ACCESS "RW" 384 // ----------------------------------------------------------------------------- 385 // Field : PSM_WDSEL_ROSC 386 #define PSM_WDSEL_ROSC_RESET _u(0x0) 387 #define PSM_WDSEL_ROSC_BITS _u(0x00000001) 388 #define PSM_WDSEL_ROSC_MSB _u(0) 389 #define PSM_WDSEL_ROSC_LSB _u(0) 390 #define PSM_WDSEL_ROSC_ACCESS "RW" 391 // ============================================================================= 392 // Register : PSM_DONE 393 // Description : Indicates the peripheral's registers are ready to access. 394 #define PSM_DONE_OFFSET _u(0x0000000c) 395 #define PSM_DONE_BITS _u(0x0001ffff) 396 #define PSM_DONE_RESET _u(0x00000000) 397 // ----------------------------------------------------------------------------- 398 // Field : PSM_DONE_PROC1 399 #define PSM_DONE_PROC1_RESET _u(0x0) 400 #define PSM_DONE_PROC1_BITS _u(0x00010000) 401 #define PSM_DONE_PROC1_MSB _u(16) 402 #define PSM_DONE_PROC1_LSB _u(16) 403 #define PSM_DONE_PROC1_ACCESS "RO" 404 // ----------------------------------------------------------------------------- 405 // Field : PSM_DONE_PROC0 406 #define PSM_DONE_PROC0_RESET _u(0x0) 407 #define PSM_DONE_PROC0_BITS _u(0x00008000) 408 #define PSM_DONE_PROC0_MSB _u(15) 409 #define PSM_DONE_PROC0_LSB _u(15) 410 #define PSM_DONE_PROC0_ACCESS "RO" 411 // ----------------------------------------------------------------------------- 412 // Field : PSM_DONE_SIO 413 #define PSM_DONE_SIO_RESET _u(0x0) 414 #define PSM_DONE_SIO_BITS _u(0x00004000) 415 #define PSM_DONE_SIO_MSB _u(14) 416 #define PSM_DONE_SIO_LSB _u(14) 417 #define PSM_DONE_SIO_ACCESS "RO" 418 // ----------------------------------------------------------------------------- 419 // Field : PSM_DONE_VREG_AND_CHIP_RESET 420 #define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0) 421 #define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000) 422 #define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13) 423 #define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13) 424 #define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" 425 // ----------------------------------------------------------------------------- 426 // Field : PSM_DONE_XIP 427 #define PSM_DONE_XIP_RESET _u(0x0) 428 #define PSM_DONE_XIP_BITS _u(0x00001000) 429 #define PSM_DONE_XIP_MSB _u(12) 430 #define PSM_DONE_XIP_LSB _u(12) 431 #define PSM_DONE_XIP_ACCESS "RO" 432 // ----------------------------------------------------------------------------- 433 // Field : PSM_DONE_SRAM5 434 #define PSM_DONE_SRAM5_RESET _u(0x0) 435 #define PSM_DONE_SRAM5_BITS _u(0x00000800) 436 #define PSM_DONE_SRAM5_MSB _u(11) 437 #define PSM_DONE_SRAM5_LSB _u(11) 438 #define PSM_DONE_SRAM5_ACCESS "RO" 439 // ----------------------------------------------------------------------------- 440 // Field : PSM_DONE_SRAM4 441 #define PSM_DONE_SRAM4_RESET _u(0x0) 442 #define PSM_DONE_SRAM4_BITS _u(0x00000400) 443 #define PSM_DONE_SRAM4_MSB _u(10) 444 #define PSM_DONE_SRAM4_LSB _u(10) 445 #define PSM_DONE_SRAM4_ACCESS "RO" 446 // ----------------------------------------------------------------------------- 447 // Field : PSM_DONE_SRAM3 448 #define PSM_DONE_SRAM3_RESET _u(0x0) 449 #define PSM_DONE_SRAM3_BITS _u(0x00000200) 450 #define PSM_DONE_SRAM3_MSB _u(9) 451 #define PSM_DONE_SRAM3_LSB _u(9) 452 #define PSM_DONE_SRAM3_ACCESS "RO" 453 // ----------------------------------------------------------------------------- 454 // Field : PSM_DONE_SRAM2 455 #define PSM_DONE_SRAM2_RESET _u(0x0) 456 #define PSM_DONE_SRAM2_BITS _u(0x00000100) 457 #define PSM_DONE_SRAM2_MSB _u(8) 458 #define PSM_DONE_SRAM2_LSB _u(8) 459 #define PSM_DONE_SRAM2_ACCESS "RO" 460 // ----------------------------------------------------------------------------- 461 // Field : PSM_DONE_SRAM1 462 #define PSM_DONE_SRAM1_RESET _u(0x0) 463 #define PSM_DONE_SRAM1_BITS _u(0x00000080) 464 #define PSM_DONE_SRAM1_MSB _u(7) 465 #define PSM_DONE_SRAM1_LSB _u(7) 466 #define PSM_DONE_SRAM1_ACCESS "RO" 467 // ----------------------------------------------------------------------------- 468 // Field : PSM_DONE_SRAM0 469 #define PSM_DONE_SRAM0_RESET _u(0x0) 470 #define PSM_DONE_SRAM0_BITS _u(0x00000040) 471 #define PSM_DONE_SRAM0_MSB _u(6) 472 #define PSM_DONE_SRAM0_LSB _u(6) 473 #define PSM_DONE_SRAM0_ACCESS "RO" 474 // ----------------------------------------------------------------------------- 475 // Field : PSM_DONE_ROM 476 #define PSM_DONE_ROM_RESET _u(0x0) 477 #define PSM_DONE_ROM_BITS _u(0x00000020) 478 #define PSM_DONE_ROM_MSB _u(5) 479 #define PSM_DONE_ROM_LSB _u(5) 480 #define PSM_DONE_ROM_ACCESS "RO" 481 // ----------------------------------------------------------------------------- 482 // Field : PSM_DONE_BUSFABRIC 483 #define PSM_DONE_BUSFABRIC_RESET _u(0x0) 484 #define PSM_DONE_BUSFABRIC_BITS _u(0x00000010) 485 #define PSM_DONE_BUSFABRIC_MSB _u(4) 486 #define PSM_DONE_BUSFABRIC_LSB _u(4) 487 #define PSM_DONE_BUSFABRIC_ACCESS "RO" 488 // ----------------------------------------------------------------------------- 489 // Field : PSM_DONE_RESETS 490 #define PSM_DONE_RESETS_RESET _u(0x0) 491 #define PSM_DONE_RESETS_BITS _u(0x00000008) 492 #define PSM_DONE_RESETS_MSB _u(3) 493 #define PSM_DONE_RESETS_LSB _u(3) 494 #define PSM_DONE_RESETS_ACCESS "RO" 495 // ----------------------------------------------------------------------------- 496 // Field : PSM_DONE_CLOCKS 497 #define PSM_DONE_CLOCKS_RESET _u(0x0) 498 #define PSM_DONE_CLOCKS_BITS _u(0x00000004) 499 #define PSM_DONE_CLOCKS_MSB _u(2) 500 #define PSM_DONE_CLOCKS_LSB _u(2) 501 #define PSM_DONE_CLOCKS_ACCESS "RO" 502 // ----------------------------------------------------------------------------- 503 // Field : PSM_DONE_XOSC 504 #define PSM_DONE_XOSC_RESET _u(0x0) 505 #define PSM_DONE_XOSC_BITS _u(0x00000002) 506 #define PSM_DONE_XOSC_MSB _u(1) 507 #define PSM_DONE_XOSC_LSB _u(1) 508 #define PSM_DONE_XOSC_ACCESS "RO" 509 // ----------------------------------------------------------------------------- 510 // Field : PSM_DONE_ROSC 511 #define PSM_DONE_ROSC_RESET _u(0x0) 512 #define PSM_DONE_ROSC_BITS _u(0x00000001) 513 #define PSM_DONE_ROSC_MSB _u(0) 514 #define PSM_DONE_ROSC_LSB _u(0) 515 #define PSM_DONE_ROSC_ACCESS "RO" 516 // ============================================================================= 517 #endif // _HARDWARE_REGS_PSM_H 518 519
