1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : PLL
10 // Version        : 1
11 // Bus type       : apb
12 // =============================================================================
13 #ifndef _HARDWARE_REGS_PLL_H
14 #define _HARDWARE_REGS_PLL_H
15 // =============================================================================
16 // Register    : PLL_CS
17 // Description : Control and Status
18 //               GENERAL CONSTRAINTS:
19 //               Reference clock frequency min=5MHz, max=800MHz
20 //               Feedback divider min=16, max=320
21 //               VCO frequency min=750MHz, max=1600MHz
22 #define PLL_CS_OFFSET _u(0x00000000)
23 #define PLL_CS_BITS   _u(0x8000013f)
24 #define PLL_CS_RESET  _u(0x00000001)
25 // -----------------------------------------------------------------------------
26 // Field       : PLL_CS_LOCK
27 // Description : PLL is locked
28 #define PLL_CS_LOCK_RESET  _u(0x0)
29 #define PLL_CS_LOCK_BITS   _u(0x80000000)
30 #define PLL_CS_LOCK_MSB    _u(31)
31 #define PLL_CS_LOCK_LSB    _u(31)
32 #define PLL_CS_LOCK_ACCESS "RO"
33 // -----------------------------------------------------------------------------
34 // Field       : PLL_CS_BYPASS
35 // Description : Passes the reference clock to the output instead of the divided
36 //               VCO. The VCO continues to run so the user can switch between
37 //               the reference clock and the divided VCO but the output will
38 //               glitch when doing so.
39 #define PLL_CS_BYPASS_RESET  _u(0x0)
40 #define PLL_CS_BYPASS_BITS   _u(0x00000100)
41 #define PLL_CS_BYPASS_MSB    _u(8)
42 #define PLL_CS_BYPASS_LSB    _u(8)
43 #define PLL_CS_BYPASS_ACCESS "RW"
44 // -----------------------------------------------------------------------------
45 // Field       : PLL_CS_REFDIV
46 // Description : Divides the PLL input reference clock.
47 //               Behaviour is undefined for div=0.
48 //               PLL output will be unpredictable during refdiv changes, wait
49 //               for lock=1 before using it.
50 #define PLL_CS_REFDIV_RESET  _u(0x01)
51 #define PLL_CS_REFDIV_BITS   _u(0x0000003f)
52 #define PLL_CS_REFDIV_MSB    _u(5)
53 #define PLL_CS_REFDIV_LSB    _u(0)
54 #define PLL_CS_REFDIV_ACCESS "RW"
55 // =============================================================================
56 // Register    : PLL_PWR
57 // Description : Controls the PLL power modes.
58 #define PLL_PWR_OFFSET _u(0x00000004)
59 #define PLL_PWR_BITS   _u(0x0000002d)
60 #define PLL_PWR_RESET  _u(0x0000002d)
61 // -----------------------------------------------------------------------------
62 // Field       : PLL_PWR_VCOPD
63 // Description : PLL VCO powerdown
64 //               To save power set high when PLL output not required or
65 //               bypass=1.
66 #define PLL_PWR_VCOPD_RESET  _u(0x1)
67 #define PLL_PWR_VCOPD_BITS   _u(0x00000020)
68 #define PLL_PWR_VCOPD_MSB    _u(5)
69 #define PLL_PWR_VCOPD_LSB    _u(5)
70 #define PLL_PWR_VCOPD_ACCESS "RW"
71 // -----------------------------------------------------------------------------
72 // Field       : PLL_PWR_POSTDIVPD
73 // Description : PLL post divider powerdown
74 //               To save power set high when PLL output not required or
75 //               bypass=1.
76 #define PLL_PWR_POSTDIVPD_RESET  _u(0x1)
77 #define PLL_PWR_POSTDIVPD_BITS   _u(0x00000008)
78 #define PLL_PWR_POSTDIVPD_MSB    _u(3)
79 #define PLL_PWR_POSTDIVPD_LSB    _u(3)
80 #define PLL_PWR_POSTDIVPD_ACCESS "RW"
81 // -----------------------------------------------------------------------------
82 // Field       : PLL_PWR_DSMPD
83 // Description : PLL DSM powerdown
84 //               Nothing is achieved by setting this low.
85 #define PLL_PWR_DSMPD_RESET  _u(0x1)
86 #define PLL_PWR_DSMPD_BITS   _u(0x00000004)
87 #define PLL_PWR_DSMPD_MSB    _u(2)
88 #define PLL_PWR_DSMPD_LSB    _u(2)
89 #define PLL_PWR_DSMPD_ACCESS "RW"
90 // -----------------------------------------------------------------------------
91 // Field       : PLL_PWR_PD
92 // Description : PLL powerdown
93 //               To save power set high when PLL output not required.
94 #define PLL_PWR_PD_RESET  _u(0x1)
95 #define PLL_PWR_PD_BITS   _u(0x00000001)
96 #define PLL_PWR_PD_MSB    _u(0)
97 #define PLL_PWR_PD_LSB    _u(0)
98 #define PLL_PWR_PD_ACCESS "RW"
99 // =============================================================================
100 // Register    : PLL_FBDIV_INT
101 // Description : Feedback divisor
102 //               (note: this PLL does not support fractional division)
103 //               see ctrl reg description for constraints
104 #define PLL_FBDIV_INT_OFFSET _u(0x00000008)
105 #define PLL_FBDIV_INT_BITS   _u(0x00000fff)
106 #define PLL_FBDIV_INT_RESET  _u(0x00000000)
107 #define PLL_FBDIV_INT_MSB    _u(11)
108 #define PLL_FBDIV_INT_LSB    _u(0)
109 #define PLL_FBDIV_INT_ACCESS "RW"
110 // =============================================================================
111 // Register    : PLL_PRIM
112 // Description : Controls the PLL post dividers for the primary output
113 //               (note: this PLL does not have a secondary output)
114 //               the primary output is driven from VCO divided by
115 //               postdiv1*postdiv2
116 #define PLL_PRIM_OFFSET _u(0x0000000c)
117 #define PLL_PRIM_BITS   _u(0x00077000)
118 #define PLL_PRIM_RESET  _u(0x00077000)
119 // -----------------------------------------------------------------------------
120 // Field       : PLL_PRIM_POSTDIV1
121 // Description : divide by 1-7
122 #define PLL_PRIM_POSTDIV1_RESET  _u(0x7)
123 #define PLL_PRIM_POSTDIV1_BITS   _u(0x00070000)
124 #define PLL_PRIM_POSTDIV1_MSB    _u(18)
125 #define PLL_PRIM_POSTDIV1_LSB    _u(16)
126 #define PLL_PRIM_POSTDIV1_ACCESS "RW"
127 // -----------------------------------------------------------------------------
128 // Field       : PLL_PRIM_POSTDIV2
129 // Description : divide by 1-7
130 #define PLL_PRIM_POSTDIV2_RESET  _u(0x7)
131 #define PLL_PRIM_POSTDIV2_BITS   _u(0x00007000)
132 #define PLL_PRIM_POSTDIV2_MSB    _u(14)
133 #define PLL_PRIM_POSTDIV2_LSB    _u(12)
134 #define PLL_PRIM_POSTDIV2_ACCESS "RW"
135 // =============================================================================
136 #endif // _HARDWARE_REGS_PLL_H
137 
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