1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : PADS_QSPI
10 // Version        : 1
11 // Bus type       : apb
12 // =============================================================================
13 #ifndef _HARDWARE_REGS_PADS_QSPI_H
14 #define _HARDWARE_REGS_PADS_QSPI_H
15 // =============================================================================
16 // Register    : PADS_QSPI_VOLTAGE_SELECT
17 // Description : Voltage select. Per bank control
18 //               0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
19 //               0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
20 #define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
21 #define PADS_QSPI_VOLTAGE_SELECT_BITS   _u(0x00000001)
22 #define PADS_QSPI_VOLTAGE_SELECT_RESET  _u(0x00000000)
23 #define PADS_QSPI_VOLTAGE_SELECT_MSB    _u(0)
24 #define PADS_QSPI_VOLTAGE_SELECT_LSB    _u(0)
25 #define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
26 #define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
27 #define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
28 // =============================================================================
29 // Register    : PADS_QSPI_GPIO_QSPI_SCLK
30 // Description : Pad control register
31 #define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
32 #define PADS_QSPI_GPIO_QSPI_SCLK_BITS   _u(0x000000ff)
33 #define PADS_QSPI_GPIO_QSPI_SCLK_RESET  _u(0x00000056)
34 // -----------------------------------------------------------------------------
35 // Field       : PADS_QSPI_GPIO_QSPI_SCLK_OD
36 // Description : Output disable. Has priority over output enable from
37 //               peripherals
38 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET  _u(0x0)
39 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS   _u(0x00000080)
40 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB    _u(7)
41 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB    _u(7)
42 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
43 // -----------------------------------------------------------------------------
44 // Field       : PADS_QSPI_GPIO_QSPI_SCLK_IE
45 // Description : Input enable
46 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET  _u(0x1)
47 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS   _u(0x00000040)
48 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB    _u(6)
49 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB    _u(6)
50 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
51 // -----------------------------------------------------------------------------
52 // Field       : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
53 // Description : Drive strength.
54 //               0x0 -> 2mA
55 //               0x1 -> 4mA
56 //               0x2 -> 8mA
57 //               0x3 -> 12mA
58 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET  _u(0x1)
59 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS   _u(0x00000030)
60 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB    _u(5)
61 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB    _u(4)
62 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
63 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
64 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
65 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
66 #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
67 // -----------------------------------------------------------------------------
68 // Field       : PADS_QSPI_GPIO_QSPI_SCLK_PUE
69 // Description : Pull up enable
70 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET  _u(0x0)
71 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS   _u(0x00000008)
72 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB    _u(3)
73 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB    _u(3)
74 #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
75 // -----------------------------------------------------------------------------
76 // Field       : PADS_QSPI_GPIO_QSPI_SCLK_PDE
77 // Description : Pull down enable
78 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET  _u(0x1)
79 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS   _u(0x00000004)
80 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB    _u(2)
81 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB    _u(2)
82 #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
83 // -----------------------------------------------------------------------------
84 // Field       : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
85 // Description : Enable schmitt trigger
86 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET  _u(0x1)
87 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS   _u(0x00000002)
88 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB    _u(1)
89 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB    _u(1)
90 #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
91 // -----------------------------------------------------------------------------
92 // Field       : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
93 // Description : Slew rate control. 1 = Fast, 0 = Slow
94 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET  _u(0x0)
95 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS   _u(0x00000001)
96 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB    _u(0)
97 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB    _u(0)
98 #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
99 // =============================================================================
100 // Register    : PADS_QSPI_GPIO_QSPI_SD0
101 // Description : Pad control register
102 #define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
103 #define PADS_QSPI_GPIO_QSPI_SD0_BITS   _u(0x000000ff)
104 #define PADS_QSPI_GPIO_QSPI_SD0_RESET  _u(0x00000052)
105 // -----------------------------------------------------------------------------
106 // Field       : PADS_QSPI_GPIO_QSPI_SD0_OD
107 // Description : Output disable. Has priority over output enable from
108 //               peripherals
109 #define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET  _u(0x0)
110 #define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS   _u(0x00000080)
111 #define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB    _u(7)
112 #define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB    _u(7)
113 #define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
114 // -----------------------------------------------------------------------------
115 // Field       : PADS_QSPI_GPIO_QSPI_SD0_IE
116 // Description : Input enable
117 #define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET  _u(0x1)
118 #define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS   _u(0x00000040)
119 #define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB    _u(6)
120 #define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB    _u(6)
121 #define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
122 // -----------------------------------------------------------------------------
123 // Field       : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
124 // Description : Drive strength.
125 //               0x0 -> 2mA
126 //               0x1 -> 4mA
127 //               0x2 -> 8mA
128 //               0x3 -> 12mA
129 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET  _u(0x1)
130 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS   _u(0x00000030)
131 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB    _u(5)
132 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB    _u(4)
133 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
134 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
135 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
136 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
137 #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
138 // -----------------------------------------------------------------------------
139 // Field       : PADS_QSPI_GPIO_QSPI_SD0_PUE
140 // Description : Pull up enable
141 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET  _u(0x0)
142 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS   _u(0x00000008)
143 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB    _u(3)
144 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB    _u(3)
145 #define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
146 // -----------------------------------------------------------------------------
147 // Field       : PADS_QSPI_GPIO_QSPI_SD0_PDE
148 // Description : Pull down enable
149 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET  _u(0x0)
150 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS   _u(0x00000004)
151 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB    _u(2)
152 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB    _u(2)
153 #define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
154 // -----------------------------------------------------------------------------
155 // Field       : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
156 // Description : Enable schmitt trigger
157 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET  _u(0x1)
158 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS   _u(0x00000002)
159 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB    _u(1)
160 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB    _u(1)
161 #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
162 // -----------------------------------------------------------------------------
163 // Field       : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
164 // Description : Slew rate control. 1 = Fast, 0 = Slow
165 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET  _u(0x0)
166 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS   _u(0x00000001)
167 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB    _u(0)
168 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB    _u(0)
169 #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
170 // =============================================================================
171 // Register    : PADS_QSPI_GPIO_QSPI_SD1
172 // Description : Pad control register
173 #define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
174 #define PADS_QSPI_GPIO_QSPI_SD1_BITS   _u(0x000000ff)
175 #define PADS_QSPI_GPIO_QSPI_SD1_RESET  _u(0x00000052)
176 // -----------------------------------------------------------------------------
177 // Field       : PADS_QSPI_GPIO_QSPI_SD1_OD
178 // Description : Output disable. Has priority over output enable from
179 //               peripherals
180 #define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET  _u(0x0)
181 #define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS   _u(0x00000080)
182 #define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB    _u(7)
183 #define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB    _u(7)
184 #define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
185 // -----------------------------------------------------------------------------
186 // Field       : PADS_QSPI_GPIO_QSPI_SD1_IE
187 // Description : Input enable
188 #define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET  _u(0x1)
189 #define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS   _u(0x00000040)
190 #define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB    _u(6)
191 #define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB    _u(6)
192 #define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
193 // -----------------------------------------------------------------------------
194 // Field       : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
195 // Description : Drive strength.
196 //               0x0 -> 2mA
197 //               0x1 -> 4mA
198 //               0x2 -> 8mA
199 //               0x3 -> 12mA
200 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET  _u(0x1)
201 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS   _u(0x00000030)
202 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB    _u(5)
203 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB    _u(4)
204 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
205 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
206 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
207 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
208 #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
209 // -----------------------------------------------------------------------------
210 // Field       : PADS_QSPI_GPIO_QSPI_SD1_PUE
211 // Description : Pull up enable
212 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET  _u(0x0)
213 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS   _u(0x00000008)
214 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB    _u(3)
215 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB    _u(3)
216 #define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
217 // -----------------------------------------------------------------------------
218 // Field       : PADS_QSPI_GPIO_QSPI_SD1_PDE
219 // Description : Pull down enable
220 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET  _u(0x0)
221 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS   _u(0x00000004)
222 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB    _u(2)
223 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB    _u(2)
224 #define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
225 // -----------------------------------------------------------------------------
226 // Field       : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
227 // Description : Enable schmitt trigger
228 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET  _u(0x1)
229 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS   _u(0x00000002)
230 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB    _u(1)
231 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB    _u(1)
232 #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
233 // -----------------------------------------------------------------------------
234 // Field       : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
235 // Description : Slew rate control. 1 = Fast, 0 = Slow
236 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET  _u(0x0)
237 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS   _u(0x00000001)
238 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB    _u(0)
239 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB    _u(0)
240 #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
241 // =============================================================================
242 // Register    : PADS_QSPI_GPIO_QSPI_SD2
243 // Description : Pad control register
244 #define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
245 #define PADS_QSPI_GPIO_QSPI_SD2_BITS   _u(0x000000ff)
246 #define PADS_QSPI_GPIO_QSPI_SD2_RESET  _u(0x00000052)
247 // -----------------------------------------------------------------------------
248 // Field       : PADS_QSPI_GPIO_QSPI_SD2_OD
249 // Description : Output disable. Has priority over output enable from
250 //               peripherals
251 #define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET  _u(0x0)
252 #define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS   _u(0x00000080)
253 #define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB    _u(7)
254 #define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB    _u(7)
255 #define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
256 // -----------------------------------------------------------------------------
257 // Field       : PADS_QSPI_GPIO_QSPI_SD2_IE
258 // Description : Input enable
259 #define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET  _u(0x1)
260 #define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS   _u(0x00000040)
261 #define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB    _u(6)
262 #define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB    _u(6)
263 #define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
264 // -----------------------------------------------------------------------------
265 // Field       : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
266 // Description : Drive strength.
267 //               0x0 -> 2mA
268 //               0x1 -> 4mA
269 //               0x2 -> 8mA
270 //               0x3 -> 12mA
271 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET  _u(0x1)
272 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS   _u(0x00000030)
273 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB    _u(5)
274 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB    _u(4)
275 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
276 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
277 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
278 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
279 #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
280 // -----------------------------------------------------------------------------
281 // Field       : PADS_QSPI_GPIO_QSPI_SD2_PUE
282 // Description : Pull up enable
283 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET  _u(0x0)
284 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS   _u(0x00000008)
285 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB    _u(3)
286 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB    _u(3)
287 #define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
288 // -----------------------------------------------------------------------------
289 // Field       : PADS_QSPI_GPIO_QSPI_SD2_PDE
290 // Description : Pull down enable
291 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET  _u(0x0)
292 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS   _u(0x00000004)
293 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB    _u(2)
294 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB    _u(2)
295 #define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
296 // -----------------------------------------------------------------------------
297 // Field       : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
298 // Description : Enable schmitt trigger
299 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET  _u(0x1)
300 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS   _u(0x00000002)
301 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB    _u(1)
302 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB    _u(1)
303 #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
304 // -----------------------------------------------------------------------------
305 // Field       : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
306 // Description : Slew rate control. 1 = Fast, 0 = Slow
307 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET  _u(0x0)
308 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS   _u(0x00000001)
309 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB    _u(0)
310 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB    _u(0)
311 #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
312 // =============================================================================
313 // Register    : PADS_QSPI_GPIO_QSPI_SD3
314 // Description : Pad control register
315 #define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
316 #define PADS_QSPI_GPIO_QSPI_SD3_BITS   _u(0x000000ff)
317 #define PADS_QSPI_GPIO_QSPI_SD3_RESET  _u(0x00000052)
318 // -----------------------------------------------------------------------------
319 // Field       : PADS_QSPI_GPIO_QSPI_SD3_OD
320 // Description : Output disable. Has priority over output enable from
321 //               peripherals
322 #define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET  _u(0x0)
323 #define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS   _u(0x00000080)
324 #define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB    _u(7)
325 #define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB    _u(7)
326 #define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
327 // -----------------------------------------------------------------------------
328 // Field       : PADS_QSPI_GPIO_QSPI_SD3_IE
329 // Description : Input enable
330 #define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET  _u(0x1)
331 #define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS   _u(0x00000040)
332 #define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB    _u(6)
333 #define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB    _u(6)
334 #define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
335 // -----------------------------------------------------------------------------
336 // Field       : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
337 // Description : Drive strength.
338 //               0x0 -> 2mA
339 //               0x1 -> 4mA
340 //               0x2 -> 8mA
341 //               0x3 -> 12mA
342 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET  _u(0x1)
343 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS   _u(0x00000030)
344 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB    _u(5)
345 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB    _u(4)
346 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
347 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
348 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
349 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
350 #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
351 // -----------------------------------------------------------------------------
352 // Field       : PADS_QSPI_GPIO_QSPI_SD3_PUE
353 // Description : Pull up enable
354 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET  _u(0x0)
355 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS   _u(0x00000008)
356 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB    _u(3)
357 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB    _u(3)
358 #define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
359 // -----------------------------------------------------------------------------
360 // Field       : PADS_QSPI_GPIO_QSPI_SD3_PDE
361 // Description : Pull down enable
362 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET  _u(0x0)
363 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS   _u(0x00000004)
364 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB    _u(2)
365 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB    _u(2)
366 #define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
367 // -----------------------------------------------------------------------------
368 // Field       : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
369 // Description : Enable schmitt trigger
370 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET  _u(0x1)
371 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS   _u(0x00000002)
372 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB    _u(1)
373 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB    _u(1)
374 #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
375 // -----------------------------------------------------------------------------
376 // Field       : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
377 // Description : Slew rate control. 1 = Fast, 0 = Slow
378 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET  _u(0x0)
379 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS   _u(0x00000001)
380 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB    _u(0)
381 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB    _u(0)
382 #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
383 // =============================================================================
384 // Register    : PADS_QSPI_GPIO_QSPI_SS
385 // Description : Pad control register
386 #define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
387 #define PADS_QSPI_GPIO_QSPI_SS_BITS   _u(0x000000ff)
388 #define PADS_QSPI_GPIO_QSPI_SS_RESET  _u(0x0000005a)
389 // -----------------------------------------------------------------------------
390 // Field       : PADS_QSPI_GPIO_QSPI_SS_OD
391 // Description : Output disable. Has priority over output enable from
392 //               peripherals
393 #define PADS_QSPI_GPIO_QSPI_SS_OD_RESET  _u(0x0)
394 #define PADS_QSPI_GPIO_QSPI_SS_OD_BITS   _u(0x00000080)
395 #define PADS_QSPI_GPIO_QSPI_SS_OD_MSB    _u(7)
396 #define PADS_QSPI_GPIO_QSPI_SS_OD_LSB    _u(7)
397 #define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
398 // -----------------------------------------------------------------------------
399 // Field       : PADS_QSPI_GPIO_QSPI_SS_IE
400 // Description : Input enable
401 #define PADS_QSPI_GPIO_QSPI_SS_IE_RESET  _u(0x1)
402 #define PADS_QSPI_GPIO_QSPI_SS_IE_BITS   _u(0x00000040)
403 #define PADS_QSPI_GPIO_QSPI_SS_IE_MSB    _u(6)
404 #define PADS_QSPI_GPIO_QSPI_SS_IE_LSB    _u(6)
405 #define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
406 // -----------------------------------------------------------------------------
407 // Field       : PADS_QSPI_GPIO_QSPI_SS_DRIVE
408 // Description : Drive strength.
409 //               0x0 -> 2mA
410 //               0x1 -> 4mA
411 //               0x2 -> 8mA
412 //               0x3 -> 12mA
413 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET  _u(0x1)
414 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS   _u(0x00000030)
415 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB    _u(5)
416 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB    _u(4)
417 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
418 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
419 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
420 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
421 #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
422 // -----------------------------------------------------------------------------
423 // Field       : PADS_QSPI_GPIO_QSPI_SS_PUE
424 // Description : Pull up enable
425 #define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET  _u(0x1)
426 #define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS   _u(0x00000008)
427 #define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB    _u(3)
428 #define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB    _u(3)
429 #define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
430 // -----------------------------------------------------------------------------
431 // Field       : PADS_QSPI_GPIO_QSPI_SS_PDE
432 // Description : Pull down enable
433 #define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET  _u(0x0)
434 #define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS   _u(0x00000004)
435 #define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB    _u(2)
436 #define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB    _u(2)
437 #define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
438 // -----------------------------------------------------------------------------
439 // Field       : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
440 // Description : Enable schmitt trigger
441 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET  _u(0x1)
442 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS   _u(0x00000002)
443 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB    _u(1)
444 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB    _u(1)
445 #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
446 // -----------------------------------------------------------------------------
447 // Field       : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
448 // Description : Slew rate control. 1 = Fast, 0 = Slow
449 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET  _u(0x0)
450 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS   _u(0x00000001)
451 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB    _u(0)
452 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB    _u(0)
453 #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
454 // =============================================================================
455 #endif // _HARDWARE_REGS_PADS_QSPI_H
456 
457