1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /*
4  * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef _HARDWARE_STRUCTS_DMA_H
10 #define _HARDWARE_STRUCTS_DMA_H
11 
12 #include "hardware/address_mapped.h"
13 #include "hardware/regs/dma.h"
14 
15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
16 //
17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18 // _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
19 //
20 // Bit-field descriptions are of the form:
21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22 
23 typedef struct {
24     _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
25     // DMA Channel 0 Read Address pointer
26     io_rw_32 read_addr;
27 
28     _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
29     // DMA Channel 0 Write Address pointer
30     io_rw_32 write_addr;
31 
32     _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
33     // DMA Channel 0 Transfer Count
34     io_rw_32 transfer_count;
35 
36     _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
37     // DMA Channel 0 Control and Status
38     // 0x80000000 [31]    : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags
39     // 0x40000000 [30]    : READ_ERROR (0): If 1, the channel received a read bus error
40     // 0x20000000 [29]    : WRITE_ERROR (0): If 1, the channel received a write bus error
41     // 0x01000000 [24]    : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the...
42     // 0x00800000 [23]    : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each...
43     // 0x00400000 [22]    : BSWAP (0): Apply byte-swap transformation to DMA data
44     // 0x00200000 [21]    : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block
45     // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal
46     // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO
47     // 0x00000400 [10]    : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses
48     // 0x000003c0 [9:6]   : RING_SIZE (0): Size of address wrap region
49     // 0x00000020 [5]     : INCR_WRITE (0): If 1, the write address increments with each transfer
50     // 0x00000010 [4]     : INCR_READ (0): If 1, the read address increments with each transfer
51     // 0x0000000c [3:2]   : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word)
52     // 0x00000002 [1]     : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in...
53     // 0x00000001 [0]     : EN (0): DMA Channel Enable
54     io_rw_32 ctrl_trig;
55 
56     _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
57     // Alias for channel 0 CTRL register
58     io_rw_32 al1_ctrl;
59 
60     _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
61     // Alias for channel 0 READ_ADDR register
62     io_rw_32 al1_read_addr;
63 
64     _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
65     // Alias for channel 0 WRITE_ADDR register
66     io_rw_32 al1_write_addr;
67 
68     _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
69     // Alias for channel 0 TRANS_COUNT register
70     io_rw_32 al1_transfer_count_trig;
71 
72     _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
73     // Alias for channel 0 CTRL register
74     io_rw_32 al2_ctrl;
75 
76     _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
77     // Alias for channel 0 TRANS_COUNT register
78     io_rw_32 al2_transfer_count;
79 
80     _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
81     // Alias for channel 0 READ_ADDR register
82     io_rw_32 al2_read_addr;
83 
84     _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
85     // Alias for channel 0 WRITE_ADDR register
86     io_rw_32 al2_write_addr_trig;
87 
88     _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
89     // Alias for channel 0 CTRL register
90     io_rw_32 al3_ctrl;
91 
92     _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
93     // Alias for channel 0 WRITE_ADDR register
94     io_rw_32 al3_write_addr;
95 
96     _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
97     // Alias for channel 0 TRANS_COUNT register
98     io_rw_32 al3_transfer_count;
99 
100     _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
101     // Alias for channel 0 READ_ADDR register
102     io_rw_32 al3_read_addr_trig;
103 } dma_channel_hw_t;
104 
105 typedef struct {
106     dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12
107 
108     uint32_t _pad0[64];
109 
110     _REG_(DMA_INTR_OFFSET) // DMA_INTR
111     // Interrupt Status (raw)
112     // 0x0000ffff [15:0]  : INTR (0): Raw interrupt status for DMA Channels 0
113     io_rw_32 intr;
114 
115     _REG_(DMA_INTE0_OFFSET) // DMA_INTE0
116     // Interrupt Enables for IRQ 0
117     // 0x0000ffff [15:0]  : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0
118     io_rw_32 inte0;
119 
120     _REG_(DMA_INTF0_OFFSET) // DMA_INTF0
121     // Force Interrupts
122     // 0x0000ffff [15:0]  : INTF0 (0): Write 1s to force the corresponding bits in INTE0
123     io_rw_32 intf0;
124 
125     _REG_(DMA_INTS0_OFFSET) // DMA_INTS0
126     // Interrupt Status for IRQ 0
127     // 0x0000ffff [15:0]  : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted
128     io_rw_32 ints0;
129 
130     uint32_t _pad1;
131 
132     _REG_(DMA_INTE1_OFFSET) // DMA_INTE1
133     // Interrupt Enables for IRQ 1
134     // 0x0000ffff [15:0]  : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1
135     io_rw_32 inte1;
136 
137     _REG_(DMA_INTF1_OFFSET) // DMA_INTF1
138     // Force Interrupts for IRQ 1
139     // 0x0000ffff [15:0]  : INTF1 (0): Write 1s to force the corresponding bits in INTE0
140     io_rw_32 intf1;
141 
142     _REG_(DMA_INTS1_OFFSET) // DMA_INTS1
143     // Interrupt Status (masked) for IRQ 1
144     // 0x0000ffff [15:0]  : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted
145     io_rw_32 ints1;
146 
147     _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
148     // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
149     //
150     // Pacing (X/Y) Fractional Timer
151     // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend
152     // 0x0000ffff [15:0]  : Y (0): Pacing Timer Divisor
153     io_rw_32 timer[NUM_DMA_TIMERS]; // 4
154 
155     _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
156     // Trigger one or more channels simultaneously
157     // 0x0000ffff [15:0]  : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel
158     io_rw_32 multi_channel_trigger;
159 
160     _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
161     // Sniffer Control
162     // 0x00000800 [11]    : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read
163     // 0x00000400 [10]    : OUT_REV (0): If set, the result appears bit-reversed when read
164     // 0x00000200 [9]     : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum
165     // 0x000001e0 [8:5]   : CALC (0)
166     // 0x0000001e [4:1]   : DMACH (0): DMA channel for Sniffer to observe
167     // 0x00000001 [0]     : EN (0): Enable sniffer
168     io_rw_32 sniff_ctrl;
169 
170     _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
171     // Data accumulator for sniff hardware
172     io_rw_32 sniff_data;
173 
174     uint32_t _pad2;
175 
176     _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
177     // Debug RAF, WAF, TDF levels
178     // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level
179     // 0x0000ff00 [15:8]  : WAF_LVL (0): Current Write-Address-FIFO fill level
180     // 0x000000ff [7:0]   : TDF_LVL (0): Current Transfer-Data-FIFO fill level
181     io_ro_32 fifo_levels;
182 
183     _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
184     // Abort an in-progress transfer sequence on one or more channels
185     // 0x0000ffff [15:0]  : CHAN_ABORT (0): Each bit corresponds to a channel
186     io_rw_32 abort;
187 } dma_hw_t;
188 
189 typedef struct {
190     struct dma_debug_hw_channel {
191         io_rw_32 ctrdeq;
192         io_ro_32 tcr;
193         uint32_t pad[14];
194     } ch[NUM_DMA_CHANNELS];
195 } dma_debug_hw_t;
196 
197 #define dma_hw ((dma_hw_t *)DMA_BASE)
198 #define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
199 
200 static_assert( NUM_DMA_TIMERS == 4, "");
201 static_assert( NUM_DMA_CHANNELS == 12, "");
202 
203 #endif
204