1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef BSP_IRQ_H
8 #define BSP_IRQ_H
9
10 /***********************************************************************************************************************
11 * Includes <System Includes> , "Project Includes"
12 **********************************************************************************************************************/
13
14 #include "fsp_features.h"
15 #include <zephyr/drivers/interrupt_controller/gic.h>
16 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
17
18 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
19 FSP_HEADER
20
21 /***********************************************************************************************************************
22 * Macro definitions
23 **********************************************************************************************************************/
24 #define BSP_IRQ_GPT_EVENT_NUM_BASE ((IRQn_Type) ELC_EVENT_GPT00_0_INT0) // IRQ number of GPT_INT00_0.
25 #define BSP_IRQ_GPT_INT_NUM_MAX (5U) // Total size from GPT_INT0 to GPT_INT4.
26 #define BSP_IRQ_GPT_REGISTER_DIVISION (2U) // Divide GPT channel number.
27 #define BSP_IRQ_GPT_IY_SHIFT_NUM (16U) // Upper bits shift of GPT_INTSELn.
28 #define BSP_IRQ_GPT_IX_SHIFT_NUM (0U) // Low bits shift of GPT_INTSELn.
29
30 #define BSP_IRQ_GPT_SELECTED_INTERVAL (4U) // Bit interval of GPT_INTSELn.
31 #define BSP_IRQ_GPT_SELECTED_EVENT_MASK (0xFU) // Bits mask of GPT_INTSELn.
32
33 #define BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP (32) // 32bit state bit per GPT_INTSTATn and so on.
34 #define BSP_IRQ_GPT_COMBINED_GROUP_NUM (28) // NS_GPT_INTSTAT0 to 25 and S_GPT_INTSTAT0 to 1.
35 #define BSP_IRQ_GPT_COMBINED_EVENT_MASK (0x1U) // Bit mask of GPT_INTMSKn
36 #define BSP_IRQ_GPT_COMBINED_EVENT_ENUM_MASK (0xFU) // Bit mask of bsp_irq_gpt_combined_event_t
37 #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES)
38
39 /***********************************************************************************************************************
40 * Typedef definitions
41 **********************************************************************************************************************/
42
43 #ifndef BSP_OVERRIDE_BSP_IRQ_GPT_SELECTED_EVENT_T
44
45 /** GPT selected interrupt event */
46 typedef enum e_bsp_irq_gpt_selected_event
47 {
48 BSP_IRQ_GPT_SELECTED_EVENT_GPT_CCMPA = 0x0, ///< GPT_CCMPA event source
49 BSP_IRQ_GPT_SELECTED_EVENT_GPT_CCMPB = 0x1, ///< GPT_CCMPB event source
50 BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPC = 0x2, ///< GPT_CMPC event source
51 BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPD = 0x3, ///< GPT_CMPD event source
52 BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPE = 0x4, ///< GPT_CMPE event source
53 BSP_IRQ_GPT_SELECTED_EVENT_GPT_CMPF = 0x5, ///< GPT_CMPF event source
54 BSP_IRQ_GPT_SELECTED_EVENT_GPT_OVF = 0x6, ///< GPT_OVF event source
55 BSP_IRQ_GPT_SELECTED_EVENT_GPT_UDF = 0x7, ///< GPT_UDF event source
56 BSP_IRQ_GPT_SELECTED_EVENT_GPT_DTE = 0x8, ///< GPT_DTE event source
57 BSP_IRQ_GPT_SELECTED_EVENT_TGIA0 = 0x9, ///< MTU3 TGIA0 event source
58 BSP_IRQ_GPT_SELECTED_EVENT_TGIB0 = 0xA, ///< MTU3 TGIB0 event source
59 BSP_IRQ_GPT_SELECTED_EVENT_TGIC0 = 0xB, ///< MTU3 TGIC0 event source
60 BSP_IRQ_GPT_SELECTED_EVENT_TGID0 = 0xC, ///< MTU3 TGID0 event source
61 BSP_IRQ_GPT_SELECTED_EVENT_TCIV0 = 0xD, ///< MTU3 TCIV0 event source
62 BSP_IRQ_GPT_SELECTED_EVENT_TGIE0 = 0x9, ///< MTU3 TGIE0 event source
63 BSP_IRQ_GPT_SELECTED_EVENT_TGIF0 = 0xA, ///< MTU3 TGIF0 event source
64 BSP_IRQ_GPT_SELECTED_EVENT_TGIA1 = 0xB, ///< MTU3 TGIA1 event source
65 BSP_IRQ_GPT_SELECTED_EVENT_TGIB1 = 0xC, ///< MTU3 TGIB1 event source
66 BSP_IRQ_GPT_SELECTED_EVENT_TCIV1 = 0xD, ///< MTU3 TCIV1 event source
67 BSP_IRQ_GPT_SELECTED_EVENT_TCIU1 = 0x9, ///< MTU3 TCIU1 event source
68 BSP_IRQ_GPT_SELECTED_EVENT_TGIA2 = 0xA, ///< MTU3 TGIA2 event source
69 BSP_IRQ_GPT_SELECTED_EVENT_TGIB2 = 0xB, ///< MTU3 TGIB2 event source
70 BSP_IRQ_GPT_SELECTED_EVENT_TCIV2 = 0xC, ///< MTU3 TCIV2 event source
71 BSP_IRQ_GPT_SELECTED_EVENT_TCIU2 = 0xD, ///< MTU3 TCIU2 event source
72 BSP_IRQ_GPT_SELECTED_EVENT_TGIA3 = 0x9, ///< MTU3 TGIA3 event source
73 BSP_IRQ_GPT_SELECTED_EVENT_TGIB3 = 0xA, ///< MTU3 TGIB3 event source
74 BSP_IRQ_GPT_SELECTED_EVENT_TGIC3 = 0xB, ///< MTU3 TGIC3 event source
75 BSP_IRQ_GPT_SELECTED_EVENT_TGID3 = 0xC, ///< MTU3 TGID3 event source
76 BSP_IRQ_GPT_SELECTED_EVENT_TCIV3 = 0xD, ///< MTU3 TCIV3 event source
77 BSP_IRQ_GPT_SELECTED_EVENT_TGIA4 = 0x9, ///< MTU3 TGIA4 event source
78 BSP_IRQ_GPT_SELECTED_EVENT_TGIB4 = 0xA, ///< MTU3 TGIB4 event source
79 BSP_IRQ_GPT_SELECTED_EVENT_TGIC4 = 0xB, ///< MTU3 TGIC4 event source
80 BSP_IRQ_GPT_SELECTED_EVENT_TGID4 = 0xC, ///< MTU3 TGID4 event source
81 BSP_IRQ_GPT_SELECTED_EVENT_TCIV4 = 0xD, ///< MTU3 TCIV4 event source
82 BSP_IRQ_GPT_SELECTED_EVENT_TCIU5 = 0x9, ///< MTU3 TCIU5 event source
83 BSP_IRQ_GPT_SELECTED_EVENT_TCIV5 = 0xA, ///< MTU3 TCIV5 event source
84 BSP_IRQ_GPT_SELECTED_EVENT_TGIW5 = 0xB, ///< MTU3 TGIW5 event source
85 BSP_IRQ_GPT_SELECTED_EVENT_TGIA6 = 0x9, ///< MTU3 TGIA6 event source
86 BSP_IRQ_GPT_SELECTED_EVENT_TGIB6 = 0xA, ///< MTU3 TGIB6 event source
87 BSP_IRQ_GPT_SELECTED_EVENT_TGIC6 = 0xB, ///< MTU3 TGIC6 event source
88 BSP_IRQ_GPT_SELECTED_EVENT_TGID6 = 0xC, ///< MTU3 TGID6 event source
89 BSP_IRQ_GPT_SELECTED_EVENT_TCIV6 = 0xD, ///< MTU3 TCIV6 event source
90 BSP_IRQ_GPT_SELECTED_EVENT_TGIA7 = 0x9, ///< MTU3 TGIA7 event source
91 BSP_IRQ_GPT_SELECTED_EVENT_TGIB7 = 0xA, ///< MTU3 TGIB7 event source
92 BSP_IRQ_GPT_SELECTED_EVENT_TGIC7 = 0xB, ///< MTU3 TGIC7 event source
93 BSP_IRQ_GPT_SELECTED_EVENT_TGID7 = 0xC, ///< MTU3 TGID7 event source
94 BSP_IRQ_GPT_SELECTED_EVENT_TCIV7 = 0xD, ///< MTU3 TCIV7 event source
95 BSP_IRQ_GPT_SELECTED_EVENT_TGIA8 = 0x9, ///< MTU3 TGIA8 event source
96 BSP_IRQ_GPT_SELECTED_EVENT_TGIB8 = 0xA, ///< MTU3 TGIB8 event source
97 BSP_IRQ_GPT_SELECTED_EVENT_TGIC8 = 0xB, ///< MTU3 TGIC8 event source
98 BSP_IRQ_GPT_SELECTED_EVENT_TGID8 = 0xC, ///< MTU3 TGID8 event source
99 BSP_IRQ_GPT_SELECTED_EVENT_TCIV8 = 0xD, ///< MTU3 TCIV8 event source
100 } bsp_irq_gpt_selected_event_t;
101
102 #endif
103
104 #ifndef BSP_OVERRIDE_BSP_IRQ_GPT_COMBINED_EVENT_T
105
106 /** GPT combined interrupt event */
107 typedef enum e_bsp_irq_gpt_combined_event
108 {
109 BSP_IRQ_GPT_COMBINED_EVENT_GPT_CCMPA = 0x0, ///< GPT_CCMPA event source
110 BSP_IRQ_GPT_COMBINED_EVENT_GPT_CCMPB = 0x1, ///< GPT_CCMPB event source
111 BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPC = 0x2, ///< GPT_CMPC event source
112 BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPD = 0x3, ///< GPT_CMPD event source
113 BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPE = 0x4, ///< GPT_CMPE event source
114 BSP_IRQ_GPT_COMBINED_EVENT_GPT_CMPF = 0x5, ///< GPT_CMPF event source
115 BSP_IRQ_GPT_COMBINED_EVENT_GPT_OVF = 0x6, ///< GPT_OVF event source
116 BSP_IRQ_GPT_COMBINED_EVENT_GPT_UDF = 0x7, ///< GPT_UDF event source
117 BSP_IRQ_GPT_COMBINED_EVENT_GPT_DTE = 0x8, ///< GPT_DTE event source
118 BSP_IRQ_GPT_COMBINED_EVENT_MTU3_0 = 0x9, ///< MTU3 event source 0
119 BSP_IRQ_GPT_COMBINED_EVENT_MTU3_1 = 0xA, ///< MTU3 event source 1
120 BSP_IRQ_GPT_COMBINED_EVENT_MTU3_2 = 0xB, ///< MTU3 event source 2
121 BSP_IRQ_GPT_COMBINED_EVENT_MTU3_3 = 0xC, ///< MTU3 event source 3
122 BSP_IRQ_GPT_COMBINED_EVENT_MTU3_4 = 0xD, ///< MTU3 event source 4
123 BSP_IRQ_GPT_COMBINED_EVENT_RESERVED1 = 0xE, ///< Reserved bit
124 BSP_IRQ_GPT_COMBINED_EVENT_RESERVED2 = 0xF, ///< Reserved bit
125 } bsp_irq_gpt_combined_event_t;
126
127 #endif
128
129 /***********************************************************************************************************************
130 * Exported global variables
131 **********************************************************************************************************************/
132 extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
133 extern void ** gp_bsp_gpt_combined_ctrl_table[BSP_IRQ_GPT_COMBINED_GROUP_NUM];
134 extern fsp_vector_t * gp_bsp_gpt_combined_isr_table[BSP_IRQ_GPT_COMBINED_GROUP_NUM];
135
136 /***********************************************************************************************************************
137 * Exported global functions (to be accessed by other files)
138 **********************************************************************************************************************/
139 #if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
140 uint32_t bsp_prv_irq_gpt_channel_get(IRQn_Type irq);
141 uint32_t bsp_prv_irq_gpt_reg_num_get(uint32_t channel);
142 uint32_t bsp_prv_irq_gpt_selected_shift_num_get(IRQn_Type irq, uint32_t channel);
143 uint32_t bsp_prv_irq_gpt_combined_shift_num_get(uint32_t channel, bsp_irq_gpt_combined_event_t event_source);
144 void * bsp_prv_irq_gpt_combined_ctrl_table_allocate(uint32_t groupIndex);
145 void * bsp_prv_irq_gpt_combined_isr_table_allocate(uint32_t groupIndex);
146 bool bsp_prv_irq_gpt_combined_table_status_get(uintptr_t * p_table, uint32_t size);
147 uint32_t bsp_prv_irq_gpt_combined_table_num_get(uint32_t channel);
148 void bsp_irq_gpt_combined_interrupt_handler(void);
149
150 #endif
151
152 /***********************************************************************************************************************
153 * Inline Functions
154 **********************************************************************************************************************/
155
156 /*******************************************************************************************************************//**
157 * @addtogroup BSP_MCU
158 * @{
159 **********************************************************************************************************************/
160
161 /*******************************************************************************************************************//**
162 * @brief Sets the ISR context associated with the requested IRQ.
163 *
164 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
165 * function.
166 * @param[in] p_context ISR context for IRQ.
167 **********************************************************************************************************************/
R_FSP_IsrContextSet(IRQn_Type const irq,void * p_context)168 __STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
169 {
170 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
171 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
172 gp_renesas_isr_context[irq] = p_context;
173 }
174
175 /*******************************************************************************************************************//**
176 * Clear the GIC pending interrupt.
177 *
178 * @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are
179 * only those for the Cortex Processor Exceptions Numbers.
180 **********************************************************************************************************************/
R_BSP_IrqClearPending(IRQn_Type irq)181 __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
182 {
183 /* Call GIC APIs provided by Zephyr */
184 arm_gic_irq_clear_pending((unsigned int)irq);
185 }
186
187 /*******************************************************************************************************************//**
188 * Get the GIC pending interrupt.
189 *
190 * @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are
191 * only those for the Cortex Processor Exceptions Numbers.
192 *
193 * @return Value indicating the status of the level interrupt.
194 **********************************************************************************************************************/
R_BSP_IrqPendingGet(IRQn_Type irq)195 __STATIC_INLINE uint32_t R_BSP_IrqPendingGet (IRQn_Type irq)
196 {
197 /* Call GIC APIs provided by Zephyr */
198 return arm_gic_irq_is_pending((unsigned int)irq);
199 }
200
201 /*******************************************************************************************************************//**
202 * Sets the interrupt priority and context.
203 *
204 * @param[in] irq The IRQ number to configure.
205 * @param[in] priority GIC priority of the interrupt
206 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
207 **********************************************************************************************************************/
R_BSP_IrqCfg(IRQn_Type const irq,uint32_t priority,void * p_context)208 __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
209 {
210 /* Priority is already set with gic initialization, remove priority config in FSP to prevent override seting on Zephyr */
211 FSP_PARAMETER_NOT_USED(priority);
212
213 /* Store the context. The context is recovered in the ISR. */
214 R_FSP_IsrContextSet(irq, p_context);
215 }
216
217 /*******************************************************************************************************************//**
218 * Enable the IRQ in the GIC (Without clearing the pending bit).
219 *
220 * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
221 * Cortex Processor Exceptions Numbers.
222 **********************************************************************************************************************/
R_BSP_IrqEnableNoClear(IRQn_Type const irq)223 __STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
224 {
225 /* Call GIC APIs provided by Zephyr */
226 arm_gic_irq_enable((unsigned int)irq);
227 }
228
229 /*******************************************************************************************************************//**
230 * Enable the IRQ in the GIC (With clearing the pending bit).
231 *
232 * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
233 * Cortex Processor Exceptions Numbers.
234 **********************************************************************************************************************/
R_BSP_IrqEnable(IRQn_Type const irq)235 __STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
236 {
237 /* Clear pending interrupts in the GIC. */
238 R_BSP_IrqClearPending(irq);
239
240 /* Enable the interrupt in the GIC. */
241 R_BSP_IrqEnableNoClear(irq);
242 }
243
244 /*******************************************************************************************************************//**
245 * Disables interrupts in the GIC.
246 *
247 * @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are
248 * only those for the Cortex Processor Exceptions Numbers.
249 **********************************************************************************************************************/
R_BSP_IrqDisable(IRQn_Type const irq)250 __STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
251 {
252 /* Call GIC APIs provided by Zephyr */
253 arm_gic_irq_disable((unsigned int)irq);
254 }
255
256 /*******************************************************************************************************************//**
257 * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
258 *
259 * @param[in] irq Interrupt number.
260 * @param[in] priority GIC priority of the interrupt
261 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
262 **********************************************************************************************************************/
R_BSP_IrqCfgEnable(IRQn_Type const irq,uint32_t priority,void * p_context)263 __STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
264 {
265 R_BSP_IrqCfg(irq, priority, p_context);
266 R_BSP_IrqEnable(irq);
267 }
268
269 /*******************************************************************************************************************//**
270 * @brief Finds the ISR context associated with the requested IRQ.
271 *
272 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
273 * function.
274 * @return ISR context for IRQ.
275 **********************************************************************************************************************/
R_FSP_IsrContextGet(IRQn_Type const irq)276 __STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
277 {
278 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
279 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
280 return gp_renesas_isr_context[irq];
281 }
282
283 /*******************************************************************************************************************//**
284 * Sets the interrupt detect type.
285 *
286 * @param[in] irq The IRQ number to configure.
287 * @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd).
288 **********************************************************************************************************************/
R_BSP_IrqDetectTypeSet(IRQn_Type const irq,uint32_t detect_type)289 __STATIC_INLINE void R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type)
290 {
291 uint32_t idx;
292 uint32_t shift;
293 uint32_t val;
294 uint8_t flags = detect_type ? IRQ_TYPE_EDGE : IRQ_TYPE_LEVEL;
295
296 /* Interrupt type config */
297 if (!GIC_IS_SGI(irq)) {
298 idx = irq / GIC_NUM_CFG_PER_REG;
299 shift = (irq & (GIC_NUM_CFG_PER_REG - 1)) * 2;
300
301 val = sys_read32(GICD_ICFGRn + idx * 4);
302 val &= ~(GICD_ICFGR_MASK << shift);
303 if (flags & IRQ_TYPE_EDGE) {
304 val |= (GICD_ICFGR_TYPE << shift);
305 }
306 sys_write32(val, GICD_ICFGRn + idx * 4);
307 }
308 }
309
310 /*******************************************************************************************************************//**
311 * Sets the interrupt Group.
312 *
313 * @param[in] irq The IRQ number to configure.
314 * @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ).
315 **********************************************************************************************************************/
R_BSP_IrqGroupSet(IRQn_Type const irq,uint32_t interrupt_group)316 __STATIC_INLINE void R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group)
317 {
318 /* Zephyr configures all interrupts in arm_gic_init */
319 ARG_UNUSED(irq);
320 ARG_UNUSED(interrupt_group);
321 }
322
323 /*******************************************************************************************************************//**
324 * Sets the interrupt mask level.
325 *
326 * @param[in] mask_level The interrupt mask level
327 **********************************************************************************************************************/
R_BSP_IrqMaskLevelSet(uint32_t mask_level)328 __STATIC_INLINE void R_BSP_IrqMaskLevelSet (uint32_t mask_level)
329 {
330 FSP_CRITICAL_SECTION_SET_STATE(mask_level << BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT);
331 }
332
333 /*******************************************************************************************************************//**
334 * Gets the interrupt mask level.
335 *
336 * @return Value indicating the interrupt mask level.
337 **********************************************************************************************************************/
R_BSP_IrqMaskLevelGet(void)338 __STATIC_INLINE uint32_t R_BSP_IrqMaskLevelGet (void)
339 {
340 return (uint32_t) ((FSP_CRITICAL_SECTION_GET_CURRENT_STATE() >> BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT) &
341 0x0000001FUL);
342 }
343
344 #if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED)
345
346 /*******************************************************************************************************************//**
347 * Manipulate GPT_INTSELn and specify the GPT/MTU3 interrupt source as GPT_INT0-3.
348 *
349 * @param[in] irq IRQ number
350 * @param[in] event_source Define the INTSEL bit value of GPT_INTSELn as an enum
351 **********************************************************************************************************************/
R_BSP_IrqGptSelectedSet(IRQn_Type irq,bsp_irq_gpt_selected_event_t event_source)352 __STATIC_INLINE void R_BSP_IrqGptSelectedSet (IRQn_Type irq, bsp_irq_gpt_selected_event_t event_source)
353 {
354 if (irq >= BSP_IRQ_GPT_EVENT_NUM_BASE)
355 {
356 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
357 uint32_t reg_num = bsp_prv_irq_gpt_reg_num_get(channel);
358 uint32_t shift_num = bsp_prv_irq_gpt_selected_shift_num_get(irq, channel);
359
360 if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
361 {
362 R_ICU_NS->NS_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
363 R_ICU_NS->NS_GPT_INTSEL[reg_num] |= (uint32_t) event_source << shift_num;
364 }
365 else
366 {
367 R_ICU_S->S_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
368 R_ICU_S->S_GPT_INTSEL[reg_num] |= (uint32_t) event_source << shift_num;
369 }
370 }
371 }
372
373 /*******************************************************************************************************************//**
374 * Manipulate GPT_INTSELn to clear the GPT/MTU3 interrupt cause setting to 0.
375 *
376 * @param[in] irq IRQ number
377 **********************************************************************************************************************/
R_BSP_IrqGptSelectedClear(IRQn_Type irq)378 __STATIC_INLINE void R_BSP_IrqGptSelectedClear (IRQn_Type irq)
379 {
380 if (irq >= BSP_IRQ_GPT_EVENT_NUM_BASE)
381 {
382 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
383 uint32_t reg_num = bsp_prv_irq_gpt_reg_num_get(channel);
384 uint32_t shift_num = bsp_prv_irq_gpt_selected_shift_num_get(irq, channel);
385
386 if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
387 {
388 R_ICU_NS->NS_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
389 }
390 else
391 {
392 R_ICU_S->S_GPT_INTSEL[reg_num] &= ~(BSP_IRQ_GPT_SELECTED_EVENT_MASK << shift_num);
393 }
394 }
395 }
396
397 /*******************************************************************************************************************//**
398 * Registers pointer addresses for control structure and interrupt handler.
399 * If there is no management table, memory is allocated.
400 *
401 * @param[in] irq IRQ number
402 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
403 * @param[in] p_context Control structure
404 * @param[in] p_interrupt_handler Interrupt handler
405 *
406 * @note Function uses the malloc function to create management tables for "control structures" and
407 * "interrupt handlers". The management table is created in units of 1 group, with 2 channels of
408 * GPT/MTU3 as 1 group.
409 * The following memory is consumed for each group. The consumption can be calculated by
410 * "address size * number of elements * number of tables".
411 * 256 bytes for CR52 (=4*32*2)
412 * 512 bytes for CA55 (=8*32*2)
413 *
414 * @retval FSP_SUCCESS Successful.
415 * @retval FSP_ERR_NOT_INITIALIZED Memory allocation failed.
416 **********************************************************************************************************************/
R_BSP_IrqGptCombinedTableSet(IRQn_Type irq,bsp_irq_gpt_combined_event_t event_source,void * p_context,void (* p_interrupt_handler)(void))417 __STATIC_INLINE fsp_err_t R_BSP_IrqGptCombinedTableSet (IRQn_Type irq,
418 bsp_irq_gpt_combined_event_t event_source,
419 void * p_context,
420 void ( * p_interrupt_handler)(void))
421 {
422 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
423 uint32_t groupIndex = bsp_prv_irq_gpt_combined_table_num_get(channel);
424 uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
425 void * p_table;
426
427 /* If not exist 'groupIndex'th control structure table,
428 * allocate memory for 'groupIndex'th control structure table. */
429 if (NULL == gp_bsp_gpt_combined_ctrl_table[groupIndex])
430 {
431 p_table = bsp_prv_irq_gpt_combined_ctrl_table_allocate(groupIndex);
432 FSP_ERROR_RETURN(NULL != p_table, FSP_ERR_NOT_INITIALIZED);
433 }
434
435 /* If not exist 'groupIndex'th interrupt handler table,
436 * allocate memory for 'groupIndex'th interrupt handler table. */
437 if (NULL == gp_bsp_gpt_combined_isr_table[groupIndex])
438 {
439 p_table = bsp_prv_irq_gpt_combined_isr_table_allocate(groupIndex);
440 FSP_ERROR_RETURN(NULL != p_table, FSP_ERR_NOT_INITIALIZED);
441 }
442
443 /* Registers pointer addresses for control structure and interrupt handler. */
444 gp_bsp_gpt_combined_ctrl_table[groupIndex][elementIndex] = p_context;
445 gp_bsp_gpt_combined_isr_table[groupIndex][elementIndex] = p_interrupt_handler;
446
447 return FSP_SUCCESS;
448 }
449
450 /*******************************************************************************************************************//**
451 * Get pointer addresses for control structure.
452 *
453 * @param[in] irq IRQ number
454 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
455 *
456 * @return Pointer addresses for control structure.
457 **********************************************************************************************************************/
R_BSP_IrqGptCombinedCtrlGet(IRQn_Type irq,bsp_irq_gpt_combined_event_t event_source)458 __STATIC_INLINE void * R_BSP_IrqGptCombinedCtrlGet (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
459 {
460 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
461 uint32_t groupIndex = bsp_prv_irq_gpt_combined_table_num_get(channel);
462 uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
463
464 return gp_bsp_gpt_combined_ctrl_table[groupIndex][elementIndex];
465 }
466
467 /*******************************************************************************************************************//**
468 * Get pointer addresses for interrupt handler.
469 *
470 * @param[in] irq IRQ number
471 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
472 *
473 * @return Pointer addresses for interrupt handler.
474 **********************************************************************************************************************/
R_BSP_IrqGptCombinedIsrGet(IRQn_Type irq,bsp_irq_gpt_combined_event_t event_source)475 __STATIC_INLINE fsp_vector_t R_BSP_IrqGptCombinedIsrGet (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
476 {
477 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
478 uint32_t groupIndex = bsp_prv_irq_gpt_combined_table_num_get(channel);
479 uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
480
481 return gp_bsp_gpt_combined_isr_table[groupIndex][elementIndex];
482 }
483
484 /*******************************************************************************************************************//**
485 * Releases pointer addresses for control structure and interrupt handler.
486 * If there are no more values to manage in the management table, memory is free.
487 *
488 * @param[in] irq IRQ number
489 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
490 **********************************************************************************************************************/
R_BSP_IrqGptCombinedTableClear(IRQn_Type irq,bsp_irq_gpt_combined_event_t event_source)491 __STATIC_INLINE void R_BSP_IrqGptCombinedTableClear (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
492 {
493 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
494 uint32_t groupIndex = bsp_prv_irq_gpt_combined_table_num_get(channel);
495 uint32_t elementIndex = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
496
497 gp_bsp_gpt_combined_ctrl_table[groupIndex][elementIndex] = NULL;
498 gp_bsp_gpt_combined_isr_table[groupIndex][elementIndex] = NULL;
499
500 uint32_t cnt;
501 for (cnt = 0; cnt < BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP; cnt++)
502 {
503 if (NULL != gp_bsp_gpt_combined_ctrl_table[groupIndex][cnt])
504 {
505 break;
506 }
507 }
508
509 if (BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP == cnt)
510 {
511 bsp_prv_free(gp_bsp_gpt_combined_ctrl_table[groupIndex]);
512 gp_bsp_gpt_combined_ctrl_table[groupIndex] = NULL;
513 }
514
515 for (cnt = 0; cnt < BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP; cnt++)
516 {
517 if (NULL != gp_bsp_gpt_combined_isr_table[groupIndex][cnt])
518 {
519 break;
520 }
521 }
522
523 if (BSP_IRQ_GPT_COMBINED_EVENT_NUM_PER_GROUP == cnt)
524 {
525 bsp_prv_free(gp_bsp_gpt_combined_ctrl_table[groupIndex]);
526 gp_bsp_gpt_combined_isr_table[groupIndex] = NULL;
527 }
528 }
529
530 /*******************************************************************************************************************//**
531 * Manipulate GPT_INTMSKn to mask GPT/MTU3 interrupts.
532 *
533 * @param[in] irq IRQ number
534 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
535 **********************************************************************************************************************/
R_BSP_IrqGptCombinedMaskSet(IRQn_Type irq,bsp_irq_gpt_combined_event_t event_source)536 __STATIC_INLINE void R_BSP_IrqGptCombinedMaskSet (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
537 {
538 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
539 uint32_t reg_num = bsp_prv_irq_gpt_reg_num_get(channel);
540 uint32_t shift_num = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
541
542 if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
543 {
544 R_ICU_NS->NS_GPT_INTMSK[reg_num] |= BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num;
545 }
546 else
547 {
548 R_ICU_S->S_GPT_INTMSK[reg_num] |= BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num;
549 }
550 }
551
552 /*******************************************************************************************************************//**
553 * Manipulate GPT_INTMSKn to unmask the GPT/MTU3 interrupt.
554 *
555 * @param[in] irq IRQ number
556 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
557 **********************************************************************************************************************/
R_BSP_IrqGptCombinedMaskClear(IRQn_Type irq,bsp_irq_gpt_combined_event_t event_source)558 __STATIC_INLINE void R_BSP_IrqGptCombinedMaskClear (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
559 {
560 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
561 uint32_t reg_num = bsp_prv_irq_gpt_reg_num_get(channel);
562 uint32_t shift_num = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
563
564 if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
565 {
566 R_ICU_NS->NS_GPT_INTMSK[reg_num] &= ~(BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
567 }
568 else
569 {
570 R_ICU_S->S_GPT_INTMSK[reg_num] &= ~(BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
571 }
572 }
573
574 /*******************************************************************************************************************//**
575 * Read GPT_INTSTATn and return the status of the GPT/MTU3 interrupt.
576 *
577 * @param[in] irq IRQ number
578 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
579 *
580 * @return GPT_INTSTATn value.
581 **********************************************************************************************************************/
R_BSP_IrqGptCombinedStatusRead(IRQn_Type irq)582 __STATIC_INLINE uint32_t R_BSP_IrqGptCombinedStatusRead (IRQn_Type irq)
583 {
584 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
585 uint32_t reg_num = bsp_prv_irq_gpt_reg_num_get(channel);
586 uint32_t intmsk = 0;
587 uint32_t intstat = 0;
588
589 if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
590 {
591 intmsk = ~(R_ICU_NS->NS_GPT_INTMSK[reg_num]);
592 intstat = R_ICU_NS->NS_GPT_INTSTAT[reg_num] & intmsk;
593 }
594 else
595 {
596 intmsk = ~(R_ICU_S->S_GPT_INTMSK[reg_num]);
597 intstat = R_ICU_S->S_GPT_INTSTAT[reg_num] & intmsk;
598 }
599
600 return intstat;
601 }
602
603 /*******************************************************************************************************************//**
604 * Write to GPT_INTCLRn to clear the GPT/MTU3 event occurrence state.
605 *
606 * @param[in] irq IRQ number
607 * @param[in] event_source Define the bit shift values of GPT_INTMSKn, GPT_INTCLRn and GPT_INTSTATn as an enum.
608 **********************************************************************************************************************/
R_BSP_IrqGptCombinedStatusClear(IRQn_Type irq,bsp_irq_gpt_combined_event_t event_source)609 __STATIC_INLINE void R_BSP_IrqGptCombinedStatusClear (IRQn_Type irq, bsp_irq_gpt_combined_event_t event_source)
610 {
611 uint32_t channel = bsp_prv_irq_gpt_channel_get(irq);
612 uint32_t reg_num = bsp_prv_irq_gpt_reg_num_get(channel);
613 uint32_t shift_num = bsp_prv_irq_gpt_combined_shift_num_get(channel, event_source);
614
615 if (channel < BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL)
616 {
617 R_ICU_NS->NS_GPT_INTCLR[reg_num] |= (BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
618 }
619 else
620 {
621 R_ICU_S->S_GPT_INTCLR[reg_num] |= (BSP_IRQ_GPT_COMBINED_EVENT_MASK << shift_num);
622 }
623 }
624
625 #endif
626
627 /** @} (end addtogroup BSP_MCU) */
628
629 /*******************************************************************************************************************//**
630 * @internal
631 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
632 * @ingroup RENESAS_INTERNAL
633 * @{
634 **********************************************************************************************************************/
635
636 /* Public functions defined in bsp.h */
637 void bsp_irq_cfg(void); // Used internally by BSP
638
639 /** @} (end addtogroup BSP_MCU_PRV) */
640
641 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
642 FSP_FOOTER
643
644 #endif
645
