1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 #ifndef R_USB_HOST_CFG_H_
8 #define R_USB_HOST_CFG_H_
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 #define USBH_CFG_PARAM_CHECKING_ENABLE    (BSP_CFG_PARAM_CHECKING_ENABLE)
14 
15 #define USBHS_PHY_CLOCK_SOURCE_IS_XTAL    (DT_ENUM_IDX_OR(DT_INST(0, renesas_ra_usbphyc), phys_clock_src, 0))
16 
17 #if USBHS_PHY_CLOCK_SOURCE_IS_XTAL
18 #if BSP_CFG_XTAL_HZ == 12000000
19 #define USBH_CFG_PHYSET_CLKSEL            (0U)
20 #elif BSP_CFG_XTAL_HZ == 48000000
21 #define USBH_CFG_PHYSET_CLKSEL            (0x1U)
22 #elif BSP_CFG_XTAL_HZ == 20000000
23 #define USBH_CFG_PHYSET_CLKSEL            (0x2U)
24 #elif BSP_CFG_XTAL_HZ == 24000000
25 #define USBH_CFG_PHYSET_CLKSEL            (0x3U)
26 #else
27 #error "Available XTAL clocks are 12-20-24-48Mhz"
28 #endif
29 #else   /* Use 48Mhz UCK as clock source for PHY clock */
30 #define USBH_CFG_PHYSET_CLKSEL            (-1)
31 #endif
32 
33 #define USBH_CFG_BUS_WAIT_CYCLES          (DT_PROP_OR(DT_NODELABEL(usbhs), bus_wait_cycles, 9) - 2)
34 
35 #ifdef __cplusplus
36 }
37 #endif
38 #endif /* R_USB_HOST_CFG_H_ */
39