1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_CFG_H_ 8 #define BSP_CFG_H_ 9 10 #include "soc.h" 11 #include "bsp_clock_cfg.h" 12 #include "bsp_mcu_family_cfg.h" 13 14 #define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000) 15 16 /* Disable BSP_CFG_PARAM_CHECKING_ENABLE as default to reduce code size */ 17 #define BSP_CFG_PARAM_CHECKING_ENABLE (0) 18 19 /* Add for zephyr porting */ 20 #define BSP_CFG_INTERRUPT_INIT 0 21 22 #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED 23 #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay)) 24 #endif 25 26 #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE 27 #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (DT_PROP_OR(DT_NODELABEL(xtal), mosel, 0)) 28 #endif 29 30 /* Keep 0 as default as LPM is not supported */ 31 #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE 32 #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (DT_PROP_OR(DT_NODELABEL(subclk), drive_capability, 0)) 33 #endif 34 35 #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED 36 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(subclk), okay)) 37 #endif 38 #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 39 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS \ 40 SUBCLOCK_STABILIZATION_MAX((DT_PROP_OR(DT_NODELABEL(subclk), stabilization_time, 1000))) 41 #endif 42 43 #define BSP_CFG_PFS_PROTECT (1) 44 45 #endif /* BSP_CFG_H_ */ 46
