1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 #ifndef BSP_CFG_H_
7 #define BSP_CFG_H_
8 
9 #include "soc.h"
10 #include "bsp_clock_cfg.h"
11 #include "bsp_mcu_family_cfg.h"
12 
13 #define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000)
14 #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
15 
16 #define BSP_CFG_PFS_PROTECT ((1))
17 
18 /* Add for zephyr porting */
19 #define BSP_CFG_INTERRUPT_INIT 0
20 #define BSP_CFG_SP_MON_INIT    0
21 
22 #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
23 #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay))
24 #endif
25 
26 #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
27 #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (DT_PROP_OR(DT_NODELABEL(xtal), mosel, 0))
28 #endif
29 #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
30 #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (DT_PROP_OR(DT_NODELABEL(subclk), drive_capability, 0))
31 #endif
32 #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
33 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(subclk), okay))
34 #endif
35 #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
36 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS                                                    \
37 	SUBCLOCK_STABILIZATION_MAX((DT_PROP_OR(DT_NODELABEL(subclk), stabilization_time, 1000)))
38 #endif
39 
40 #endif /* BSP_CFG_H_ */
41