1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * Includes <System Includes> , "Project Includes"
9 **********************************************************************************************************************/
10 #include "bsp_clocks.h"
11
12 /***********************************************************************************************************************
13 * Macro definitions
14 **********************************************************************************************************************/
15
16 /* Key code for writing PRCR register. */
17 #define BSP_PRV_PRCR_KEY (0xA500U)
18 #define BSP_PRV_PRCR_CGC_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U)
19 #define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
20
21 /* Key code for writing PCMD register. */
22 #define BSP_PRV_PCMD_KEY (0xA5U)
23
24 /* Calculate the value to write to SCKCR. */
25 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
26 #define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U)
27 #define BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS ((BSP_CFG_FSELXSPI1_DIVSELXSPI1 & 0x47U) << 8U)
28 #define BSP_PRV_STARTUP_SCKCR_CKIO_BITS ((BSP_CFG_CKIO & 7U) << 16U)
29 #define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U)
30 #define BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS ((BSP_CFG_PHYSEL & 1U) << 21U)
31 #define BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS ((BSP_CFG_CLMASEL & 1U) << 22U)
32 #define BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS ((BSP_CFG_SPI0ASYNCCLK & 1U) << 24U)
33 #define BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS ((BSP_CFG_SPI1ASYNCCLK & 1U) << 25U)
34 #define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U)
35 #define BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS ((BSP_CFG_SCI0ASYNCCLK & 1U) << 27U)
36 #define BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS ((BSP_CFG_SCI1ASYNCCLK & 1U) << 28U)
37 #define BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS ((BSP_CFG_SCI2ASYNCCLK & 1U) << 29U)
38 #define BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS ((BSP_CFG_SCI3ASYNCCLK & 1U) << 30U)
39 #define BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS ((BSP_CFG_SCI4ASYNCCLK & 1U) << 31U)
40 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
41 #define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U)
42 #define BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS ((BSP_CFG_FSELXSPI1_DIVSELXSPI1 & 0x47U) << 8U)
43 #define BSP_PRV_STARTUP_SCKCR_CKIO_BITS ((BSP_CFG_CKIO & 7U) << 16U)
44 #define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U)
45 #define BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS ((BSP_CFG_PHYSEL & 1U) << 21U)
46 #define BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS ((BSP_CFG_CLMASEL & 1U) << 22U)
47 #endif
48
49 /* Calculate the value to write to SCKCR2. */
50 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
51 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS (BSP_CFG_FSELCPU0 & 3U)
52 #if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM)
53 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS ((BSP_CFG_FSELCPU1 & 3U) << 2U)
54 #else
55 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS (0U)
56 #endif
57 #define BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS (1U << 4U) // The write value should be 1.
58 #define BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS ((BSP_CFG_DIVSELSUB & 1U) << 5U)
59 #define BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS ((BSP_CFG_SPI3ASYNCCLK & 1U) << 24U)
60 #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U)
61 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
62 #define BSP_PRV_STARTUP_SCKCR2_CR52CPU0_BITS (BSP_CFG_CR52C0CLK & 3U)
63 #define BSP_PRV_STARTUP_SCKCR2_CR52CPU1_BITS ((BSP_CFG_CR52C1CLK & 3U) << 2U)
64 #define BSP_PRV_STARTUP_SCKCR2_CA55CORE0_BITS ((BSP_CFG_CA55CORE0 & 1U) << 8U)
65 #define BSP_PRV_STARTUP_SCKCR2_CA55CORE1_BITS ((BSP_CFG_CA55CORE1 & 1U) << 9U)
66 #define BSP_PRV_STARTUP_SCKCR2_CA55CORE2_BITS ((BSP_CFG_CA55CORE2 & 1U) << 10U)
67 #define BSP_PRV_STARTUP_SCKCR2_CA55CORE3_BITS ((BSP_CFG_CA55CORE3 & 1U) << 11U)
68 #define BSP_PRV_STARTUP_SCKCR2_CA55SCLK_BITS ((BSP_CFG_CA55SCLK & 1U) << 12U)
69 #define BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS ((BSP_CFG_SPI3ASYNCCLK & 3U) << 16U)
70 #define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 3U) << 18U)
71 #endif
72
73 /* Calculate the value to write to SCKCR3. */
74 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
75 #define BSP_PRV_STARTUP_SCKCR3_SPI0ASYNCSEL_BITS (BSP_CFG_SPI0ASYNCCLK & 3U)
76 #define BSP_PRV_STARTUP_SCKCR3_SPI1ASYNCSEL_BITS ((BSP_CFG_SPI1ASYNCCLK & 3U) << 2U)
77 #define BSP_PRV_STARTUP_SCKCR3_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 3U) << 4U)
78 #define BSP_PRV_STARTUP_SCKCR3_SCI0ASYNCSEL_BITS ((BSP_CFG_SCI0ASYNCCLK & 3U) << 6U)
79 #define BSP_PRV_STARTUP_SCKCR3_SCI1ASYNCSEL_BITS ((BSP_CFG_SCI1ASYNCCLK & 3U) << 8U)
80 #define BSP_PRV_STARTUP_SCKCR3_SCI2ASYNCSEL_BITS ((BSP_CFG_SCI2ASYNCCLK & 3U) << 10U)
81 #define BSP_PRV_STARTUP_SCKCR3_SCI3ASYNCSEL_BITS ((BSP_CFG_SCI3ASYNCCLK & 3U) << 12U)
82 #define BSP_PRV_STARTUP_SCKCR3_SCI4ASYNCSEL_BITS ((BSP_CFG_SCI4ASYNCCLK & 3U) << 14U)
83 #define BSP_PRV_STARTUP_SCKCR3_LCDCDIVSEL_BITS ((BSP_CFG_LCDCDIVSEL & 15U) << 20U)
84 #endif
85
86 /* Calculate the value to write to SCKCR4. */
87 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
88 #define BSP_PRV_STARTUP_SCKCR4_SCIE0ASYNCSEL_BITS (BSP_CFG_SCIE0ASYNCCLK & 3U)
89 #define BSP_PRV_STARTUP_SCKCR4_SCIE1ASYNCSEL_BITS ((BSP_CFG_SCIE1ASYNCCLK & 3U) << 2U)
90 #define BSP_PRV_STARTUP_SCKCR4_SCIE2ASYNCSEL_BITS ((BSP_CFG_SCIE2ASYNCCLK & 3U) << 4U)
91 #define BSP_PRV_STARTUP_SCKCR4_SCIE3ASYNCSEL_BITS ((BSP_CFG_SCIE3ASYNCCLK & 3U) << 6U)
92 #define BSP_PRV_STARTUP_SCKCR4_SCIE4ASYNCSEL_BITS ((BSP_CFG_SCIE4ASYNCCLK & 3U) << 8U)
93 #define BSP_PRV_STARTUP_SCKCR4_SCIE5ASYNCSEL_BITS ((BSP_CFG_SCIE5ASYNCCLK & 3U) << 10U)
94 #define BSP_PRV_STARTUP_SCKCR4_SCIE6ASYNCSEL_BITS ((BSP_CFG_SCIE6ASYNCCLK & 3U) << 12U)
95 #define BSP_PRV_STARTUP_SCKCR4_SCIE7ASYNCSEL_BITS ((BSP_CFG_SCIE7ASYNCCLK & 3U) << 14U)
96 #define BSP_PRV_STARTUP_SCKCR4_SCIE8ASYNCSEL_BITS ((BSP_CFG_SCIE8ASYNCCLK & 3U) << 16U)
97 #define BSP_PRV_STARTUP_SCKCR4_SCIE9ASYNCSEL_BITS ((BSP_CFG_SCIE9ASYNCCLK & 3U) << 18U)
98 #define BSP_PRV_STARTUP_SCKCR4_SCIE10ASYNCSEL_BITS ((BSP_CFG_SCIE10ASYNCCLK & 3U) << 20U)
99 #define BSP_PRV_STARTUP_SCKCR4_SCIE11ASYNCSEL_BITS ((BSP_CFG_SCIE11ASYNCCLK & 3U) << 22U)
100 #define BSP_PRV_STARTUP_SCKCR4_ENCOUTCLK_BITS ((BSP_CFG_ENCOUTCLK & 1U) << 24U)
101 #endif
102 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
103 #define BSP_PRV_STARTUP_SCKCR (BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS | \
104 BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS | \
105 BSP_PRV_STARTUP_SCKCR_CKIO_BITS | \
106 BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS | \
107 BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS | \
108 BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS | \
109 BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS | \
110 BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS | \
111 BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS | \
112 BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS | \
113 BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS | \
114 BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS | \
115 BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS | \
116 BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS)
117
118 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
119 #define BSP_PRV_STARTUP_SCKCR (BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS | \
120 BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS | \
121 BSP_PRV_STARTUP_SCKCR_CKIO_BITS | \
122 BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS | \
123 BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS | \
124 BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS)
125 #endif
126 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
127 #define BSP_PRV_STARTUP_SCKCR2 (BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS | \
128 BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS | \
129 BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS | \
130 BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS | \
131 BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS | \
132 BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS)
133 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
134 #define BSP_PRV_STARTUP_SCKCR2 (BSP_PRV_STARTUP_SCKCR2_CR52CPU0_BITS | \
135 BSP_PRV_STARTUP_SCKCR2_CR52CPU1_BITS | \
136 BSP_PRV_STARTUP_SCKCR2_CA55CORE0_BITS | \
137 BSP_PRV_STARTUP_SCKCR2_CA55CORE1_BITS | \
138 BSP_PRV_STARTUP_SCKCR2_CA55CORE2_BITS | \
139 BSP_PRV_STARTUP_SCKCR2_CA55CORE3_BITS | \
140 BSP_PRV_STARTUP_SCKCR2_CA55SCLK_BITS | \
141 BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS | \
142 BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS)
143 #endif
144
145 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
146 #define BSP_PRV_STARTUP_SCKCR3 (0U)
147 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
148 #define BSP_PRV_STARTUP_SCKCR3 (BSP_PRV_STARTUP_SCKCR3_SPI0ASYNCSEL_BITS | \
149 BSP_PRV_STARTUP_SCKCR3_SPI1ASYNCSEL_BITS | \
150 BSP_PRV_STARTUP_SCKCR3_SPI2ASYNCSEL_BITS | \
151 BSP_PRV_STARTUP_SCKCR3_SCI0ASYNCSEL_BITS | \
152 BSP_PRV_STARTUP_SCKCR3_SCI1ASYNCSEL_BITS | \
153 BSP_PRV_STARTUP_SCKCR3_SCI2ASYNCSEL_BITS | \
154 BSP_PRV_STARTUP_SCKCR3_SCI3ASYNCSEL_BITS | \
155 BSP_PRV_STARTUP_SCKCR3_SCI4ASYNCSEL_BITS | \
156 BSP_PRV_STARTUP_SCKCR3_LCDCDIVSEL_BITS)
157 #endif
158 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
159 #define BSP_PRV_STARTUP_SCKCR4 (0U)
160 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
161 #define BSP_PRV_STARTUP_SCKCR4 (BSP_PRV_STARTUP_SCKCR4_SCIE0ASYNCSEL_BITS | \
162 BSP_PRV_STARTUP_SCKCR4_SCIE1ASYNCSEL_BITS | \
163 BSP_PRV_STARTUP_SCKCR4_SCIE2ASYNCSEL_BITS | \
164 BSP_PRV_STARTUP_SCKCR4_SCIE3ASYNCSEL_BITS | \
165 BSP_PRV_STARTUP_SCKCR4_SCIE4ASYNCSEL_BITS | \
166 BSP_PRV_STARTUP_SCKCR4_SCIE5ASYNCSEL_BITS | \
167 BSP_PRV_STARTUP_SCKCR4_SCIE6ASYNCSEL_BITS | \
168 BSP_PRV_STARTUP_SCKCR4_SCIE7ASYNCSEL_BITS | \
169 BSP_PRV_STARTUP_SCKCR4_SCIE8ASYNCSEL_BITS | \
170 BSP_PRV_STARTUP_SCKCR4_SCIE9ASYNCSEL_BITS | \
171 BSP_PRV_STARTUP_SCKCR4_SCIE10ASYNCSEL_BITS | \
172 BSP_PRV_STARTUP_SCKCR4_SCIE11ASYNCSEL_BITS | \
173 BSP_PRV_STARTUP_SCKCR4_ENCOUTCLK_BITS)
174 #endif
175
176 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
177
178 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_ICLK_MUL2 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2 << \
179 R_SYSC_S_SCKCR2_FSELCPU0_Pos)
180 #if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM)
181 #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_ICLK_MUL2 (BSP_CLOCKS_FSELCPU1_ICLK_MUL2 << \
182 R_SYSC_S_SCKCR2_FSELCPU1_Pos)
183 #endif
184
185 #endif
186
187 /* Calculate the value to write to HIZCTRLEN. */
188 #if (4 == BSP_FEATURE_CGC_CLMA_UNIT)
189 #define BSP_PRV_STARTUP_HIZCTRLEN ((BSP_CFG_CLMA1MASK << 2) | (BSP_CFG_CLMA0MASK << 1) | \
190 BSP_CFG_CLMA3MASK)
191 #elif (7 == BSP_FEATURE_CGC_CLMA_UNIT)
192 #define BSP_PRV_STARTUP_HIZCTRLEN ((BSP_CFG_CLMA4MASK << 5) | \
193 (BSP_CFG_CLMA3MASK << 4) | \
194 (BSP_CFG_CLMA2MASK << 3) | \
195 (BSP_CFG_CLMA1MASK << 2) | \
196 (BSP_CFG_CLMA0MASK << 1) | \
197 (BSP_CFG_CLMA6MASK))
198 #endif
199
200 /* Calculate the value to write to PLL0_SSC_CTR */
201 #if BSP_FEATURE_CGC_PLL0_STANDBY_STATE_SUPPORTED
202 #define BSP_PRV_STARTUP_PLL0_SSC_CTR ((BSP_CFG_PLL0MFR << 24) | \
203 (BSP_CFG_PLL0MRR << 16) | \
204 (BSP_CFG_PLL0SSCEN << 0))
205 #endif
206
207 /* Calculate the value to write to PLL2_SSC_CTR */
208 #if BSP_FEATURE_CGC_PLL2_STANDBY_STATE_SUPPORTED
209 #define BSP_PRV_STARTUP_PLL2_SSC_CTR ((BSP_CFG_PLL2MFR << 24) | \
210 (BSP_CFG_PLL2MRR << 16) | \
211 (BSP_CFG_PLL2SSCEN << 0))
212
213 #endif
214
215 /* Calculate the value to write to PLL3_VCO_CTR */
216 #if BSP_FEATURE_CGC_PLL3_STANDBY_STATE_SUPPORTED
217 #define BSP_PRV_STARTUP_PLL3_VCO_CTR0 ((BSP_CFG_PLL3P << 16) | \
218 (BSP_CFG_PLL3M << 0))
219
220 #define BSP_PRV_STARTUP_PLL3_VCO_CTR1 ((BSP_CFG_PLL3K << 16) | \
221 (BSP_CFG_PLL3S << 0))
222 #endif
223
224 /* Frequencies of clocks. */
225 #define BSP_PRV_CPU_FREQ_600_MHZ (600000000U) // CPU frequency is 600 MHz
226 #define BSP_PRV_CPU_FREQ_500_MHZ (500000000U) // CPU frequency is 500 MHz
227 #define BSP_PRV_CPU_FREQ_200_MHZ (200000000U) // CPU frequency is 200 MHz
228 #define BSP_PRV_CPU_FREQ_150_MHZ (150000000U) // CPU frequency is 150 MHz
229
230 /* Command sequence for enabling CLMA. */
231 #define BSP_PRV_CTL0_ENABLE_TARGET_CMD (0x01)
232 #define BSP_PRV_CTL0_ENABLE_REVERSED_CMD (0xFE)
233
234 #define BSP_PRV_LOCO_STABILIZATION_COUNT (40000)
235
236 /***********************************************************************************************************************
237 * Typedef definitions
238 **********************************************************************************************************************/
239
240 /***********************************************************************************************************************
241 * Exported global variables (to be accessed by other files)
242 **********************************************************************************************************************/
243
244 /***********************************************************************************************************************
245 * Private global variables and functions
246 **********************************************************************************************************************/
247 #if !BSP_CFG_SOFT_RESET_SUPPORTED
248 static void bsp_prv_clock_set_hard_reset(void);
249
250 #endif
251
252 /*******************************************************************************************************************//**
253 * @internal
254 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
255 * @ingroup RENESAS_INTERNAL
256 * @{
257 **********************************************************************************************************************/
258
259 /*******************************************************************************************************************//**
260 * Update SystemCoreClock variable based on current clock settings.
261 **********************************************************************************************************************/
SystemCoreClockUpdate(void)262 void SystemCoreClockUpdate (void)
263 {
264 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
265 #if defined(BSP_CFG_CORE_CR52)
266 uint32_t devselsub = R_SYSC_S->SCKCR2_b.DIVSELSUB;
267 uint32_t fselcpu = R_SYSC_S->SCKCR2_b.FSELCPU0;
268
269 if (0U == devselsub)
270 {
271 SystemCoreClock = BSP_PRV_CPU_FREQ_200_MHZ << fselcpu;
272 }
273 else
274 {
275 SystemCoreClock = BSP_PRV_CPU_FREQ_150_MHZ << fselcpu;
276 }
277 #endif
278 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
279 #if defined(BSP_CFG_CORE_CR52)
280 #if (0 == BSP_CFG_CORE_CR52)
281 uint32_t cr52cpu = R_SYSC_S->SCKCR2_b.CR52CPU0;
282 #elif (1 == BSP_CFG_CORE_CR52)
283 uint32_t cr52cpu = R_SYSC_S->SCKCR2_b.CR52CPU1;
284 #endif
285 SystemCoreClock = BSP_PRV_CPU_FREQ_500_MHZ << cr52cpu;
286 #elif defined(BSP_CFG_CORE_CA55)
287 #if (0 == BSP_CFG_CORE_CA55)
288 uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE0;
289 #elif (1 == BSP_CFG_CORE_CA55)
290 uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE1;
291 #elif (2 == BSP_CFG_CORE_CA55)
292 uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE2;
293 #elif (3 == BSP_CFG_CORE_CA55)
294 uint32_t ca55core = R_SYSC_S->SCKCR2_b.CA55CORE3;
295 #endif
296 SystemCoreClock = BSP_PRV_CPU_FREQ_600_MHZ << ca55core;
297 #endif
298 #endif
299 }
300
301 /*******************************************************************************************************************//**
302 * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this
303 * configuration and the CGC registers are expected to be unlocked in PRCR.
304 *
305 * @param[in] sckcr Value to set in SCKCR register
306 * @param[in] sckcr2 Value to set in SCKCR2 register
307 * @param[in] sckcr3 Value to set in SCKCR3 register
308 * @param[in] sckcr4 Value to set in SCKCR4 register
309 **********************************************************************************************************************/
bsp_prv_clock_set(uint32_t sckcr,uint32_t sckcr2,uint32_t sckcr3,uint32_t sckcr4)310 void bsp_prv_clock_set (uint32_t sckcr, uint32_t sckcr2, uint32_t sckcr3, uint32_t sckcr4)
311 {
312 volatile uint32_t dummy;
313 sckcr = sckcr & BSP_PRV_SCKCR_MASK;
314 sckcr2 = sckcr2 & BSP_PRV_SCKCR2_MASK;
315 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
316 FSP_PARAMETER_NOT_USED(sckcr3);
317 FSP_PARAMETER_NOT_USED(sckcr4);
318 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
319 sckcr3 = sckcr3 & BSP_PRV_SCKCR3_MASK;
320 sckcr4 = sckcr4 & BSP_PRV_SCKCR4_MASK;
321 #endif
322
323 /* Set the system source clock */
324 R_SYSC_S->SCKCR2 = sckcr2;
325
326 /** In order to secure processing after clock frequency is changed,
327 * dummy read the same register at least eight times.
328 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
329 dummy = R_SYSC_S->SCKCR2;
330 dummy = R_SYSC_S->SCKCR2;
331 dummy = R_SYSC_S->SCKCR2;
332 dummy = R_SYSC_S->SCKCR2;
333 dummy = R_SYSC_S->SCKCR2;
334 dummy = R_SYSC_S->SCKCR2;
335 dummy = R_SYSC_S->SCKCR2;
336 dummy = R_SYSC_S->SCKCR2;
337
338 R_SYSC_NS->SCKCR = sckcr;
339
340 /** In order to secure processing after clock frequency is changed,
341 * dummy read the same register at least eight times.
342 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
343 dummy = R_SYSC_NS->SCKCR;
344 dummy = R_SYSC_NS->SCKCR;
345 dummy = R_SYSC_NS->SCKCR;
346 dummy = R_SYSC_NS->SCKCR;
347 dummy = R_SYSC_NS->SCKCR;
348 dummy = R_SYSC_NS->SCKCR;
349 dummy = R_SYSC_NS->SCKCR;
350 dummy = R_SYSC_NS->SCKCR;
351
352 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
353 R_SYSC_NS->SCKCR3 = sckcr3;
354
355 /** In order to secure processing after clock frequency is changed,
356 * dummy read the same register at least eight times.
357 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
358 dummy = R_SYSC_NS->SCKCR3;
359 dummy = R_SYSC_NS->SCKCR3;
360 dummy = R_SYSC_NS->SCKCR3;
361 dummy = R_SYSC_NS->SCKCR3;
362 dummy = R_SYSC_NS->SCKCR3;
363 dummy = R_SYSC_NS->SCKCR3;
364 dummy = R_SYSC_NS->SCKCR3;
365 dummy = R_SYSC_NS->SCKCR3;
366
367 R_SYSC_NS->SCKCR4 = sckcr4;
368
369 /** In order to secure processing after clock frequency is changed,
370 * dummy read the same register at least eight times.
371 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
372 dummy = R_SYSC_NS->SCKCR4;
373 dummy = R_SYSC_NS->SCKCR4;
374 dummy = R_SYSC_NS->SCKCR4;
375 dummy = R_SYSC_NS->SCKCR4;
376 dummy = R_SYSC_NS->SCKCR4;
377 dummy = R_SYSC_NS->SCKCR4;
378 dummy = R_SYSC_NS->SCKCR4;
379 dummy = R_SYSC_NS->SCKCR4;
380 #endif
381
382 FSP_PARAMETER_NOT_USED(dummy);
383
384 /* Clock is now at requested frequency. */
385
386 /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
387 SystemCoreClockUpdate();
388 }
389
390 #if !BSP_CFG_SOFT_RESET_SUPPORTED
391
bsp_prv_clock_set_hard_reset(void)392 static void bsp_prv_clock_set_hard_reset (void)
393 {
394 volatile uint32_t dummy;
395 uint32_t sckcr = BSP_PRV_STARTUP_SCKCR & BSP_PRV_SCKCR_MASK;
396 uint32_t sckcr2 = BSP_PRV_STARTUP_SCKCR2 & BSP_PRV_SCKCR2_MASK;
397 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
398 uint32_t sckcr3 = BSP_PRV_STARTUP_SCKCR3 & BSP_PRV_SCKCR3_MASK;
399 uint32_t sckcr4 = BSP_PRV_STARTUP_SCKCR4 & BSP_PRV_SCKCR4_MASK;
400 #endif
401
402 /* Set the system source clock */
403 R_SYSC_S->SCKCR2 = sckcr2;
404
405 /** In order to secure processing after clock frequency is changed,
406 * dummy read the same register at least eight times.
407 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
408 dummy = R_SYSC_S->SCKCR2;
409 dummy = R_SYSC_S->SCKCR2;
410 dummy = R_SYSC_S->SCKCR2;
411 dummy = R_SYSC_S->SCKCR2;
412 dummy = R_SYSC_S->SCKCR2;
413 dummy = R_SYSC_S->SCKCR2;
414 dummy = R_SYSC_S->SCKCR2;
415 dummy = R_SYSC_S->SCKCR2;
416
417 R_SYSC_NS->SCKCR = sckcr;
418
419 /** In order to secure processing after clock frequency is changed,
420 * dummy read the same register at least eight times.
421 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
422 dummy = R_SYSC_NS->SCKCR;
423 dummy = R_SYSC_NS->SCKCR;
424 dummy = R_SYSC_NS->SCKCR;
425 dummy = R_SYSC_NS->SCKCR;
426 dummy = R_SYSC_NS->SCKCR;
427 dummy = R_SYSC_NS->SCKCR;
428 dummy = R_SYSC_NS->SCKCR;
429 dummy = R_SYSC_NS->SCKCR;
430
431 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
432 R_SYSC_NS->SCKCR3 = sckcr3;
433
434 /** In order to secure processing after clock frequency is changed,
435 * dummy read the same register at least eight times.
436 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
437 dummy = R_SYSC_NS->SCKCR3;
438 dummy = R_SYSC_NS->SCKCR3;
439 dummy = R_SYSC_NS->SCKCR3;
440 dummy = R_SYSC_NS->SCKCR3;
441 dummy = R_SYSC_NS->SCKCR3;
442 dummy = R_SYSC_NS->SCKCR3;
443 dummy = R_SYSC_NS->SCKCR3;
444 dummy = R_SYSC_NS->SCKCR3;
445
446 R_SYSC_NS->SCKCR4 = sckcr4;
447
448 /** In order to secure processing after clock frequency is changed,
449 * dummy read the same register at least eight times.
450 * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
451 dummy = R_SYSC_NS->SCKCR4;
452 dummy = R_SYSC_NS->SCKCR4;
453 dummy = R_SYSC_NS->SCKCR4;
454 dummy = R_SYSC_NS->SCKCR4;
455 dummy = R_SYSC_NS->SCKCR4;
456 dummy = R_SYSC_NS->SCKCR4;
457 dummy = R_SYSC_NS->SCKCR4;
458 dummy = R_SYSC_NS->SCKCR4;
459 #endif
460
461 FSP_PARAMETER_NOT_USED(dummy);
462
463 /* Clock is now at requested frequency. */
464
465 /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
466 SystemCoreClockUpdate();
467 }
468
469 #endif
470
471 /*******************************************************************************************************************//**
472 * Initializes system clocks. Makes no assumptions about current register settings.
473 **********************************************************************************************************************/
bsp_clock_init(void)474 void bsp_clock_init (void)
475 {
476 volatile uint32_t dummy = 0;
477
478 /* Unlock CGC protection registers. */
479 R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK;
480 R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK;
481
482 /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */
483 SystemCoreClockUpdate();
484
485 /* Set source clock and dividers. */
486 #if BSP_CFG_SOFT_RESET_SUPPORTED
487 bsp_prv_clock_set(BSP_PRV_STARTUP_SCKCR, BSP_PRV_STARTUP_SCKCR2, BSP_PRV_STARTUP_SCKCR3, BSP_PRV_STARTUP_SCKCR4);
488 #else
489 bsp_prv_clock_set_hard_reset();
490 #endif
491
492 #if (BSP_FEATURE_CGC_PLL0_STANDBY_STATE_SUPPORTED)
493 if (BSP_CLOCKS_PLL0_NORMAL == BSP_CFG_PLL0)
494 {
495 if (BSP_CLOCKS_PLL0_STANDBY == R_SYSC_S->PLL0EN_b.PLL0EN)
496 {
497 /* Configure SSC settings. */
498 if (BSP_CFG_PLL0SSCEN == BSP_CLOCKS_PLL0SSCEN_ENABLE)
499 {
500 R_SYSC_S->PLL0_SSC_CTR = BSP_PRV_STARTUP_PLL0_SSC_CTR;
501 }
502
503 /* Release PLL from standby state. */
504 R_SYSC_S->PLL0EN = BSP_CFG_PLL0;
505
506 /* Confirm transition to normal mode. */
507 FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PLL0MON_b.PLL0MON, 1U);
508
509 /* Confirm clock source change of PLL clock domain. */
510 FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PMSEL_b.PMSEL0MON, 1U);
511 }
512 }
513 #endif
514
515 #if (BSP_FEATURE_CGC_PLL1_STANDBY_STATE_SUPPORTED)
516 #if (BSP_CLOCKS_PLL1_INITIAL != BSP_CFG_PLL1)
517
518 /* Release PLL from standby state. */
519 R_SYSC_S->PLL1EN = BSP_CFG_PLL1;
520 #endif
521 #endif
522
523 #if (BSP_FEATURE_CGC_PLL2_STANDBY_STATE_SUPPORTED)
524 if (BSP_CLOCKS_PLL2_NORMAL == BSP_CFG_PLL2)
525 {
526 if (BSP_CLOCKS_PLL2_STANDBY == R_SYSC_S->PLL2EN_b.PLL2EN)
527 {
528 /* Configure SSC settings. */
529 if (BSP_CFG_PLL0SSCEN == BSP_CLOCKS_PLL0SSCEN_ENABLE)
530 {
531 R_SYSC_S->PLL2_SSC_CTR = BSP_PRV_STARTUP_PLL2_SSC_CTR;
532 }
533
534 /* Release PLL from standby state. */
535 R_SYSC_S->PLL2EN = BSP_CFG_PLL2;
536
537 /* Confirm transition to normal mode. */
538 FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PLL2MON_b.PLL2MON, 1U);
539
540 /* Confirm clock source change of PLL clock domain. */
541 FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PMSEL_b.PMSEL2MON, 1U);
542 }
543 }
544 #endif
545
546 #if (BSP_FEATURE_CGC_PLL3_STANDBY_STATE_SUPPORTED)
547 if (BSP_CLOCKS_PLL3_NORMAL == BSP_CFG_PLL3)
548 {
549 if (BSP_CLOCKS_PLL3_STANDBY == R_SYSC_S->PLL3EN_b.PLL3EN)
550 {
551 /* Configure PLL3 settings. */
552 R_SYSC_S->PLL3_VCO_CTR0 = BSP_PRV_STARTUP_PLL3_VCO_CTR0;
553 R_SYSC_S->PLL3_VCO_CTR1 = BSP_PRV_STARTUP_PLL3_VCO_CTR1;
554
555 /* Release PLL from standby state. */
556 R_SYSC_S->PLL3EN = BSP_CFG_PLL3;
557
558 /* Confirm transition to normal mode. */
559 FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PLL3MON_b.PLL3MON, 1U);
560
561 /* Confirm clock source change of PLL clock domain. */
562 FSP_HARDWARE_REGISTER_WAIT(R_SYSC_S->PMSEL_b.PMSEL3MON, 1U);
563 }
564 }
565 #endif
566
567 #if (BSP_CLOCKS_LOCO_ENABLE == BSP_CFG_LOCO_ENABLE)
568 R_SYSC_S->LOCOCR = BSP_CLOCKS_LOCO_ENABLE;
569
570 /* Only start using the LOCO clock after
571 * the LOCO oscillation stabilization time (tLOCOWT) has elapsed. */
572 for (uint16_t i = 0; i < BSP_PRV_LOCO_STABILIZATION_COUNT; i++)
573 {
574 __asm volatile ("nop");
575 }
576 #endif
577
578 R_SYSC_S->HIZCTRLEN = BSP_PRV_STARTUP_HIZCTRLEN;
579
580 #if (BSP_CLOCKS_CLMA0_ENABLE == BSP_CFG_CLMA0_ENABLE)
581
582 /* Set the lower and upper limit for comparing frequency domains. */
583 R_CLMA0->CMPL = BSP_CFG_CLMA0_CMPL;
584 R_CLMA0->CMPH = BSP_CFG_CLMA0_CMPH;
585
586 /* Enabling CLMA0 operation. */
587 do
588 {
589 R_CLMA0->PCMD = BSP_PRV_PCMD_KEY;
590
591 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
592 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
593 R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
594
595 if (1 != R_CLMA0->CTL0)
596 {
597 /* Check the value of PROTSR register. */
598 dummy = R_CLMA0->PROTSR;
599 }
600 } while (1 == R_CLMA0->PROTSR_b.PRERR);
601 #endif
602
603 #if (BSP_CLOCKS_CLMA1_ENABLE == BSP_CFG_CLMA1_ENABLE)
604
605 /* Set the lower and upper limit for comparing frequency domains. */
606 R_CLMA1->CMPL = BSP_CFG_CLMA1_CMPL;
607 R_CLMA1->CMPH = BSP_CFG_CLMA1_CMPH;
608
609 /* Enabling CLMA1 operation. */
610 do
611 {
612 R_CLMA1->PCMD = BSP_PRV_PCMD_KEY;
613
614 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
615 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
616 R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
617
618 if (1 != R_CLMA1->CTL0)
619 {
620 /* Check the value of PROTSR register. */
621 dummy = R_CLMA1->PROTSR;
622 }
623 } while (1 == R_CLMA1->PROTSR_b.PRERR);
624 #endif
625
626 #if (BSP_CLOCKS_CLMA2_ENABLE == BSP_CFG_CLMA2_ENABLE)
627
628 /* Set the lower and upper limit for comparing frequency domains. */
629 R_CLMA2->CMPL = BSP_CFG_CLMA2_CMPL;
630 R_CLMA2->CMPH = BSP_CFG_CLMA2_CMPH;
631
632 /* Enabling CLMA2 operation. */
633 do
634 {
635 R_CLMA2->PCMD = BSP_PRV_PCMD_KEY;
636
637 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
638 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
639 R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
640
641 if (1 != R_CLMA2->CTL0)
642 {
643 /* Check the value of PROTSR register. */
644 dummy = R_CLMA2->PROTSR;
645 }
646 } while (1 == R_CLMA2->PROTSR_b.PRERR);
647 #endif
648
649 #if (BSP_CLOCKS_CLMA3_ENABLE == BSP_CFG_CLMA3_ENABLE)
650
651 /* Set the lower and upper limit for comparing frequency domains. */
652 R_CLMA3->CMPL = BSP_CFG_CLMA3_CMPL;
653 R_CLMA3->CMPH = BSP_CFG_CLMA3_CMPH;
654
655 /* Enabling CLMA3 operation. */
656 do
657 {
658 R_CLMA3->PCMD = BSP_PRV_PCMD_KEY;
659
660 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
661 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
662 R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
663
664 if (1 != R_CLMA3->CTL0)
665 {
666 /* Check the value of PROTSR register. */
667 dummy = R_CLMA3->PROTSR;
668 }
669 } while (1 == R_CLMA3->PROTSR_b.PRERR);
670 #endif
671
672 #if (BSP_CLOCKS_CLMA4_ENABLE == BSP_CFG_CLMA4_ENABLE)
673
674 /* Set the lower and upper limit for comparing frequency domains. */
675 R_CLMA4->CMPL = BSP_CFG_CLMA4_CMPL;
676 R_CLMA4->CMPH = BSP_CFG_CLMA4_CMPH;
677
678 /* Enabling CLMA4 operation. */
679 do
680 {
681 R_CLMA4->PCMD = BSP_PRV_PCMD_KEY;
682
683 R_CLMA4->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
684 R_CLMA4->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
685 R_CLMA4->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
686
687 if (1 != R_CLMA4->CTL0)
688 {
689 /* Check the value of PROTSR register. */
690 dummy = R_CLMA4->PROTSR;
691 }
692 } while (1 == R_CLMA4->PROTSR_b.PRERR);
693 #endif
694
695 #if (BSP_CLOCKS_CLMA5_ENABLE == BSP_CFG_CLMA5_ENABLE)
696
697 /* Set the lower and upper limit for comparing frequency domains. */
698 R_CLMA5->CMPL = BSP_CFG_CLMA5_CMPL;
699 R_CLMA5->CMPH = BSP_CFG_CLMA5_CMPH;
700
701 /* Enabling CLMA5 operation. */
702 do
703 {
704 R_CLMA5->PCMD = BSP_PRV_PCMD_KEY;
705
706 R_CLMA5->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
707 R_CLMA5->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
708 R_CLMA5->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
709
710 if (1 != R_CLMA5->CTL0)
711 {
712 /* Check the value of PROTSR register. */
713 dummy = R_CLMA5->PROTSR;
714 }
715 } while (1 == R_CLMA5->PROTSR_b.PRERR);
716 #endif
717
718 #if (BSP_CLOCKS_CLMA6_ENABLE == BSP_CFG_CLMA6_ENABLE)
719
720 /* Set the lower and upper limit for comparing frequency domains. */
721 R_CLMA6->CMPL = BSP_CFG_CLMA6_CMPL;
722 R_CLMA6->CMPH = BSP_CFG_CLMA6_CMPH;
723
724 /* Enabling CLMA6 operation. */
725 do
726 {
727 R_CLMA6->PCMD = BSP_PRV_PCMD_KEY;
728
729 R_CLMA6->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
730 R_CLMA6->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
731 R_CLMA6->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
732
733 if (1 != R_CLMA6->CTL0)
734 {
735 /* Check the value of PROTSR register. */
736 dummy = R_CLMA6->PROTSR;
737 }
738 } while (1 == R_CLMA6->PROTSR_b.PRERR);
739 #endif
740
741 /* Lock CGC and LPM protection registers. */
742 R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_LOCK;
743 R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_LOCK;
744
745 FSP_PARAMETER_NOT_USED(dummy);
746 }
747
748 /** @} (end addtogroup BSP_MCU_PRV) */
749
