1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef R_SCI_UART_H 8 #define R_SCI_UART_H 9 10 /*******************************************************************************************************************//** 11 * @addtogroup SCI_UART 12 * @{ 13 **********************************************************************************************************************/ 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 #include "bsp_api.h" 19 #include "r_uart_api.h" 20 #include "r_sci_uart_cfg.h" 21 22 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 23 FSP_HEADER 24 25 /*********************************************************************************************************************** 26 * Macro definitions 27 **********************************************************************************************************************/ 28 29 /********************************************************************************************************************** 30 * Typedef definitions 31 **********************************************************************************************************************/ 32 33 /** Enumeration for SCI clock source */ 34 typedef enum e_sci_uart_clock 35 { 36 SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation 37 SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK 38 SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate 39 SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate 40 } sci_uart_clock_t; 41 42 /** UART flow control mode definition */ 43 typedef enum e_sci_uart_flow_control 44 { 45 SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS 46 SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS 47 SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS 48 SCI_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS 49 } sci_uart_flow_control_t; 50 51 /** UART instance control block. */ 52 typedef struct st_sci_uart_instance_ctrl 53 { 54 /* Parameters to control UART peripheral device */ 55 uint8_t fifo_depth; // FIFO depth of the UART channel 56 uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise 57 uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data 58 uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise 59 uint32_t open; // Used to determine if the channel is configured 60 61 bsp_io_port_pin_t flow_pin; 62 63 /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ 64 uint8_t const * p_tx_src; 65 66 /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ 67 uint32_t tx_src_bytes; 68 69 /* Destination buffer pointer used for receiving data. */ 70 uint8_t const * p_rx_dest; 71 72 /* Size of destination buffer pointer used for receiving data. */ 73 uint32_t rx_dest_bytes; 74 75 /* Pointer to the configuration block. */ 76 uart_cfg_t const * p_cfg; 77 78 /* Base register for this channel */ 79 R_SCI0_Type * p_reg; 80 81 void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. 82 uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. 83 84 /* Pointer to context to be passed into callback function */ 85 void const * p_context; 86 } sci_uart_instance_ctrl_t; 87 88 /** Receive FIFO trigger configuration. */ 89 typedef enum e_sci_uart_rx_fifo_trigger 90 { 91 SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering 92 SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) 93 } sci_uart_rx_fifo_trigger_t; 94 95 /** Asynchronous Start Bit Edge Detection configuration. */ 96 typedef enum e_sci_uart_start_bit 97 { 98 SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit 99 SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit 100 } sci_uart_start_bit_t; 101 102 /** Noise cancellation configuration. */ 103 typedef enum e_sci_uart_noise_cancellation 104 { 105 SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation 106 SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation, The base clock signal divided by 1 107 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1 = 0x2, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 1 108 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2 = 0x3, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 2 109 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4 = 0x4, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 4 110 SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8 = 0x5, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 8 111 } sci_uart_noise_cancellation_t; 112 113 /** RS-485 Enable/Disable. */ 114 typedef enum e_sci_uart_rs485_enable 115 { 116 SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. 117 SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. 118 } sci_uart_rs485_enable_t; 119 120 /** The polarity of the RS-485 DE signal. */ 121 typedef enum e_sci_uart_rs485_de_polarity 122 { 123 SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. 124 SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. 125 } sci_uart_rs485_de_polarity_t; 126 127 /** Source clock selection options for SCI. */ 128 typedef enum e_sci_uart_clock_source 129 { 130 SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0, 131 SCI_UART_CLOCK_SOURCE_SCI1ASYNCCLK = 1, 132 SCI_UART_CLOCK_SOURCE_SCI2ASYNCCLK = 2, 133 SCI_UART_CLOCK_SOURCE_SCI3ASYNCCLK = 3, 134 SCI_UART_CLOCK_SOURCE_SCI4ASYNCCLK = 4, 135 SCI_UART_CLOCK_SOURCE_SCI5ASYNCCLK = 5, 136 SCI_UART_CLOCK_SOURCE_PCLKM = 6, 137 } sci_uart_clock_source_t; 138 139 /** Baudrate calculation configuration. */ 140 typedef struct st_sci_uart_baud_calculation 141 { 142 uint32_t baudrate; ///< Target baudrate 143 bool bitrate_modulation; ///< Whether bitrate modulation use or not 144 uint32_t baud_rate_error_x_1000; ///< Max baudrate percent error 145 } sci_uart_baud_calculation_t; 146 147 /** Register settings to achieve a desired baud rate and modulation duty. */ 148 typedef struct st_sci_baud_setting_t 149 { 150 union 151 { 152 uint32_t baudrate_bits; 153 154 struct 155 { 156 uint32_t : 4; 157 uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select 158 uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select 159 uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 160 uint32_t : 1; 161 uint32_t brr : 8; ///< Bit Rate Register setting 162 uint32_t brme : 1; ///< Bit Rate Modulation Enable 163 uint32_t : 3; 164 uint32_t cks : 2; ///< CKS value to get divisor (CKS = N) 165 uint32_t : 2; 166 uint32_t mddr : 8; ///< Modulation Duty Register setting 167 } baudrate_bits_b; 168 }; 169 } sci_baud_setting_t; 170 171 /** Configuration settings for controlling the DE signal for RS-485. */ 172 typedef struct st_sci_uart_rs485_setting 173 { 174 sci_uart_rs485_enable_t enable; ///< Enable the DE signal. 175 sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. 176 uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer. 177 uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated. 178 } sci_uart_rs485_setting_t; 179 180 /** UART on SCI device Configuration */ 181 typedef struct st_sci_uart_extended_cfg 182 { 183 sci_uart_clock_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK 184 sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge 185 sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting 186 187 sci_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. 188 189 sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used. 190 191 bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin 192 sci_uart_flow_control_t flow_control; ///< CTS/RTS function 193 sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. 194 195 /** Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK. */ 196 sci_uart_clock_source_t clock_source; 197 } sci_uart_extended_cfg_t; 198 199 /********************************************************************************************************************** 200 * Exported global variables 201 **********************************************************************************************************************/ 202 203 /** @cond INC_HEADER_DEFS_SEC */ 204 /** Filled in Interface API structure for this Instance. */ 205 extern const uart_api_t g_uart_on_sci; 206 207 /** @endcond */ 208 209 fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); 210 fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); 211 fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); 212 fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_ctrl, void const * const p_baud_setting); 213 fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); 214 fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_ctrl); 215 fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); 216 fsp_err_t R_SCI_UART_BaudCalculate(sci_uart_baud_calculation_t const * const p_baud_target, 217 sci_uart_clock_source_t clock_source, 218 sci_baud_setting_t * const p_baud_setting); 219 fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_ctrl, 220 void ( * p_callback)(uart_callback_args_t *), 221 void const * const p_context, 222 uart_callback_args_t * const p_callback_memory); 223 fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); 224 225 /*******************************************************************************************************************//** 226 * @} (end addtogroup SCI_UART) 227 **********************************************************************************************************************/ 228 229 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 230 FSP_FOOTER 231 232 #endif 233
