1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef R_SCIF_UART_H 8 #define R_SCIF_UART_H 9 10 /*******************************************************************************************************************//** 11 * @addtogroup SCIF_UART 12 * @{ 13 **********************************************************************************************************************/ 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 #include "bsp_api.h" 19 #include "r_uart_api.h" 20 #include "r_scif_uart_cfg.h" 21 22 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 23 FSP_HEADER 24 25 /*********************************************************************************************************************** 26 * Macro definitions 27 **********************************************************************************************************************/ 28 #define SCIF_UART_INVALID_16BIT_PARAM (0xFFFFU) 29 #define SCIF_UART_INVALID_8BIT_PARAM (0xFFU) 30 31 /********************************************************************************************************************** 32 * Typedef definitions 33 **********************************************************************************************************************/ 34 35 /** Enumeration for SCIF clock source */ 36 typedef enum e_scif_clk_src 37 { 38 SCIF_UART_CLOCK_INT, ///< Use internal clock for baud generation 39 SCIF_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK 40 SCIF_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate 41 SCIF_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate 42 } scif_clk_src_t; 43 44 /** UART communication mode definition */ 45 typedef enum e_scif_uart_mode 46 { 47 SCIF_UART_MODE_RS232, ///< Enables RS232 communication mode 48 SCIF_UART_MODE_RS485_HD, ///< Enables RS485 half duplex communication mode 49 SCIF_UART_MODE_RS485_FD, ///< Enables RS485 full duplex communication mode 50 } scif_uart_mode_t; 51 52 /** UART automatic flow control definition */ 53 typedef enum e_scif_uart_flow_control 54 { 55 SCIF_UART_FLOW_CONTROL_NONE, ///< Disables flow control 56 SCIF_UART_FLOW_CONTROL_AUTO, ///< Enables automatic RTS/CTS flow control 57 } scif_uart_flow_control_t; 58 59 /** Noise cancellation configuration. */ 60 typedef enum e_scif_uart_noise_cancellation 61 { 62 SCIF_UART_NOISE_CANCELLATION_DISABLE, ///< Disable noise cancellation 63 SCIF_UART_NOISE_CANCELLATION_ENABLE, ///< Enable noise cancellation 64 } scif_uart_noise_cancellation_t; 65 66 /** RS-485 Enable/Disable. */ 67 typedef enum e_sci_uart_rs485_enable 68 { 69 SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. 70 SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. 71 } sci_uart_rs485_enable_t; 72 73 /** The polarity of the RS-485 DE signal. */ 74 typedef enum e_sci_uart_rs485_de_polarity 75 { 76 SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. 77 SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. 78 } sci_uart_rs485_de_polarity_t; 79 80 /** Receive FIFO trigger configuration. */ 81 typedef enum e_scif_uart_receive_trigger 82 { 83 SCIF_UART_RECEIVE_TRIGGER_ONE, ///< Interrupt at least one byte is in FIFO 84 SCIF_UART_RECEIVE_TRIGGER_QUARTER, ///< Interrupt at least quarter of FIFO or 15ETU past from last receive 85 SCIF_UART_RECEIVE_TRIGGER_HALF, ///< Interrupt at least half of FIFO or 15ETU past from last receive 86 SCIF_UART_RECEIVE_TRIGGER_MAX, ///< Interrupt at almost full in FIFO or 15ETU past from last receive 87 SCIF_UART_RECEIVE_TRIGGER_1, ///< Interrupt at least 1 byte is in FIFO or 15ETU past from last receive 88 SCIF_UART_RECEIVE_TRIGGER_2, ///< Interrupt at least 2 bytes is in FIFO or 15ETU past from last receive 89 SCIF_UART_RECEIVE_TRIGGER_3, ///< Interrupt at least 3 bytes is in FIFO or 15ETU past from last receive 90 SCIF_UART_RECEIVE_TRIGGER_4, ///< Interrupt at least 4 bytes is in FIFO or 15ETU past from last receive 91 SCIF_UART_RECEIVE_TRIGGER_5, ///< Interrupt at least 5 bytes is in FIFO or 15ETU past from last receive 92 SCIF_UART_RECEIVE_TRIGGER_6, ///< Interrupt at least 6 bytes is in FIFO or 15ETU past from last receive 93 SCIF_UART_RECEIVE_TRIGGER_7, ///< Interrupt at least 7 bytes is in FIFO or 15ETU past from last receive 94 SCIF_UART_RECEIVE_TRIGGER_8, ///< Interrupt at least 8 bytes is in FIFO or 15ETU past from last receive 95 SCIF_UART_RECEIVE_TRIGGER_9, ///< Interrupt at least 9 bytes is in FIFO or 15ETU past from last receive 96 SCIF_UART_RECEIVE_TRIGGER_10, ///< Interrupt at least 10 bytes is in FIFO or 15ETU past from last receive 97 SCIF_UART_RECEIVE_TRIGGER_11, ///< Interrupt at least 11 bytes is in FIFO or 15ETU past from last receive 98 SCIF_UART_RECEIVE_TRIGGER_12, ///< Interrupt at least 12 bytes is in FIFO or 15ETU past from last receive 99 SCIF_UART_RECEIVE_TRIGGER_13, ///< Interrupt at least 13 bytes is in FIFO or 15ETU past from last receive 100 SCIF_UART_RECEIVE_TRIGGER_14, ///< Interrupt at least 14 bytes is in FIFO or 15ETU past from last receive 101 SCIF_UART_RECEIVE_TRIGGER_15, ///< Interrupt at least 15 bytes is in FIFO or 15ETU past from last receive 102 } scif_uart_receive_trigger_t; 103 104 /** RTS trigger level. */ 105 typedef enum e_scif_uart_rts_trigger 106 { 107 SCIF_UART_RTS_TRIGGER_1, ///< RTS trigger level = 1 108 SCIF_UART_RTS_TRIGGER_4, ///< RTS trigger level = 4 109 SCIF_UART_RTS_TRIGGER_6, ///< RTS trigger level = 6 110 SCIF_UART_RTS_TRIGGER_8, ///< RTS trigger level = 8 111 SCIF_UART_RTS_TRIGGER_10, ///< RTS trigger level = 10 112 SCIF_UART_RTS_TRIGGER_12, ///< RTS trigger level = 12 113 SCIF_UART_RTS_TRIGGER_14, ///< RTS trigger level = 14 114 SCIF_UART_RTS_TRIGGER_15, ///< RTS trigger level = 15 115 } scif_uart_rts_trigger_t; 116 117 /** UART instance control block. */ 118 typedef struct st_scif_uart_instance_ctrl 119 { 120 /* Parameters to control UART peripheral device */ 121 uint32_t open; // Used to determine if the channel is configured 122 123 bsp_io_port_pin_t driver_enable_pin; 124 125 /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ 126 uint8_t const * p_tx_src; 127 128 /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ 129 uint32_t tx_src_bytes; 130 131 /* Destination buffer pointer used for receiving data. */ 132 uint8_t * p_rx_dest; 133 134 /* Size of destination buffer pointer used for receiving data. */ 135 uint32_t rx_dest_bytes; 136 137 /* Pointer to the configuration block. */ 138 uart_cfg_t const * p_cfg; 139 140 /* Base register for this channel */ 141 R_SCIFA0_Type * p_reg; 142 143 /* Backup SPTR value for writing */ 144 uint16_t sptr; 145 146 void (* p_callback)(uart_callback_args_t * p_arg); // Pointer to callback 147 uart_callback_args_t * p_callback_memory; // Pointer to pre-allocated callback argument 148 149 /* Pointer to context to be passed into callback function */ 150 void const * p_context; 151 } scif_uart_instance_ctrl_t; 152 153 /** Register settings to achieve a desired baud rate and modulation duty. */ 154 typedef struct st_scif_baud_setting 155 { 156 struct 157 { 158 uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select 159 uint8_t brme : 1; ///< Bit Rate Modulation Enable 160 uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select 161 uint8_t cks : 2; ///< CKS value to get divisor (CKS = N) 162 } semr_baudrate_bits_b; 163 uint8_t brr; ///< Bit Rate Register setting 164 uint8_t mddr; ///< Modulation Duty Register setting 165 } scif_baud_setting_t; 166 167 /** Configuration settings for controlling the DE signal for RS-485. */ 168 typedef struct st_sci_uart_rs485_setting 169 { 170 sci_uart_rs485_enable_t enable; ///< Enable the DE signal. 171 sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. 172 bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin. 173 } sci_uart_rs485_setting_t; 174 175 /** UART on SCIF device Configuration */ 176 typedef struct st_scif_uart_extended_cfg 177 { 178 uint8_t bri_ipl; ///< Break interrupt priority 179 IRQn_Type bri_irq; ///< Break interrupt IRQ number 180 scif_clk_src_t clock; ///< The source clock for the baud-rate generator. 181 scif_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting 182 183 scif_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. 184 185 scif_uart_receive_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level. 186 scif_uart_rts_trigger_t rts_fifo_trigger; ///< RTS trigger level. 187 188 scif_uart_mode_t uart_mode; ///< UART communication mode selection 189 scif_uart_flow_control_t flow_control; ///< CTS/RTS function 190 sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. 191 } scif_uart_extended_cfg_t; 192 193 /********************************************************************************************************************** 194 * Exported global variables 195 **********************************************************************************************************************/ 196 197 /** @cond INC_HEADER_DEFS_SEC */ 198 /** Filled in Interface API structure for this Instance. */ 199 extern const uart_api_t g_uart_on_scif; 200 201 /** @endcond */ 202 203 fsp_err_t R_SCIF_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); 204 fsp_err_t R_SCIF_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); 205 fsp_err_t R_SCIF_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); 206 fsp_err_t R_SCIF_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); 207 fsp_err_t R_SCIF_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); 208 fsp_err_t R_SCIF_UART_Close(uart_ctrl_t * const p_api_ctrl); 209 fsp_err_t R_SCIF_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); 210 fsp_err_t R_SCIF_UART_BaudCalculate(uart_ctrl_t * const p_api_ctrl, 211 uint32_t baudrate, 212 bool bitrate_modulation, 213 uint32_t baud_rate_error_x_1000, 214 scif_baud_setting_t * const p_baud_setting); 215 fsp_err_t R_SCIF_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, 216 void ( * p_callback)(uart_callback_args_t * p_arg), 217 void const * const p_context, 218 uart_callback_args_t * const p_callback_memory); 219 fsp_err_t R_SCIF_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); 220 221 /*******************************************************************************************************************//** 222 * @} (end addtogroup SCIF_UART) 223 **********************************************************************************************************************/ 224 225 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 226 FSP_FOOTER 227 228 #endif /* R_SCIF_UART_H */ 229
