1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include "bsp_api.h"
8
9 /***********************************************************************************************************************
10 * Includes
11 **********************************************************************************************************************/
12 #include "r_qspi.h"
13
14 /***********************************************************************************************************************
15 * Macro definitions
16 **********************************************************************************************************************/
17 #define QSPI_PRV_OPEN (0x51535049)
18
19 #define QSPI_PRV_MASK_UPPER_4_BITS_OF_BYTE (0xF0U)
20 #define QSPI_PRV_MASK_LOWER_4_BITS_OF_BYTE (0x0FU)
21
22 #define QSPI_PRV_LSB_NIBBLE_CLEARED (0xEEEEEEEE)
23 #define QSPI_PRV_EVEN_BITS_CLEARED (0xAAAA)
24
25 /***********************************************************************************************************************
26 * Typedef definitions
27 **********************************************************************************************************************/
28
29 /* Number of address bytes in 4 byte address mode. */
30 #define QSPI_4_BYTE_ADDRESS (4U)
31
32 /***********************************************************************************************************************
33 * Private function prototypes
34 **********************************************************************************************************************/
35 #if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM
36
37 static void qspi_d0_byte_write_quad_mode(uint8_t byte);
38
39 static void qspi_d0_byte_write_dual_mode(uint8_t byte);
40
41 #endif
42
43 static void qspi_d0_byte_write_standard(uint8_t byte);
44
45 static void r_qspi_direct_write_sub(uint8_t const * const p_src, uint32_t const bytes, bool const read_after_write);
46
47 static void r_qspi_direct_read_sub(uint8_t * const p_dest, uint32_t const bytes);
48 static bool r_qspi_status_sub(qspi_instance_ctrl_t * p_instance_ctrl);
49
50 static fsp_err_t r_qspi_xip(qspi_instance_ctrl_t * p_instance_ctrl, uint8_t code, bool enter_mode);
51
52 #if QSPI_CFG_PARAM_CHECKING_ENABLE
53
54 static fsp_err_t r_qspi_param_checking_dcom(qspi_instance_ctrl_t * p_instance_ctrl);
55
56 static fsp_err_t qspi_program_param_check(qspi_instance_ctrl_t * p_instance_ctrl,
57 uint8_t const * const p_src,
58 uint8_t * const p_dest,
59 uint32_t byte_count);
60
61 #endif
62
63 /***********************************************************************************************************************
64 * Private global variables
65 **********************************************************************************************************************/
66
67 #if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM
68
69 /* Page program command. Index by [data_lines]. data_lines is 0 for 1 data line, 1 for 2 data lines, or
70 * 2 for 4 data lines. */
71 static void(*const gp_qspi_prv_byte_write[3]) (uint8_t byte) =
72 {
73 qspi_d0_byte_write_standard,
74 qspi_d0_byte_write_dual_mode,
75 qspi_d0_byte_write_quad_mode
76 };
77 #endif
78
79 /*******************************************************************************************************************//**
80 * @addtogroup QSPI
81 * @{
82 **********************************************************************************************************************/
83
84 /***********************************************************************************************************************
85 * Global Variables
86 **********************************************************************************************************************/
87
88 const spi_flash_api_t g_qspi_on_spi_flash =
89 {
90 .open = R_QSPI_Open,
91 .directWrite = R_QSPI_DirectWrite,
92 .directRead = R_QSPI_DirectRead,
93 .directTransfer = R_QSPI_DirectTransfer,
94 .spiProtocolSet = R_QSPI_SpiProtocolSet,
95 .write = R_QSPI_Write,
96 .erase = R_QSPI_Erase,
97 .statusGet = R_QSPI_StatusGet,
98 .xipEnter = R_QSPI_XipEnter,
99 .xipExit = R_QSPI_XipExit,
100 .bankSet = R_QSPI_BankSet,
101 .autoCalibrate = R_QSPI_AutoCalibrate,
102 .close = R_QSPI_Close,
103 };
104
105 /***********************************************************************************************************************
106 * Functions
107 **********************************************************************************************************************/
108
109 /*******************************************************************************************************************//**
110 * Open the QSPI driver module. After the driver is open, the QSPI can be accessed like internal flash memory starting
111 * at address 0x60000000.
112 *
113 * Implements @ref spi_flash_api_t::open.
114 *
115 * @retval FSP_SUCCESS Configuration was successful.
116 * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl or p_cfg is NULL.
117 * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with the same p_instance_ctrl.
118 **********************************************************************************************************************/
R_QSPI_Open(spi_flash_ctrl_t * p_ctrl,spi_flash_cfg_t const * const p_cfg)119 fsp_err_t R_QSPI_Open (spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg)
120 {
121 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
122
123 #if QSPI_CFG_PARAM_CHECKING_ENABLE
124 FSP_ASSERT(NULL != p_instance_ctrl);
125 FSP_ASSERT(NULL != p_cfg);
126 FSP_ERROR_RETURN(QSPI_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
127 FSP_ASSERT((p_cfg->dummy_clocks >= SPI_FLASH_DUMMY_CLOCKS_3 && p_cfg->dummy_clocks <= SPI_FLASH_DUMMY_CLOCKS_17) ||
128 p_cfg->dummy_clocks == SPI_FLASH_DUMMY_CLOCKS_DEFAULT);
129 #endif
130
131 /* Enable clock to the QSPI block */
132 R_BSP_MODULE_START(FSP_IP_QSPI, 0U);
133
134 qspi_extended_cfg_t * p_cfg_extend = (qspi_extended_cfg_t *) p_cfg->p_extend;
135
136 /* Initialized unused registers. */
137 R_QSPI->SFMCST = 0U;
138 R_QSPI->SFMSIC = 0U;
139 R_QSPI->SFMPMD = 0U;
140 R_QSPI->SFMCNT1 = 0U;
141
142 /* Set the initial SPI protocol. */
143 R_QSPI->SFMSPC = R_QSPI_SFMSPC_SFMSDE_Msk | p_cfg->spi_protocol;
144
145 /* Set the SPI clock rate */
146 R_QSPI->SFMSKC = p_cfg_extend->qspclk_div;
147
148 /* Set the address mode. */
149 R_QSPI->SFMSAC = p_cfg->address_bytes;
150
151 uint32_t dummy_clocks = 0;
152 if (SPI_FLASH_DUMMY_CLOCKS_DEFAULT != p_cfg->dummy_clocks)
153 {
154 /* Convert dummy cycles setting to the register value. */
155 dummy_clocks = (uint32_t) p_cfg->dummy_clocks - 2U;
156 }
157
158 /* Set the number of dummy cycles in QSPI peripheral */
159 R_QSPI->SFMSDC = dummy_clocks | R_QSPI_SFMSDC_SFMXD_Msk;
160
161 /* Set configured minimum high level width for QSSL signal. */
162 R_QSPI->SFMSSC = p_cfg_extend->min_qssl_deselect_cycles | R_QSPI_SFMSSC_SFMSLD_Msk | R_QSPI_SFMSSC_SFMSHD_Msk;
163
164 /* Set the read mode based on user configuration. */
165 R_QSPI->SFMSMD = R_QSPI_SFMSMD_SFMPFE_Msk | p_cfg->read_mode;
166
167 /* Initialize control block. */
168 p_instance_ctrl->p_cfg = p_cfg;
169
170 /* This is the index into g_qspi_prv_program_command. The index should be 0 for data on one line, 1 for data on
171 * 2 lines, and 2 for data on 4 lines. */
172 if (SPI_FLASH_READ_MODE_STANDARD == p_cfg->read_mode)
173 {
174 p_instance_ctrl->data_lines = SPI_FLASH_DATA_LINES_1;
175 }
176 else
177 {
178 p_instance_ctrl->data_lines = (spi_flash_data_lines_t) (31 - __CLZ(p_cfg->read_mode));
179 }
180
181 /* The memory size is read from the device if needed. */
182 p_instance_ctrl->total_size_bytes = 0U;
183
184 p_instance_ctrl->open = QSPI_PRV_OPEN;
185
186 return FSP_SUCCESS;
187 }
188
189 /*******************************************************************************************************************//**
190 * Writes raw data directly to the QSPI.
191 *
192 * Implements @ref spi_flash_api_t::directWrite.
193 *
194 * @retval FSP_SUCCESS The flash was programmed successfully.
195 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
196 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
197 * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled.
198 * @retval FSP_ERR_DEVICE_BUSY The device is busy.
199 **********************************************************************************************************************/
R_QSPI_DirectWrite(spi_flash_ctrl_t * p_ctrl,uint8_t const * const p_src,uint32_t const bytes,bool const read_after_write)200 fsp_err_t R_QSPI_DirectWrite (spi_flash_ctrl_t * p_ctrl,
201 uint8_t const * const p_src,
202 uint32_t const bytes,
203 bool const read_after_write)
204 {
205 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
206
207 #if QSPI_CFG_PARAM_CHECKING_ENABLE
208 fsp_err_t err = r_qspi_param_checking_dcom(p_instance_ctrl);
209 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
210 FSP_ASSERT(NULL != p_src);
211 FSP_ASSERT(bytes > 0);
212 #else
213 FSP_PARAMETER_NOT_USED(p_instance_ctrl);
214 #endif
215
216 /* Write data to QSPI. */
217 r_qspi_direct_write_sub(p_src, bytes, read_after_write);
218
219 return FSP_SUCCESS;
220 }
221
222 /*******************************************************************************************************************//**
223 * Reads raw data directly from the QSPI. This API can only be called after R_QSPI_DirectWrite with read_after_write
224 * set to true.
225 *
226 * Implements @ref spi_flash_api_t::directRead.
227 *
228 * @retval FSP_SUCCESS The flash was programmed successfully.
229 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
230 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
231 * @retval FSP_ERR_INVALID_MODE This function must be called after R_QSPI_DirectWrite with read_after_write set
232 * to true.
233 **********************************************************************************************************************/
R_QSPI_DirectRead(spi_flash_ctrl_t * p_ctrl,uint8_t * const p_dest,uint32_t const bytes)234 fsp_err_t R_QSPI_DirectRead (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes)
235 {
236 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
237
238 #if QSPI_CFG_PARAM_CHECKING_ENABLE
239 FSP_ASSERT(NULL != p_instance_ctrl);
240
241 FSP_ASSERT(NULL != p_dest);
242 FSP_ASSERT(bytes > 0);
243 FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
244
245 /* This API can only be called after R_QSPI_DirectWrite with the read_after_write parameter set to true. The QSPI
246 * peripheral must already be in direct communications mode. */
247 FSP_ERROR_RETURN(1U == R_QSPI->SFMCMD, FSP_ERR_INVALID_MODE);
248 #else
249 FSP_PARAMETER_NOT_USED(p_instance_ctrl);
250 #endif
251
252 /* Read data from QSPI. */
253 r_qspi_direct_read_sub(p_dest, bytes);
254
255 return FSP_SUCCESS;
256 }
257
258 /*******************************************************************************************************************//**
259 * Read/Write raw data directly with the OctaFlash/OctaRAM device. Unsupported by QSPI.
260 *
261 * Implements @ref spi_flash_api_t::directTransfer.
262 *
263 * @retval FSP_ERR_UNSUPPORTED API not supported by QSPI.
264 **********************************************************************************************************************/
R_QSPI_DirectTransfer(spi_flash_ctrl_t * p_ctrl,spi_flash_direct_transfer_t * const p_transfer,spi_flash_direct_transfer_dir_t direction)265 fsp_err_t R_QSPI_DirectTransfer (spi_flash_ctrl_t * p_ctrl,
266 spi_flash_direct_transfer_t * const p_transfer,
267 spi_flash_direct_transfer_dir_t direction)
268 {
269 FSP_PARAMETER_NOT_USED(p_ctrl);
270 FSP_PARAMETER_NOT_USED(p_transfer);
271 FSP_PARAMETER_NOT_USED(direction);
272
273 return FSP_ERR_UNSUPPORTED;
274 }
275
276 /*******************************************************************************************************************//**
277 * Enters XIP (execute in place) mode.
278 *
279 * Implements @ref spi_flash_api_t::xipEnter.
280 *
281 * @retval FSP_SUCCESS The flash was programmed successfully.
282 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
283 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
284 **********************************************************************************************************************/
R_QSPI_XipEnter(spi_flash_ctrl_t * p_ctrl)285 fsp_err_t R_QSPI_XipEnter (spi_flash_ctrl_t * p_ctrl)
286 {
287 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
288 fsp_err_t err;
289 err = r_qspi_xip(p_instance_ctrl, p_instance_ctrl->p_cfg->xip_enter_command, true);
290 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
291
292 return FSP_SUCCESS;
293 }
294
295 /*******************************************************************************************************************//**
296 * Exits XIP (execute in place) mode.
297 *
298 * Implements @ref spi_flash_api_t::xipExit.
299 *
300 * @retval FSP_SUCCESS The flash was programmed successfully.
301 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
302 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
303 **********************************************************************************************************************/
R_QSPI_XipExit(spi_flash_ctrl_t * p_ctrl)304 fsp_err_t R_QSPI_XipExit (spi_flash_ctrl_t * p_ctrl)
305 {
306 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
307 fsp_err_t err;
308 err = r_qspi_xip(p_instance_ctrl, p_instance_ctrl->p_cfg->xip_exit_command, false);
309 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
310
311 return FSP_SUCCESS;
312 }
313
314 /*******************************************************************************************************************//**
315 * Program a page of data to the flash.
316 *
317 * Implements @ref spi_flash_api_t::write.
318 *
319 * @retval FSP_SUCCESS The flash was programmed successfully.
320 * @retval FSP_ERR_ASSERTION p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
321 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
322 * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled.
323 * @retval FSP_ERR_DEVICE_BUSY The device is busy.
324 **********************************************************************************************************************/
R_QSPI_Write(spi_flash_ctrl_t * p_ctrl,uint8_t const * const p_src,uint8_t * const p_dest,uint32_t byte_count)325 fsp_err_t R_QSPI_Write (spi_flash_ctrl_t * p_ctrl,
326 uint8_t const * const p_src,
327 uint8_t * const p_dest,
328 uint32_t byte_count)
329 {
330 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
331
332 #if QSPI_CFG_PARAM_CHECKING_ENABLE
333 fsp_err_t err = qspi_program_param_check(p_instance_ctrl, p_src, p_dest, byte_count);
334 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
335 #endif
336
337 uint32_t chip_address = (uint32_t) p_dest - (uint32_t) QSPI_DEVICE_START_ADDRESS + R_QSPI->SFMCNT1;
338
339 bool restore_spi_mode = false;
340 void (* write_command)(uint8_t byte) = qspi_d0_byte_write_standard;
341 void (* write_address)(uint8_t byte) = qspi_d0_byte_write_standard;
342
343 #if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM
344
345 /* If the peripheral is in extended SPI mode, and the configuration provided in the BSP allows for programming on
346 * multiple data lines, and a unique command is provided for the required mode, update the SPI protocol to send
347 * data on multiple lines. */
348 if ((SPI_FLASH_DATA_LINES_1 != p_instance_ctrl->data_lines) &&
349 (SPI_FLASH_PROTOCOL_EXTENDED_SPI == R_QSPI->SFMSPC_b.SFMSPI))
350 {
351 R_QSPI->SFMSPC_b.SFMSPI = p_instance_ctrl->data_lines;
352
353 restore_spi_mode = true;
354
355 /* Write command in extended SPI mode on one line. */
356 write_command = gp_qspi_prv_byte_write[p_instance_ctrl->data_lines];
357
358 if (SPI_FLASH_DATA_LINES_1 == p_instance_ctrl->p_cfg->page_program_address_lines)
359 {
360 /* Write address in extended SPI mode on one line. */
361 write_address = gp_qspi_prv_byte_write[p_instance_ctrl->data_lines];
362 }
363 }
364 #endif
365
366 /* Enter Direct Communication mode */
367 R_QSPI->SFMCMD = 1;
368
369 /* Send command to enable writing */
370 write_command(p_instance_ctrl->p_cfg->write_enable_command);
371
372 /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
373 * in the RA6M3 manual R01UH0886EJ0100. */
374 R_QSPI->SFMCMD = 1;
375
376 /* Send command to write data */
377 write_command(p_instance_ctrl->p_cfg->page_program_command);
378
379 /* Write the address. */
380 if ((p_instance_ctrl->p_cfg->address_bytes & R_QSPI_SFMSAC_SFMAS_Msk) == SPI_FLASH_ADDRESS_BYTES_4)
381 {
382 /* Send the most significant byte of the address */
383 write_address((uint8_t) (chip_address >> 24));
384 }
385
386 /* Send the remaining bytes of the address */
387 write_address((uint8_t) (chip_address >> 16));
388 write_address((uint8_t) (chip_address >> 8));
389 write_address((uint8_t) (chip_address));
390
391 /* Write the data. */
392 uint32_t index = 0;
393 while (index < byte_count)
394 {
395 /* Read the device memory into the passed in buffer */
396 R_QSPI->SFMCOM = p_src[index];
397 index++;
398 }
399
400 /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
401 * in the RA6M3 manual R01UH0886EJ0100. */
402 R_QSPI->SFMCMD = 1;
403
404 /* If the SPI protocol was modified in this function, restore it. */
405 if (restore_spi_mode)
406 {
407 /* Restore SPI mode to extended SPI mode. */
408 R_QSPI->SFMSPC_b.SFMSPI = SPI_FLASH_PROTOCOL_EXTENDED_SPI;
409 }
410
411 /* Return to ROM access mode */
412 R_QSPI->SFMCMD = 0;
413
414 return FSP_SUCCESS;
415 }
416
417 /*******************************************************************************************************************//**
418 * Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t.
419 * For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.
420 *
421 * Implements @ref spi_flash_api_t::erase.
422 *
423 * @retval FSP_SUCCESS The command to erase the flash was executed successfully.
424 * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_device_address is NULL, or byte_count doesn't match an erase
425 * size defined in spi_flash_cfg_t, or device is in XIP mode.
426 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
427 * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled.
428 * @retval FSP_ERR_DEVICE_BUSY The device is busy.
429 **********************************************************************************************************************/
R_QSPI_Erase(spi_flash_ctrl_t * p_ctrl,uint8_t * const p_device_address,uint32_t byte_count)430 fsp_err_t R_QSPI_Erase (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count)
431 {
432 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
433
434 #if QSPI_CFG_PARAM_CHECKING_ENABLE
435 fsp_err_t err = r_qspi_param_checking_dcom(p_instance_ctrl);
436 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
437 FSP_ASSERT(NULL != p_device_address);
438 #endif
439
440 uint16_t erase_command = 0;
441 uint32_t chip_address = (uint32_t) p_device_address - QSPI_DEVICE_START_ADDRESS + R_QSPI->SFMCNT1;
442 bool send_address = true;
443
444 for (uint32_t index = 0; index < p_instance_ctrl->p_cfg->erase_command_list_length; index++)
445 {
446 /* If requested byte_count is supported by underlying flash, store the command. */
447 if (byte_count == p_instance_ctrl->p_cfg->p_erase_command_list[index].size)
448 {
449 if (SPI_FLASH_ERASE_SIZE_CHIP_ERASE == byte_count)
450 {
451 /* Don't send address for chip erase. */
452 send_address = false;
453 }
454
455 erase_command = p_instance_ctrl->p_cfg->p_erase_command_list[index].command;
456 break;
457 }
458 }
459
460 #if QSPI_CFG_PARAM_CHECKING_ENABLE
461 FSP_ASSERT(0U != erase_command);
462 #endif
463
464 /* Enter direct communication mode */
465 R_QSPI->SFMCMD = 1U;
466
467 /* Enable write. */
468 R_QSPI->SFMCOM = p_instance_ctrl->p_cfg->write_enable_command;
469
470 /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
471 * in the RA6M3 manual R01UH0886EJ0100. */
472 R_QSPI->SFMCMD = 1U;
473
474 /* Send erase command. */
475 R_QSPI->SFMCOM = erase_command;
476
477 /* Send address if this is not a chip erase command. */
478 if (send_address)
479 {
480 if ((p_instance_ctrl->p_cfg->address_bytes & R_QSPI_SFMSAC_SFMAS_Msk) == SPI_FLASH_ADDRESS_BYTES_4)
481 {
482 R_QSPI->SFMCOM = (uint8_t) (chip_address >> 24);
483 }
484
485 R_QSPI->SFMCOM = (uint8_t) (chip_address >> 16);
486 R_QSPI->SFMCOM = (uint8_t) (chip_address >> 8);
487 R_QSPI->SFMCOM = (uint8_t) (chip_address);
488 }
489
490 /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
491 * in the RA6M3 manual R01UH0886EJ0100. */
492 R_QSPI->SFMCMD = 1U;
493
494 /* Exit direct communication mode */
495 R_QSPI->SFMCMD = 0U;
496
497 return FSP_SUCCESS;
498 }
499
500 /*******************************************************************************************************************//**
501 * Gets the write or erase status of the flash.
502 *
503 * Implements @ref spi_flash_api_t::statusGet.
504 *
505 * @retval FSP_SUCCESS The write status is in p_status.
506 * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_status is NULL.
507 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
508 * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled.
509 **********************************************************************************************************************/
R_QSPI_StatusGet(spi_flash_ctrl_t * p_ctrl,spi_flash_status_t * const p_status)510 fsp_err_t R_QSPI_StatusGet (spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status)
511 {
512 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
513
514 #if QSPI_CFG_PARAM_CHECKING_ENABLE
515 FSP_ASSERT(NULL != p_instance_ctrl);
516 FSP_ASSERT(NULL != p_status);
517 FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
518
519 /* Do not enter direct communication mode from XIP mode. Reference note in section 39.10.2 "Using Direct
520 * Communication Mode" in the RA6M3 manual R01UH0886EJ0100. */
521 FSP_ERROR_RETURN(0U == R_QSPI->SFMSDC_b.SFMXST, FSP_ERR_INVALID_MODE);
522 #endif
523
524 /* Read device status. */
525 p_status->write_in_progress = r_qspi_status_sub(p_instance_ctrl);
526
527 return FSP_SUCCESS;
528 }
529
530 /*******************************************************************************************************************//**
531 * Selects the bank to access. A bank is a 64MB sliding access window into the QSPI device flash memory space. To access
532 * chip address 0x4000000, select bank 1, then read from internal flash address 0x60000000. To access chip address
533 * 0x8001000, select bank 2, then read from internal flash address 0x60001000.
534 *
535 * This function is not required for memory devices less than or equal to 512 Mb (64MB).
536 *
537 * Implements @ref spi_flash_api_t::bankSet.
538 *
539 * @retval FSP_SUCCESS Bank successfully selected.
540 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
541 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
542 **********************************************************************************************************************/
R_QSPI_BankSet(spi_flash_ctrl_t * p_ctrl,uint32_t bank)543 fsp_err_t R_QSPI_BankSet (spi_flash_ctrl_t * p_ctrl, uint32_t bank)
544 {
545 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
546
547 #if QSPI_CFG_PARAM_CHECKING_ENABLE
548 FSP_ASSERT(NULL != p_instance_ctrl);
549 FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
550 #else
551 FSP_PARAMETER_NOT_USED(p_instance_ctrl);
552 #endif
553
554 /* Select the requested bank. */
555 R_QSPI->SFMCNT1 = bank << R_QSPI_SFMCNT1_QSPI_EXT_Pos;
556
557 return FSP_SUCCESS;
558 }
559
560 /*******************************************************************************************************************//**
561 * Sets the SPI protocol.
562 *
563 * Implements @ref spi_flash_api_t::spiProtocolSet.
564 *
565 * @retval FSP_SUCCESS SPI protocol updated on MCU peripheral.
566 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
567 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
568 * @retval FSP_ERR_INVALID_ARGUMENT Invalid SPI protocol requested.
569 **********************************************************************************************************************/
R_QSPI_SpiProtocolSet(spi_flash_ctrl_t * p_ctrl,spi_flash_protocol_t spi_protocol)570 fsp_err_t R_QSPI_SpiProtocolSet (spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol)
571 {
572 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
573
574 #if QSPI_CFG_PARAM_CHECKING_ENABLE
575 FSP_ASSERT(NULL != p_instance_ctrl);
576 FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
577 FSP_ERROR_RETURN(SPI_FLASH_PROTOCOL_QPI >= spi_protocol, FSP_ERR_INVALID_ARGUMENT);
578 #else
579 FSP_PARAMETER_NOT_USED(p_instance_ctrl);
580 #endif
581
582 /* Update the SPI protocol. */
583
584 /* The cast is used to prevent a warning that not all values of spi_flash_protocol_t fit in SFMSPI. spi_protocol is
585 * verified to fit in SFMSPI in parameter checking above. */
586 R_QSPI->SFMSPC_b.SFMSPI = (uint32_t) spi_protocol & 3U;
587
588 return FSP_SUCCESS;
589 }
590
591 /*******************************************************************************************************************//**
592 * Auto-calibrate the OctaRAM device using the preamble pattern. Unsupported by QSPI.
593 * Implements @ref spi_flash_api_t::autoCalibrate.
594 *
595 * @retval FSP_ERR_UNSUPPORTED API not supported by QSPI
596 **********************************************************************************************************************/
R_QSPI_AutoCalibrate(spi_flash_ctrl_t * p_ctrl)597 fsp_err_t R_QSPI_AutoCalibrate (spi_flash_ctrl_t * p_ctrl)
598 {
599 FSP_PARAMETER_NOT_USED(p_ctrl);
600
601 return FSP_ERR_UNSUPPORTED;
602 }
603
604 /*******************************************************************************************************************//**
605 * Close the QSPI driver module.
606 *
607 * Implements @ref spi_flash_api_t::close.
608 *
609 * @retval FSP_SUCCESS Configuration was successful.
610 * @retval FSP_ERR_ASSERTION p_instance_ctrl is NULL.
611 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
612 **********************************************************************************************************************/
R_QSPI_Close(spi_flash_ctrl_t * p_ctrl)613 fsp_err_t R_QSPI_Close (spi_flash_ctrl_t * p_ctrl)
614 {
615 qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl;
616
617 #if QSPI_CFG_PARAM_CHECKING_ENABLE
618 FSP_ASSERT(NULL != p_instance_ctrl);
619 FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
620 #endif
621
622 p_instance_ctrl->open = 0U;
623
624 /* Disable clock to the QSPI block */
625 R_BSP_MODULE_STOP(FSP_IP_QSPI, 0U);
626
627 return FSP_SUCCESS;
628 }
629
630 /*******************************************************************************************************************//**
631 * @} (end addtogroup QSPI)
632 **********************************************************************************************************************/
633
634 /*******************************************************************************************************************//**
635 * Enters or exits XIP (execute in place) mode.
636 *
637 * @param[in] p_instance_ctrl Pointer to a driver handle
638 * @param[in] code Code to place in M7-M0
639 * @param[in] enter_mode True to enter, false to exit
640 *
641 * @retval FSP_SUCCESS The flash was programmed successfully.
642 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
643 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
644 **********************************************************************************************************************/
r_qspi_xip(qspi_instance_ctrl_t * p_instance_ctrl,uint8_t code,bool enter_mode)645 static fsp_err_t r_qspi_xip (qspi_instance_ctrl_t * p_instance_ctrl, uint8_t code, bool enter_mode)
646 {
647 #if QSPI_CFG_PARAM_CHECKING_ENABLE
648
649 /* FSP_ASSERT(NULL != p_instance_ctrl) is optimized out when it shouldn't be. It appears to be affected by GCC bug
650 * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90949. */
651 qspi_instance_ctrl_t * volatile p_volatile_ctrl = p_instance_ctrl;
652 FSP_ASSERT(NULL != p_volatile_ctrl);
653 FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
654 #endif
655
656 volatile uint8_t i = 0;
657
658 FSP_PARAMETER_NOT_USED(i);
659
660 uint32_t dummy_clocks = 0;
661 if (SPI_FLASH_DUMMY_CLOCKS_DEFAULT != p_instance_ctrl->p_cfg->dummy_clocks)
662 {
663 /* Convert dummy cycles setting to the register value. */
664 dummy_clocks = (uint32_t) p_instance_ctrl->p_cfg->dummy_clocks - 2U;
665 }
666
667 R_QSPI->SFMSDC = (uint32_t) (code << R_QSPI_SFMSDC_SFMXD_Pos) |
668 (uint32_t) (enter_mode << R_QSPI_SFMSDC_SFMXEN_Pos) |
669 dummy_clocks;
670
671 /* Read from QSPI to send the XIP entry request. */
672 i = *(volatile uint8_t *) QSPI_DEVICE_START_ADDRESS;
673
674 /* Wait for the controller to XIP mode status to update. To confirm completion of the XIP mode enter/exit procedure,
675 * read 1/0 from the SFMXST bit in the SFMSDC register. Reference section 39.8.1 "Selecting the XIP Mode" and
676 * section 39.8.2 "Releasing the XIP Mode" in the RA6M3 manual R01UH0886EJ0100. */
677 FSP_HARDWARE_REGISTER_WAIT(R_QSPI->SFMSDC_b.SFMXST, (uint32_t) enter_mode);
678
679 return FSP_SUCCESS;
680 }
681
682 /*******************************************************************************************************************//**
683 * Gets device status.
684 *
685 * @param[in] p_instance_ctrl Pointer to a driver handle
686 *
687 * @return True if busy, false if not.
688 **********************************************************************************************************************/
r_qspi_status_sub(qspi_instance_ctrl_t * p_instance_ctrl)689 static bool r_qspi_status_sub (qspi_instance_ctrl_t * p_instance_ctrl)
690 {
691 /* Enter direct communication mode */
692 R_QSPI->SFMCMD = 1U;
693
694 R_QSPI->SFMCOM = p_instance_ctrl->p_cfg->status_command;
695 bool status = (R_QSPI->SFMCOM >> p_instance_ctrl->p_cfg->write_status_bit) & 1;
696
697 /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
698 * in the RA6M3 manual R01UH0886EJ0100. */
699 R_QSPI->SFMCMD = 1U;
700
701 /* Exit direct communication mode */
702 R_QSPI->SFMCMD = 0U;
703
704 return status;
705 }
706
707 /*******************************************************************************************************************//**
708 * Writes raw data to QSPI.
709 *
710 * @param[in] p_src Pointer to data to write
711 * @param[in] bytes Number of bytes to write
712 * @param[in] read_after_write Whether or not to close SPI bus cycle
713 **********************************************************************************************************************/
r_qspi_direct_write_sub(uint8_t const * const p_src,uint32_t const bytes,bool const read_after_write)714 static void r_qspi_direct_write_sub (uint8_t const * const p_src, uint32_t const bytes, bool const read_after_write)
715 {
716 /* Enter direct communication mode */
717 R_QSPI->SFMCMD = 1U;
718
719 /* Write data to QSPI. */
720 for (uint32_t i = 0; i < bytes; i++)
721 {
722 R_QSPI->SFMCOM = p_src[i];
723 }
724
725 if (!read_after_write)
726 {
727 /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct
728 * Communication" in the RA6M3 manual R01UH0886EJ0100. */
729 R_QSPI->SFMCMD = 1U;
730
731 /* Return to ROM access mode */
732 R_QSPI->SFMCMD = 0U;
733 }
734 }
735
736 /*******************************************************************************************************************//**
737 * Reads raw data from QSPI.
738 *
739 * @param[in] p_dest Pointer to store data
740 * @param[in] bytes Number of bytes to read
741 **********************************************************************************************************************/
r_qspi_direct_read_sub(uint8_t * const p_dest,uint32_t const bytes)742 static void r_qspi_direct_read_sub (uint8_t * const p_dest, uint32_t const bytes)
743 {
744 /* Read data from QSPI. */
745 for (uint32_t i = 0; i < bytes; i++)
746 {
747 p_dest[i] = (uint8_t) R_QSPI->SFMCOM;
748 }
749
750 /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct
751 * Communication" in the RA6M3 manual R01UH0886EJ0100. */
752 R_QSPI->SFMCMD = 1U;
753
754 /* Return to ROM access mode */
755 R_QSPI->SFMCMD = 0U;
756 }
757
758 #if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM
759
760 /*******************************************************************************************************************//**
761 * Writes a byte in extended SPI mode when the QSPI peripheral is configured for quad mode.
762 *
763 * @param[in] byte Byte to write
764 **********************************************************************************************************************/
qspi_d0_byte_write_quad_mode(uint8_t byte)765 static void qspi_d0_byte_write_quad_mode (uint8_t byte)
766 {
767 /* The LSB of each nibble ends up on D0. */
768 uint32_t value = QSPI_PRV_LSB_NIBBLE_CLEARED;
769 for (uint32_t i = 0U; i < 8U; i++)
770 {
771 uint32_t bit = ((uint32_t) (byte >> i) & 1U);
772
773 /* Place bits in every 4th bit (bit 0, 4, 8, ... 28). */
774 uint32_t bit_mask = bit << (i * 4U);
775
776 value |= bit_mask;
777 }
778
779 R_QSPI->SFMCOM = (uint8_t) (value >> 24U);
780 R_QSPI->SFMCOM = (uint8_t) (value >> 16U);
781 R_QSPI->SFMCOM = (uint8_t) (value >> 8U);
782 R_QSPI->SFMCOM = (uint8_t) value;
783 }
784
785 #endif
786
787 #if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM
788
789 /*******************************************************************************************************************//**
790 * Writes a byte in extended SPI mode when the QSPI peripheral is configured for dual mode.
791 *
792 * @param[in] byte Byte to write
793 **********************************************************************************************************************/
qspi_d0_byte_write_dual_mode(uint8_t byte)794 static void qspi_d0_byte_write_dual_mode (uint8_t byte)
795 {
796 /* Every other bit ends up on D0. Unused bits are set. */
797 uint16_t value = QSPI_PRV_EVEN_BITS_CLEARED;
798 for (uint32_t i = 0U; i < 8U; i++)
799 {
800 uint16_t bit = ((uint16_t) (byte >> i) & 1U);
801
802 /* Place bits in every other bit (bit 0, 2, 4 ... 14). */
803 uint16_t bit_mask = (uint16_t) (bit << (i * 2U));
804
805 value |= bit_mask;
806 }
807
808 R_QSPI->SFMCOM = (uint8_t) (value >> 8U);
809 R_QSPI->SFMCOM = (uint8_t) value;
810 }
811
812 #endif
813
814 /*******************************************************************************************************************//**
815 * Writes a byte in the SPI mode configured in the QSPI peripheral.
816 *
817 * @param[in] byte Byte to write
818 **********************************************************************************************************************/
qspi_d0_byte_write_standard(uint8_t byte)819 static void qspi_d0_byte_write_standard (uint8_t byte)
820 {
821 R_QSPI->SFMCOM = byte;
822 }
823
824 #if QSPI_CFG_PARAM_CHECKING_ENABLE
825
826 /*******************************************************************************************************************//**
827 * Parameter checking.
828 *
829 * @param[in] p_instance_ctrl Pointer to a driver handle
830 *
831 * @retval FSP_SUCCESS Device size stored in p_device_size_bytes
832 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
833 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
834 * @retval FSP_ERR_DEVICE_BUSY The device is busy.
835 * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled.
836 **********************************************************************************************************************/
r_qspi_param_checking_dcom(qspi_instance_ctrl_t * p_instance_ctrl)837 static fsp_err_t r_qspi_param_checking_dcom (qspi_instance_ctrl_t * p_instance_ctrl)
838 {
839 FSP_ASSERT(NULL != p_instance_ctrl);
840 FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
841
842 /* Do not enter direct communication mode from XIP mode. Reference note in section 39.10.2 "Using Direct
843 * Communication Mode" in the RA6M3 manual R01UH0886EJ0100. */
844 FSP_ERROR_RETURN(0U == R_QSPI->SFMSDC_b.SFMXST, FSP_ERR_INVALID_MODE);
845
846 /* Verify device is not busy. */
847 FSP_ERROR_RETURN(!r_qspi_status_sub(p_instance_ctrl), FSP_ERR_DEVICE_BUSY);
848
849 return FSP_SUCCESS;
850 }
851
852 #endif
853
854 #if QSPI_CFG_PARAM_CHECKING_ENABLE
855
856 /*******************************************************************************************************************//**
857 * Parameter checking for R_QSPI_Write.
858 *
859 * @param[in] p_instance_ctrl Pointer to a driver handle
860 * @param[in] p_src The source of the data to write to QSPI
861 * @param[in] p_dest The address in QSPI to write to
862 * @param[in] byte_count The number of bytes to write
863 *
864 * @retval FSP_SUCCESS Parameters are valid.
865 * @retval FSP_ERR_ASSERTION p_instance_ctrl,p_device_address or p_memory_address is NULL.
866 * @retval FSP_ERR_NOT_OPEN Driver is not opened.
867 * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled.
868 * @retval FSP_ERR_DEVICE_BUSY The device is busy.
869 **********************************************************************************************************************/
qspi_program_param_check(qspi_instance_ctrl_t * p_instance_ctrl,uint8_t const * const p_src,uint8_t * const p_dest,uint32_t byte_count)870 static fsp_err_t qspi_program_param_check (qspi_instance_ctrl_t * p_instance_ctrl,
871 uint8_t const * const p_src,
872 uint8_t * const p_dest,
873 uint32_t byte_count)
874 {
875 fsp_err_t err = r_qspi_param_checking_dcom(p_instance_ctrl);
876 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
877 FSP_ASSERT(NULL != p_src);
878 FSP_ASSERT(NULL != p_dest);
879
880 /* Check if byte_count is valid */
881 uint32_t page_size_bytes = p_instance_ctrl->p_cfg->page_size_bytes;
882 uint32_t bytes_left_in_page = page_size_bytes - ((uint32_t) p_dest % page_size_bytes);
883 FSP_ASSERT(byte_count <= bytes_left_in_page);
884
885 return FSP_SUCCESS;
886 }
887
888 #endif
889
