1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*********************************************************************************************************************** 8 * Includes 9 **********************************************************************************************************************/ 10 #include "r_mipi_phy.h" 11 12 /*********************************************************************************************************************** 13 * Macro definitions 14 **********************************************************************************************************************/ 15 #define MIPI_PHY_OPEN (0x4D504950) 16 17 #define MIPI_DSI_PRV_1MHZ (1000000) 18 19 /*********************************************************************************************************************** 20 * Typedef definitions 21 **********************************************************************************************************************/ 22 23 /*********************************************************************************************************************** 24 * Global variables 25 **********************************************************************************************************************/ 26 27 const mipi_phy_api_t g_mipi_phy = 28 { 29 .open = r_mipi_phy_open, 30 .close = r_mipi_phy_close, 31 }; 32 33 /*********************************************************************************************************************** 34 * Private function prototypes 35 **********************************************************************************************************************/ 36 37 /*******************************************************************************************************************//** 38 * @addtogroup MIPI_PHY 39 * @{ 40 **********************************************************************************************************************/ 41 42 /*********************************************************************************************************************** 43 * Functions 44 **********************************************************************************************************************/ 45 46 /********************************************************************************************************************** 47 * Initialize the MIPI DSI peripheral according to section 57.3.1 D-PHY Start-up Procedure, R01UH0995EJ0060 48 * 49 * @retval FSP_SUCCESS The channel was successfully opened. 50 * @retval FSP_ERR_ASSERTION One or both of the parameters was NULL. 51 * @retval FSP_ERR_ALREADY_OPEN The instance is already opened. 52 * @retval FSP_ERR_INVALID_MODE Power control mode must be high-speed-mode. 53 **********************************************************************************************************************/ r_mipi_phy_open(mipi_phy_ctrl_t * const p_api_ctrl,mipi_phy_cfg_t const * const p_cfg)54fsp_err_t r_mipi_phy_open (mipi_phy_ctrl_t * const p_api_ctrl, mipi_phy_cfg_t const * const p_cfg) 55 { 56 mipi_phy_ctrl_t * p_ctrl = p_api_ctrl; 57 58 /* Set DPHYREFCR to match PCLKA */ 59 uint32_t pclka_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKA); 60 R_DPHYCNT->DPHYREFCR_b.RFREQ = (uint8_t) ((pclka_hz / MIPI_DSI_PRV_1MHZ) - 1); 61 62 /* Start D-PHY LDO and wait for startup */ 63 R_DPHYCNT->DPHYPWRCR_b.PWRSEN = 1; 64 FSP_HARDWARE_REGISTER_WAIT((R_DPHYCNT->DPHYSFR & R_DPHYCNT_DPHYSFR_PWRSF_Msk), R_DPHYCNT_DPHYSFR_PWRSF_Msk); 65 66 /* Configure D-PHY PLL and LP frequency divider */ 67 R_DPHYCNT->DPHYPLFCR = p_cfg->pll_settings.raw; 68 R_DPHYCNT->DPHYESCCR_b.ESCDIV = p_cfg->lp_divisor; 69 70 /* Start D-PHY PLL and wait for startup */ 71 R_DPHYCNT->DPHYPLOCR_b.PLLSTP = 0; 72 FSP_HARDWARE_REGISTER_WAIT((R_DPHYCNT->DPHYSFR & R_DPHYCNT_DPHYSFR_PLLSF_Msk), R_DPHYCNT_DPHYSFR_PLLSF_Msk); 73 74 /* Set D-PHY timing parameters */ 75 mipi_phy_timing_t const * p_timing = p_cfg->p_timing; 76 R_DPHYCNT->DPHYTIM1 = p_timing->t_init; 77 R_DPHYCNT->DPHYTIM2 = p_timing->t_clk_prep; 78 R_DPHYCNT->DPHYTIM3 = p_timing->t_hs_prep; 79 R_DPHYCNT->DPHYTIM4 = p_timing->dphytim4; 80 R_DPHYCNT->DPHYTIM5 = p_timing->dphytim5; 81 R_DPHYCNT->DPHYTIM6 = p_timing->t_lp_exit; 82 83 /* Enable D-PHY */ 84 R_DPHYCNT->DPHYOCR_b.DPHYEN = 1U; 85 86 /* Keep track of p_cfg struct */ 87 p_ctrl->p_cfg = p_cfg; 88 89 /* Mark control block as opened */ 90 p_ctrl->open = MIPI_PHY_OPEN; 91 92 return FSP_SUCCESS; 93 } 94 95 /********************************************************************************************************************** 96 * Stop filter operations and close the channel instance. 97 * 98 * NOTE: D_PHY must be stopped and LDO disabled before entering standby mode. See 56.3.2 D-PHY Stop Procedure, R01UH0995EJ0060 99 * 100 * @retval FSP_SUCCESS The channel is successfully closed. 101 * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. 102 * @retval FSP_ERR_NOT_OPEN Instance is not open. 103 **********************************************************************************************************************/ r_mipi_phy_close(mipi_phy_ctrl_t * const p_api_ctrl)104fsp_err_t r_mipi_phy_close (mipi_phy_ctrl_t * const p_api_ctrl) 105 { 106 mipi_phy_ctrl_t * p_ctrl = p_api_ctrl; 107 108 /* Disable D-PHY */ 109 R_DPHYCNT->DPHYOCR_b.DPHYEN = 0; 110 111 /* Disable D-PHY PLL */ 112 R_DPHYCNT->DPHYPLOCR_b.PLLSTP = 1; 113 114 /* Disable MIPI LDO */ 115 R_DPHYCNT->DPHYPWRCR_b.PWRSEN = 0; 116 117 /* Set control block to closed */ 118 p_ctrl->open = 0U; 119 120 return FSP_SUCCESS; 121 } 122 123 /*******************************************************************************************************************//** 124 * @} (end addtogroup MIPI_PHY) 125 **********************************************************************************************************************/ 126
