1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @addtogroup BSP_MCU_RA8M1 9 * @{ 10 **********************************************************************************************************************/ 11 12 /** @} (end addtogroup BSP_MCU_RA8M1) */ 13 14 #ifndef BSP_OVERRIDE_H 15 #define BSP_OVERRIDE_H 16 17 /*********************************************************************************************************************** 18 * Includes <System Includes> , "Project Includes" 19 **********************************************************************************************************************/ 20 21 /*********************************************************************************************************************** 22 * Macro definitions 23 **********************************************************************************************************************/ 24 25 /* Define overrides required for this MCU. */ 26 27 #define BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T 28 #define BSP_OVERRIDE_GROUP_IRQ_T 29 30 /*********************************************************************************************************************** 31 * Typedef definitions 32 **********************************************************************************************************************/ 33 34 /** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, 35 * PCLKS A-D. */ 36 typedef enum e_cgc_sys_clock_div 37 { 38 CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 39 CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 40 CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 41 CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 42 CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 43 CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 44 CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 45 CGC_SYS_CLOCK_DIV_3 = 8, ///< System clock divided by 3 46 CGC_SYS_CLOCK_DIV_6 = 9, ///< System clock divided by 6 47 CGC_SYS_CLOCK_DIV_12 = 10, ///< System clock divided by 12 48 } cgc_sys_clock_div_t; 49 50 /* Which interrupts can have callbacks registered. */ 51 typedef enum e_bsp_grp_irq 52 { 53 BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred 54 BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred 55 BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt 56 BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt 57 BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected 58 BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt 59 BSP_GRP_IRQ_MPU_BUS_TZF = 12, ///< MPU Bus or TrustZone Filter Error 60 BSP_GRP_IRQ_COMMON_MEMORY = 13, ///< SRAM ECC or SRAM Parity Error 61 BSP_GRP_IRQ_LOCKUP = 15, ///< LockUp Error 62 } bsp_grp_irq_t; 63 64 /*********************************************************************************************************************** 65 * Exported global variables 66 **********************************************************************************************************************/ 67 68 /*********************************************************************************************************************** 69 * Exported global functions (to be accessed by other files) 70 **********************************************************************************************************************/ 71 72 #endif 73
