1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_ELC_H 8 #define BSP_ELC_H 9 10 /*******************************************************************************************************************//** 11 * @addtogroup BSP_MCU_RA8M1 12 * @{ 13 **********************************************************************************************************************/ 14 15 /*********************************************************************************************************************** 16 * Macro definitions 17 **********************************************************************************************************************/ 18 19 /*********************************************************************************************************************** 20 * Typedef definitions 21 **********************************************************************************************************************/ 22 23 /*********************************************************************************************************************** 24 * Exported global variables 25 **********************************************************************************************************************/ 26 27 /*********************************************************************************************************************** 28 * Exported global functions (to be accessed by other files) 29 **********************************************************************************************************************/ 30 31 /* UNCRUSTIFY-OFF */ 32 33 /** Sources of event signals to be linked to other peripherals or the CPU 34 * @note This list is device specific. 35 * */ 36 typedef enum e_elc_event_ra8m1 37 { 38 ELC_EVENT_NONE = (0x0), // Link disabled 39 ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 40 ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 41 ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 42 ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 43 ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 44 ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 45 ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 46 ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 47 ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 48 ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 49 ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 50 ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 51 ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 52 ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 53 ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 54 ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 55 ELC_EVENT_DMAC0_INT = (0x011), // DMAC0 transfer end 56 ELC_EVENT_DMAC1_INT = (0x012), // DMAC1 transfer end 57 ELC_EVENT_DMAC2_INT = (0x013), // DMAC2 transfer end 58 ELC_EVENT_DMAC3_INT = (0x014), // DMAC3 transfer end 59 ELC_EVENT_DMAC4_INT = (0x015), // DMAC4 transfer end 60 ELC_EVENT_DMAC5_INT = (0x016), // DMAC5 transfer end 61 ELC_EVENT_DMAC6_INT = (0x017), // DMAC6 transfer end 62 ELC_EVENT_DMAC7_INT = (0x018), // DMAC7 transfer end 63 ELC_EVENT_DTC_END = (0x021), // DTC transfer end 64 ELC_EVENT_DTC_COMPLETE = (0x022), // DTC transfer complete 65 ELC_EVENT_DMA_TRANSERR = (0x027), // DMA/DTC transfer error 66 ELC_EVENT_DBG_CTIIRQ0 = (0x029), // Coresight Crosstrigger Event 67 ELC_EVENT_DBG_CTIIRQ1 = (0x02A), // Coresight Crosstrigger Event 68 ELC_EVENT_DBG_JBRXI = (0x02B), // JB RXI 69 ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt 70 ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt 71 ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt 72 ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt 73 ELC_EVENT_VBATT_TADI = (0x03D), // VBATT Tamper Detection 74 ELC_EVENT_CGC_MOSC_STOP = (0x03E), // Main Clock oscillation stop 75 ELC_EVENT_ULPT0_INT = (0x040), // ULPT0 Underflow 76 ELC_EVENT_ULPT0_COMPARE_A = (0x041), // ULPT0 Compare match A 77 ELC_EVENT_ULPT0_COMPARE_B = (0x042), // ULPT0 Compare match B 78 ELC_EVENT_ULPT1_INT = (0x043), // ULPT1 Underflow 79 ELC_EVENT_ULPT1_COMPARE_A = (0x044), // ULPT1 Compare match A 80 ELC_EVENT_ULPT1_COMPARE_B = (0x045), // ULPT1 Compare match B 81 ELC_EVENT_AGT0_INT = (0x046), // AGT interrupt 82 ELC_EVENT_AGT0_COMPARE_A = (0x047), // Compare match A 83 ELC_EVENT_AGT0_COMPARE_B = (0x048), // Compare match B 84 ELC_EVENT_AGT1_INT = (0x049), // AGT interrupt 85 ELC_EVENT_AGT1_COMPARE_A = (0x04A), // Compare match A 86 ELC_EVENT_AGT1_COMPARE_B = (0x04B), // Compare match B 87 ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow 88 ELC_EVENT_WDT0_UNDERFLOW = (0x053), // WDT0 underflow 89 ELC_EVENT_RTC_ALARM = (0x055), // Alarm interrupt 90 ELC_EVENT_RTC_PERIOD = (0x056), // Periodic interrupt 91 ELC_EVENT_RTC_CARRY = (0x057), // Carry interrupt 92 ELC_EVENT_USBFS_FIFO_0 = (0x058), // DMA transfer request 0 93 ELC_EVENT_USBFS_FIFO_1 = (0x059), // DMA transfer request 1 94 ELC_EVENT_USBFS_INT = (0x05A), // USBFS interrupt 95 ELC_EVENT_USBFS_RESUME = (0x05B), // USBFS resume interrupt 96 ELC_EVENT_IIC0_RXI = (0x05C), // Receive data full 97 ELC_EVENT_IIC0_TXI = (0x05D), // Transmit data empty 98 ELC_EVENT_IIC0_TEI = (0x05E), // Transmit end 99 ELC_EVENT_IIC0_ERI = (0x05F), // Transfer error 100 ELC_EVENT_IIC0_WUI = (0x060), // Wakeup interrupt 101 ELC_EVENT_IIC1_RXI = (0x061), // Receive data full 102 ELC_EVENT_IIC1_TXI = (0x062), // Transmit data empty 103 ELC_EVENT_IIC1_TEI = (0x063), // Transmit end 104 ELC_EVENT_IIC1_ERI = (0x064), // Transfer error 105 ELC_EVENT_SDHIMMC0_ACCS = (0x06B), // Card access 106 ELC_EVENT_SDHIMMC0_SDIO = (0x06C), // SDIO access 107 ELC_EVENT_SDHIMMC0_CARD = (0x06D), // Card detect 108 ELC_EVENT_SDHIMMC0_DMA_REQ = (0x06E), // DMA transfer request 109 ELC_EVENT_SDHIMMC1_ACCS = (0x06F), // Card access 110 ELC_EVENT_SDHIMMC1_SDIO = (0x070), // SDIO access 111 ELC_EVENT_SDHIMMC1_CARD = (0x071), // Card detect 112 ELC_EVENT_SDHIMMC1_DMA_REQ = (0x072), // DMA transfer request 113 ELC_EVENT_SSI0_TXI = (0x073), // Transmit data empty 114 ELC_EVENT_SSI0_RXI = (0x074), // Receive data full 115 ELC_EVENT_SSI0_INT = (0x076), // Error interrupt 116 ELC_EVENT_SSI1_TXI_RXI = (0x079), // Receive data full/Transmit data empty 117 ELC_EVENT_SSI1_INT = (0x07A), // Error interrupt 118 ELC_EVENT_ACMPHS0_INT = (0x07B), // High Speed Comparator channel 0 interrupt 119 ELC_EVENT_ACMPHS1_INT = (0x07C), // High Speed Comparator channel 1 interrupt 120 ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x083), // Software event 0 121 ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x084), // Software event 1 122 ELC_EVENT_IOPORT_EVENT_1 = (0x088), // Port 1 event 123 ELC_EVENT_IOPORT_EVENT_2 = (0x089), // Port 2 event 124 ELC_EVENT_IOPORT_EVENT_3 = (0x08A), // Port 3 event 125 ELC_EVENT_IOPORT_EVENT_4 = (0x08B), // Port 4 event 126 ELC_EVENT_CAC_FREQUENCY_ERROR = (0x08C), // Frequency error interrupt 127 ELC_EVENT_CAC_MEASUREMENT_END = (0x08D), // Measurement end interrupt 128 ELC_EVENT_CAC_OVERFLOW = (0x08E), // Overflow interrupt 129 ELC_EVENT_POEG0_EVENT = (0x08F), // Port Output disable 0 interrupt 130 ELC_EVENT_POEG1_EVENT = (0x090), // Port Output disable 1 interrupt 131 ELC_EVENT_POEG2_EVENT = (0x091), // Port Output disable 2 interrupt 132 ELC_EVENT_POEG3_EVENT = (0x092), // Port Output disable 3 interrupt 133 ELC_EVENT_OPS_UVW_EDGE = (0x0A0), // UVW edge event 134 ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0A1), // Capture/Compare match A 135 ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0A2), // Capture/Compare match B 136 ELC_EVENT_GPT0_COMPARE_C = (0x0A3), // Compare match C 137 ELC_EVENT_GPT0_COMPARE_D = (0x0A4), // Compare match D 138 ELC_EVENT_GPT0_COMPARE_E = (0x0A5), // Compare match E 139 ELC_EVENT_GPT0_COMPARE_F = (0x0A6), // Compare match F 140 ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0A7), // Overflow 141 ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0A8), // Underflow 142 ELC_EVENT_GPT0_PC = (0x0A9), // Period count function finish 143 ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0AA), // Capture/Compare match A 144 ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0AB), // Capture/Compare match B 145 ELC_EVENT_GPT1_COMPARE_C = (0x0AC), // Compare match C 146 ELC_EVENT_GPT1_COMPARE_D = (0x0AD), // Compare match D 147 ELC_EVENT_GPT1_COMPARE_E = (0x0AE), // Compare match E 148 ELC_EVENT_GPT1_COMPARE_F = (0x0AF), // Compare match F 149 ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0B0), // Overflow 150 ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0B1), // Underflow 151 ELC_EVENT_GPT1_PC = (0x0B2), // Period count function finish 152 ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0B3), // Capture/Compare match A 153 ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0B4), // Capture/Compare match B 154 ELC_EVENT_GPT2_COMPARE_C = (0x0B5), // Compare match C 155 ELC_EVENT_GPT2_COMPARE_D = (0x0B6), // Compare match D 156 ELC_EVENT_GPT2_COMPARE_E = (0x0B7), // Compare match E 157 ELC_EVENT_GPT2_COMPARE_F = (0x0B8), // Compare match F 158 ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0B9), // Overflow 159 ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0BA), // Underflow 160 ELC_EVENT_GPT2_PC = (0x0BB), // Period count function finish 161 ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0BC), // Capture/Compare match A 162 ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0BD), // Capture/Compare match B 163 ELC_EVENT_GPT3_COMPARE_C = (0x0BE), // Compare match C 164 ELC_EVENT_GPT3_COMPARE_D = (0x0BF), // Compare match D 165 ELC_EVENT_GPT3_COMPARE_E = (0x0C0), // Compare match E 166 ELC_EVENT_GPT3_COMPARE_F = (0x0C1), // Compare match F 167 ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0C2), // Overflow 168 ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0C3), // Underflow 169 ELC_EVENT_GPT3_PC = (0x0C4), // Period count function finish 170 ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0C5), // Capture/Compare match A 171 ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0C6), // Capture/Compare match B 172 ELC_EVENT_GPT4_COMPARE_C = (0x0C7), // Compare match C 173 ELC_EVENT_GPT4_COMPARE_D = (0x0C8), // Compare match D 174 ELC_EVENT_GPT4_COMPARE_E = (0x0C9), // Compare match E 175 ELC_EVENT_GPT4_COMPARE_F = (0x0CA), // Compare match F 176 ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0CB), // Overflow 177 ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0CC), // Underflow 178 ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A 179 ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B 180 ELC_EVENT_GPT5_COMPARE_C = (0x0D0), // Compare match C 181 ELC_EVENT_GPT5_COMPARE_D = (0x0D1), // Compare match D 182 ELC_EVENT_GPT5_COMPARE_E = (0x0D2), // Compare match E 183 ELC_EVENT_GPT5_COMPARE_F = (0x0D3), // Compare match F 184 ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0D4), // Overflow 185 ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0D5), // Underflow 186 ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0D7), // Capture/Compare match A 187 ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0D8), // Capture/Compare match B 188 ELC_EVENT_GPT6_COMPARE_C = (0x0D9), // Compare match C 189 ELC_EVENT_GPT6_COMPARE_D = (0x0DA), // Compare match D 190 ELC_EVENT_GPT6_COMPARE_E = (0x0DB), // Compare match E 191 ELC_EVENT_GPT6_COMPARE_F = (0x0DC), // Compare match F 192 ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0DD), // Overflow 193 ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0DE), // Underflow 194 ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0E0), // Capture/Compare match A 195 ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0E1), // Capture/Compare match B 196 ELC_EVENT_GPT7_COMPARE_C = (0x0E2), // Compare match C 197 ELC_EVENT_GPT7_COMPARE_D = (0x0E3), // Compare match D 198 ELC_EVENT_GPT7_COMPARE_E = (0x0E4), // Compare match E 199 ELC_EVENT_GPT7_COMPARE_F = (0x0E5), // Compare match F 200 ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0E6), // Overflow 201 ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0E7), // Underflow 202 ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x0E9), // Capture/Compare match A 203 ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x0EA), // Capture/Compare match B 204 ELC_EVENT_GPT8_COMPARE_C = (0x0EB), // Compare match C 205 ELC_EVENT_GPT8_COMPARE_D = (0x0EC), // Compare match D 206 ELC_EVENT_GPT8_COMPARE_E = (0x0ED), // Compare match E 207 ELC_EVENT_GPT8_COMPARE_F = (0x0EE), // Compare match F 208 ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x0EF), // Overflow 209 ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x0F0), // Underflow 210 ELC_EVENT_GPT8_PC = (0x0F1), // Period count function finish 211 ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x0F2), // Capture/Compare match A 212 ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x0F3), // Capture/Compare match B 213 ELC_EVENT_GPT9_COMPARE_C = (0x0F4), // Compare match C 214 ELC_EVENT_GPT9_COMPARE_D = (0x0F5), // Compare match D 215 ELC_EVENT_GPT9_COMPARE_E = (0x0F6), // Compare match E 216 ELC_EVENT_GPT9_COMPARE_F = (0x0F7), // Compare match F 217 ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x0F8), // Overflow 218 ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x0F9), // Underflow 219 ELC_EVENT_GPT9_PC = (0x0FA), // Period count function finish 220 ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x0FB), // Capture/Compare match A 221 ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x0FC), // Capture/Compare match B 222 ELC_EVENT_GPT10_COMPARE_C = (0x0FD), // Compare match C 223 ELC_EVENT_GPT10_COMPARE_D = (0x0FE), // Compare match D 224 ELC_EVENT_GPT10_COMPARE_E = (0x0FF), // Compare match E 225 ELC_EVENT_GPT10_COMPARE_F = (0x100), // Compare match F 226 ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x101), // Overflow 227 ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x102), // Underflow 228 ELC_EVENT_GPT10_PC = (0x103), // Period count function finish 229 ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x104), // Capture/Compare match A 230 ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x105), // Capture/Compare match B 231 ELC_EVENT_GPT11_COMPARE_C = (0x106), // Compare match C 232 ELC_EVENT_GPT11_COMPARE_D = (0x107), // Compare match D 233 ELC_EVENT_GPT11_COMPARE_E = (0x108), // Compare match E 234 ELC_EVENT_GPT11_COMPARE_F = (0x109), // Compare match F 235 ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x10A), // Overflow 236 ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x10B), // Underflow 237 ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x10D), // Capture/Compare match A 238 ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x10E), // Capture/Compare match B 239 ELC_EVENT_GPT12_COMPARE_C = (0x10F), // Compare match C 240 ELC_EVENT_GPT12_COMPARE_D = (0x110), // Compare match D 241 ELC_EVENT_GPT12_COMPARE_E = (0x111), // Compare match E 242 ELC_EVENT_GPT12_COMPARE_F = (0x112), // Compare match F 243 ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x113), // Overflow 244 ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x114), // Underflow 245 ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x116), // Capture/Compare match A 246 ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x117), // Capture/Compare match B 247 ELC_EVENT_GPT13_COMPARE_C = (0x118), // Compare match C 248 ELC_EVENT_GPT13_COMPARE_D = (0x119), // Compare match D 249 ELC_EVENT_GPT13_COMPARE_E = (0x11A), // Compare match E 250 ELC_EVENT_GPT13_COMPARE_F = (0x11B), // Compare match F 251 ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x11C), // Overflow 252 ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x11D), // Underflow 253 ELC_EVENT_EDMAC0_EINT = (0x120), // EDMAC 0 interrupt 254 ELC_EVENT_USBHS_FIFO_0 = (0x121), // DMA transfer request 0 255 ELC_EVENT_USBHS_FIFO_1 = (0x122), // DMA transfer request 1 256 ELC_EVENT_USBHS_USB_INT_RESUME = (0x123), // USBHS interrupt 257 ELC_EVENT_SCI0_RXI = (0x124), // Receive data full 258 ELC_EVENT_SCI0_TXI = (0x125), // Transmit data empty 259 ELC_EVENT_SCI0_TEI = (0x126), // Transmit end 260 ELC_EVENT_SCI0_ERI = (0x127), // Receive error 261 ELC_EVENT_SCI0_AED = (0x128), // Active edge detection 262 ELC_EVENT_SCI0_BFD = (0x129), // Break field detection 263 ELC_EVENT_SCI0_AM = (0x12A), // Address match event 264 ELC_EVENT_SCI1_RXI = (0x12B), // Receive data full 265 ELC_EVENT_SCI1_TXI = (0x12C), // Transmit data empty 266 ELC_EVENT_SCI1_TEI = (0x12D), // Transmit end 267 ELC_EVENT_SCI1_ERI = (0x12E), // Receive error 268 ELC_EVENT_SCI1_AED = (0x12F), // Active edge detection 269 ELC_EVENT_SCI1_BFD = (0x130), // Break field detection 270 ELC_EVENT_SCI1_AM = (0x131), // Address match event 271 ELC_EVENT_SCI2_RXI = (0x132), // Receive data full 272 ELC_EVENT_SCI2_TXI = (0x133), // Transmit data empty 273 ELC_EVENT_SCI2_TEI = (0x134), // Transmit end 274 ELC_EVENT_SCI2_ERI = (0x135), // Receive error 275 ELC_EVENT_SCI2_AM = (0x138), // Address match event 276 ELC_EVENT_SCI3_RXI = (0x139), // Receive data full 277 ELC_EVENT_SCI3_TXI = (0x13A), // Transmit data empty 278 ELC_EVENT_SCI3_TEI = (0x13B), // Transmit end 279 ELC_EVENT_SCI3_ERI = (0x13C), // Receive error 280 ELC_EVENT_SCI3_AM = (0x13F), // Address match event 281 ELC_EVENT_SCI4_RXI = (0x140), // Receive data full 282 ELC_EVENT_SCI4_TXI = (0x141), // Transmit data empty 283 ELC_EVENT_SCI4_TEI = (0x142), // Transmit end 284 ELC_EVENT_SCI4_ERI = (0x143), // Receive error 285 ELC_EVENT_SCI4_AM = (0x146), // Address match event 286 ELC_EVENT_SCI9_RXI = (0x163), // Receive data full 287 ELC_EVENT_SCI9_TXI = (0x164), // Transmit data empty 288 ELC_EVENT_SCI9_TEI = (0x165), // Transmit end 289 ELC_EVENT_SCI9_ERI = (0x166), // Receive error 290 ELC_EVENT_SCI9_AM = (0x169), // Address match event 291 ELC_EVENT_SPI0_RXI = (0x178), // Receive buffer full 292 ELC_EVENT_SPI0_TXI = (0x179), // Transmit buffer empty 293 ELC_EVENT_SPI0_IDLE = (0x17A), // Idle 294 ELC_EVENT_SPI0_ERI = (0x17B), // Error 295 ELC_EVENT_SPI0_TEI = (0x17C), // Transmission complete event 296 ELC_EVENT_SPI1_RXI = (0x17D), // Receive buffer full 297 ELC_EVENT_SPI1_TXI = (0x17E), // Transmit buffer empty 298 ELC_EVENT_SPI1_IDLE = (0x17F), // Idle 299 ELC_EVENT_SPI1_ERI = (0x180), // Error 300 ELC_EVENT_SPI1_TEI = (0x181), // Transmission complete event 301 ELC_EVENT_XSPI_ERR = (0x182), // xSPI Error 302 ELC_EVENT_XSPI_CMP = (0x183), // xSPI Complete 303 ELC_EVENT_CAN_RXF = (0x185), // Global recieve FIFO interrupt 304 ELC_EVENT_CAN_GLERR = (0x186), // Global error 305 ELC_EVENT_CAN0_DMAREQ0 = (0x187), // RX fifo DMA request 0 306 ELC_EVENT_CAN0_DMAREQ1 = (0x188), // RX fifo DMA request 1 307 ELC_EVENT_CAN1_DMAREQ0 = (0x18B), // RX fifo DMA request 0 308 ELC_EVENT_CAN1_DMAREQ1 = (0x18C), // RX fifo DMA request 1 309 ELC_EVENT_CAN0_TX = (0x18F), // Transmit interrupt 310 ELC_EVENT_CAN0_CHERR = (0x190), // Channel error 311 ELC_EVENT_CAN0_COMFRX = (0x191), // Common FIFO recieve interrupt 312 ELC_EVENT_CAN0_CF_DMAREQ = (0x192), // Channel DMA request 313 ELC_EVENT_CAN0_RXMB = (0x193), // Receive message buffer interrupt 314 ELC_EVENT_CAN1_TX = (0x194), // Transmit interrupt 315 ELC_EVENT_CAN1_CHERR = (0x195), // Channel error 316 ELC_EVENT_CAN1_COMFRX = (0x196), // Common FIFO recieve interrupt 317 ELC_EVENT_CAN1_CF_DMAREQ = (0x197), // Channel DMA request 318 ELC_EVENT_CAN1_RXMB = (0x198), // Receive message buffer interrupt 319 ELC_EVENT_CAN0_MRAM_ERI = (0x19B), // CANFD0 ECC error 320 ELC_EVENT_CAN1_MRAM_ERI = (0x19C), // CANFD1 ECC error 321 ELC_EVENT_I3C0_RESPONSE = (0x19D), // Response status buffer full 322 ELC_EVENT_I3C0_COMMAND = (0x19E), // Command buffer empty 323 ELC_EVENT_I3C0_IBI = (0x19F), // IBI status buffer full 324 ELC_EVENT_I3C0_RX = (0x1A0), // Receive 325 ELC_EVENT_I3C0_TX = (0x1A1), // Transmit 326 ELC_EVENT_I3C0_RCV_STATUS = (0x1A2), // Receive status buffer full 327 ELC_EVENT_I3C0_HRESP = (0x1A3), // High priority response queue full 328 ELC_EVENT_I3C0_HCMD = (0x1A4), // High priority command queue empty 329 ELC_EVENT_I3C0_HRX = (0x1A5), // High priority rx data buffer full 330 ELC_EVENT_I3C0_HTX = (0x1A6), // High priority tx data buffer empty 331 ELC_EVENT_I3C0_TEND = (0x1A7), // Transmit end 332 ELC_EVENT_I3C0_EEI = (0x1A8), // Error 333 ELC_EVENT_I3C0_STEV = (0x1A9), // Synchronous timing 334 ELC_EVENT_I3C0_MREFOVF = (0x1AA), // MREF counter overflow 335 ELC_EVENT_I3C0_MREFCPT = (0x1AB), // MREF capture 336 ELC_EVENT_I3C0_AMEV = (0x1AC), // Additional master-initiated bus event 337 ELC_EVENT_I3C0_WU = (0x1AD), // Wake-up Condition Detection interrupt 338 ELC_EVENT_ADC0_SCAN_END = (0x1AE), // End of A/D scanning operation 339 ELC_EVENT_ADC0_SCAN_END_B = (0x1AF), // A/D scan end interrupt for group B 340 ELC_EVENT_ADC0_WINDOW_A = (0x1B0), // Window A Compare match interrupt 341 ELC_EVENT_ADC0_WINDOW_B = (0x1B1), // Window B Compare match interrupt 342 ELC_EVENT_ADC0_COMPARE_MATCH = (0x1B2), // Compare match 343 ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x1B3), // Compare mismatch 344 ELC_EVENT_ADC1_SCAN_END = (0x1B4), // End of A/D scanning operation 345 ELC_EVENT_ADC1_SCAN_END_B = (0x1B5), // A/D scan end interrupt for group B 346 ELC_EVENT_ADC1_WINDOW_A = (0x1B6), // Window A Compare match interrupt 347 ELC_EVENT_ADC1_WINDOW_B = (0x1B7), // Window B Compare match interrupt 348 ELC_EVENT_ADC1_COMPARE_MATCH = (0x1B8), // Compare match 349 ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x1B9), // Compare mismatch 350 ELC_EVENT_DOC_INT = (0x1BA), // Data operation circuit interrupt 351 ELC_EVENT_RSIP_TADI = (0x1BC), // RSIP Tampler Detection 352 ELC_EVENT_CEU_CEUI = (0x1DA) // CEU interrupt 353 } elc_event_t; 354 355 #define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) 356 357 #define ELC_PERIPHERAL_NUM (31U) 358 #define BSP_OVERRIDE_ELC_PERIPHERAL_T 359 /** Possible peripherals to be linked to event signals 360 * @note This list is device specific. 361 * */ 362 typedef enum e_elc_peripheral 363 { 364 ELC_PERIPHERAL_GPT_A = (0), 365 ELC_PERIPHERAL_GPT_B = (1), 366 ELC_PERIPHERAL_GPT_C = (2), 367 ELC_PERIPHERAL_GPT_D = (3), 368 ELC_PERIPHERAL_GPT_E = (4), 369 ELC_PERIPHERAL_GPT_F = (5), 370 ELC_PERIPHERAL_GPT_G = (6), 371 ELC_PERIPHERAL_GPT_H = (7), 372 ELC_PERIPHERAL_ADC0 = (8), 373 ELC_PERIPHERAL_ADC0_B = (9), 374 ELC_PERIPHERAL_ADC1 = (10), 375 ELC_PERIPHERAL_ADC1_B = (11), 376 ELC_PERIPHERAL_DAC0 = (12), 377 ELC_PERIPHERAL_DAC1 = (13), 378 ELC_PERIPHERAL_IOPORT1 = (14), 379 ELC_PERIPHERAL_IOPORT2 = (15), 380 ELC_PERIPHERAL_IOPORT3 = (16), 381 ELC_PERIPHERAL_IOPORT4 = (17), 382 ELC_PERIPHERAL_I3C = (30) 383 } elc_peripheral_t; 384 385 /** Positions of event link set registers (ELSRs) available on this MCU */ 386 #define BSP_ELC_PERIPHERAL_MASK (0x4003FFFFU) 387 388 /* UNCRUSTIFY-ON */ 389 /** @} (end addtogroup BSP_MCU_RA8M1) */ 390 391 #endif 392
