1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_FEATURE_H 8 #define BSP_FEATURE_H 9 10 /*********************************************************************************************************************** 11 * Includes <System Includes> , "Project Includes" 12 **********************************************************************************************************************/ 13 #include "bsp_feature_gen.h" 14 15 /*********************************************************************************************************************** 16 * Macro definitions 17 **********************************************************************************************************************/ 18 19 /** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ 20 #define CGC_MOMCR_RESERVED_MASK (0x8U) /* RA8 has reserved bit in MOMCR that must be 1. */ 21 #if (BSP_CFG_XTAL_HZ > (24000000)) 22 #define CGC_MAINCLOCK_DRIVE (0x05U | CGC_MOMCR_RESERVED_MASK) 23 #elif (BSP_CFG_XTAL_HZ > (8000000)) && (BSP_CFG_XTAL_HZ <= (24000000)) 24 #define CGC_MAINCLOCK_DRIVE (0x03U | CGC_MOMCR_RESERVED_MASK) 25 #else 26 #define CGC_MAINCLOCK_DRIVE (0x00U | CGC_MOMCR_RESERVED_MASK) 27 #endif 28 29 /*********************************************************************************************************************** 30 * Typedef definitions 31 **********************************************************************************************************************/ 32 33 /*********************************************************************************************************************** 34 * Exported global variables (to be accessed by other files) 35 **********************************************************************************************************************/ 36 37 /*********************************************************************************************************************** 38 * Private global variables and functions 39 **********************************************************************************************************************/ 40 41 #define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. 42 #define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) 43 44 #define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0U) // Feature not available on this MCU 45 #define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0U) // Feature not available on this MCU 46 47 #define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) // ADC Derived from RA8D1 48 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0) // Feature not available on this MCU 49 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0) // Feature not available on this MCU 50 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0) // Feature not available on this MCU 51 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0) // Feature not available on this MCU 52 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) 53 #define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) 54 #define BSP_FEATURE_ADC_D_CHANNELS (0) // Feature not available on this MCU 55 #define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0) // Feature not available on this MCU 56 #define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) 57 #define BSP_FEATURE_ADC_HAS_ADBUF (1U) 58 #define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) 59 #define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) 60 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U) 61 #define BSP_FEATURE_ADC_HAS_PGA (0U) 62 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) 63 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) 64 #define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) 65 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) 66 #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) 67 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) 68 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU) 69 #define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU 70 #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) 71 #define BSP_FEATURE_ADC_TSN_SLOPE (4000) 72 #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0xF01FF) // 0 to 8, 16 to 19 73 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F007F) // 0 to 6, 16 to 22 74 #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) 75 76 #define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0) 77 #define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2) 78 #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL 79 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) 80 81 #define BSP_FEATURE_BSP_FLASH_CACHE (1) 82 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) 83 #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) 84 #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) 85 #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU 86 #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) 87 #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) 88 #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) 89 #define BSP_FEATURE_BSP_HAS_DTCM (1U) 90 #define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0U) // Mutually exclusive with USB60 Clock 91 #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (1) 92 #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) 93 #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) 94 #define BSP_FEATURE_BSP_HAS_ITCM (1U) 95 #define BSP_FEATURE_BSP_HAS_LCD_CLOCK (1) 96 #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1U) 97 #define BSP_FEATURE_BSP_HAS_OFS2 (1U) 98 #define BSP_FEATURE_BSP_HAS_OFS3 (0U) 99 #define BSP_FEATURE_BSP_HAS_SCE5 (0) 100 #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU 101 #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) 102 #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (1) 103 #define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) 104 #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) 105 #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (1) 106 #define BSP_FEATURE_BSP_HAS_SP_MON (0U) 107 #define BSP_FEATURE_BSP_HAS_SYRACCR (1U) 108 #define BSP_FEATURE_BSP_HAS_TZFSAR (0) 109 #define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU 110 #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) 111 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) 112 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) 113 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) 114 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) 115 #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) 116 #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU 117 #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. 118 #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) 119 #define BSP_FEATURE_BSP_NUM_PMSAR (16U) // 16 due to offset address change from PMSAR2 to PMSAR3 120 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFU) 121 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) 122 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1) 123 #define BSP_FEATURE_BSP_OSIS_PADDING (0U) 124 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) 125 #define BSP_FEATURE_BSP_RESET_TRNG (0U) 126 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (240000000U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). 127 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (192000000U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). 128 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (120000000U) 129 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (48000000U) // The maximum frequency allowed without having one ROM wait cycle. 130 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (144000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). 131 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (96000000U) // The maximum frequency allowed without having two ROM wait cycles. (Set to zero if this is not an option). 132 #define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) 133 #define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x03008190U) 134 #define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) 135 136 #define BSP_FEATURE_CANFD_FD_SUPPORT (1U) 137 #define BSP_FEATURE_CANFD_LITE (1U) 138 #define BSP_FEATURE_CANFD_NUM_CHANNELS (1U) 139 #define BSP_FEATURE_CANFD_NUM_INSTANCES (2U) 140 141 #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) 142 #define BSP_FEATURE_CAN_CLOCK (0U) 143 #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) 144 #define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA8D1 has CAN-FD 145 146 #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0) 147 #define BSP_FEATURE_CGC_HAS_BCLK (1U) 148 #define BSP_FEATURE_CGC_HAS_CPUCLK (1U) 149 #define BSP_FEATURE_CGC_HAS_FCLK (1U) 150 #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) 151 #define BSP_FEATURE_CGC_HAS_FLL (1U) 152 #define BSP_FEATURE_CGC_HAS_FLWT (1U) 153 #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) 154 #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) 155 #define BSP_FEATURE_CGC_HAS_PCLKA (1U) 156 #define BSP_FEATURE_CGC_HAS_PCLKB (1U) 157 #define BSP_FEATURE_CGC_HAS_PCLKC (1U) 158 #define BSP_FEATURE_CGC_HAS_PCLKD (1U) 159 #define BSP_FEATURE_CGC_HAS_PCLKE (1U) 160 #define BSP_FEATURE_CGC_HAS_PLL (1U) 161 #define BSP_FEATURE_CGC_HAS_PLL2 (1U) 162 #define BSP_FEATURE_CGC_HAS_SOPCCR (0U) 163 #define BSP_FEATURE_CGC_HAS_SOSC (1U) 164 #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA8D1 there is another register to enable write access for SRAMWTSC. 165 #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) 166 #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) 167 #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) 168 #define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) 169 #define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) 170 #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_1) 171 #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) 172 #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz 173 #define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode 174 #define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode 175 #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) 176 #define BSP_FEATURE_CGC_MODRV_MASK (0x1EU) 177 #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) 178 #define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000U) 179 #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3U) 180 #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3U) 181 #define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) 182 #define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) 183 #define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) 184 #define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) 185 #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (480000000U) 186 #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (40000000U) 187 #define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (48000000U) 188 #define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) 189 #define BSP_FEATURE_CGC_PLLCCR_TYPE (3U) 190 #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (1440000000U) 191 #define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (640000000U) 192 #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (12000000U) 193 #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (6000000U) 194 #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP 195 #define BSP_FEATURE_CGC_REGISTER_SET_B (0) 196 #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) 197 #define BSP_FEATURE_CGC_SODRV_MASK (3U) 198 #define BSP_FEATURE_CGC_SODRV_SHIFT (0U) 199 #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) 200 #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5) 201 #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) 202 #define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU 203 #define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) 204 #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00000000) 205 #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) 206 #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) 207 208 #define BSP_FEATURE_CRC_HAS_SNOOP (1U) 209 #define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) 210 #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) 211 #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) 212 213 #define BSP_FEATURE_CRYPTO_HAS_AES (1) 214 #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) 215 #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) 216 #define BSP_FEATURE_CRYPTO_HAS_ECC (1) 217 #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) 218 #define BSP_FEATURE_CRYPTO_HAS_HASH (1) 219 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (1) 220 #define BSP_FEATURE_CRYPTO_HAS_RSA (1) 221 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) 222 #define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) 223 #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) // Feature not available on this MCU 224 #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) 225 #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) 226 #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) 227 #define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) 228 229 #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0U) // Feature not available on this MCU 230 #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0U) // Feature not available on this MCU 231 #define BSP_FEATURE_CTSU_HAS_TXVSEL (0) // Feature not available on this MCU 232 #define BSP_FEATURE_CTSU_VERSION (0) // Feature not available on this MCU 233 234 #define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU 235 #define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU 236 #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU 237 #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU 238 239 #define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) 240 #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) 241 #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) 242 #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) 243 #define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (1U) 244 #define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) 245 #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) 246 247 #define BSP_FEATURE_DMAC_HAS_DELSR (1U) 248 #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) 249 #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) 250 251 #define BSP_FEATURE_DOC_VERSION (2U) 252 253 #define BSP_FEATURE_DWT_CYCCNT (1U) // RA8D1 has Data Watchpoint Cycle Count Register 254 255 #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Deprecated (Removing in FSP v6.0) 256 #define BSP_FEATURE_ELC_VERSION (2U) 257 258 #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) 259 #define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) 260 #define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (1U) // Feature available on this MCU 261 262 #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x02000000U) 263 #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x27000000U) 264 #define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x02200000U) 265 #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) 266 #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) 267 #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) 268 #define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) 269 #define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) 270 #define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) 271 #define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1) 272 #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1) 273 #define BSP_FEATURE_FLASH_HP_VERSION (40U) 274 #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU 275 #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU 276 #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU 277 #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU 278 #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU 279 #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU 280 #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU 281 #define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU 282 #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU 283 #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU 284 #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU 285 286 #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00FFU) 287 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) 288 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) 289 #define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) 290 #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (115000000U) 291 #define BSP_FEATURE_GPT_ODC_FREQ_MAX (200000000U) 292 #define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) 293 #define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU 294 #define BSP_FEATURE_GPT_TPCS_SHIFT (0U) 295 #define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFU) 296 297 #define BSP_FEATURE_I3C_NUM_CHANNELS (1U) 298 #define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) 299 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) 300 #define BSP_FEATURE_I3C_MSTP_OFFSET (4U) 301 302 #define BSP_FEATURE_ICU_HAS_FILTER (1U) 303 #define BSP_FEATURE_ICU_HAS_IELSR (1U) 304 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) 305 #define BSP_FEATURE_ICU_HAS_WUPEN1 (1) 306 #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU 307 #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) 308 #define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register 309 #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) 310 311 #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) 312 #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) 313 #define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x01) 314 #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0x03) 315 #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) 316 #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU 317 318 #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) 319 #define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) 320 #define BSP_FEATURE_IOPORT_VERSION (2U) 321 322 #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) 323 #define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (1U) 324 325 #define BSP_FEATURE_KINT_HAS_MSTP (0U) // Feature not available on this MCU 326 327 #define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U) 328 #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) 329 #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x12FFFFU) 330 #define BSP_FEATURE_LPM_DPSIER_MASK (0xAF1FFFFFU) 331 #define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (1U) 332 #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) 333 #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) 334 #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) 335 #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (1U) 336 #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (1U) 337 #define BSP_FEATURE_LPM_HAS_LPSCR (1U) 338 #define BSP_FEATURE_LPM_HAS_PDRAMSCR (1U) 339 #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) 340 #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (0U) 341 #define BSP_FEATURE_LPM_HAS_SNOOZE (0U) 342 #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) 343 #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) 344 #define BSP_FEATURE_LPM_HAS_STCONR (0U) 345 #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU 346 #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU 347 #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU 348 #define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU 349 #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) 350 #define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU 351 #define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU 352 #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1U) 353 354 #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) 355 #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) 356 #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) 357 #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V 358 #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V 359 #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V 360 #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V 361 #define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30U) // LVD1 operation stabilization time after LVD1 is enabled 362 #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (30U) // LVD2 operation stabilization time after LVD2 is enabled 363 #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1U) 364 #define BSP_FEATURE_LVD_VERSION (1U) 365 366 #define BSP_FEATURE_MACL_SUPPORTED (0U) 367 368 #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) 369 #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU 370 #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) 371 #define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) 372 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU 373 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU 374 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU 375 #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) 376 #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) 377 378 #define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000U) 379 #define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000U) 380 381 #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) 382 383 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) 384 385 #define BSP_FEATURE_RTC_IS_AVAILABLE (1U) 386 #define BSP_FEATURE_RTC_IS_IRTC (0U) 387 #define BSP_FEATURE_RTC_HAS_ROPSEL (0) // Feature not available on this MCU 388 #define BSP_FEATURE_RTC_HAS_TCEN (1U) 389 #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) 390 #define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) 391 392 #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU 393 394 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0U) 395 #define BSP_FEATURE_SCI_CHANNELS (0x21FU) 396 #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) 397 #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (1U) 398 #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x21FU) 399 #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x21FU) 400 #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) 401 #define BSP_FEATURE_SCI_VERSION (2U) 402 #define BSP_FEATURE_SCI_LIN_CHANNELS (0x3U) 403 404 #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) 405 #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) 406 #define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported 407 #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) 408 #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x03U) 409 410 #define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000U) 411 412 #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU 413 #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU 414 #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU 415 #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU 416 #define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU 417 #define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU 418 419 #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) 420 #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) 421 #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) 422 #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) 423 #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x3U) 424 425 #define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (1) 426 427 #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) 428 #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) 429 430 #define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU 431 #define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU 432 433 #define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU 434 #define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU 435 #define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU 436 437 #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) available on this MCU 438 439 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) 440 #define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) 441 #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) 442 #define BSP_FEATURE_TZ_HAS_DLM (1U) 443 #define BSP_FEATURE_TZ_VERSION (2U) 444 445 #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) 446 #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) 447 448 #define BSP_FEATURE_USB_NUM_IP (2U) 449 #define BSP_FEATURE_USB_HAS_USBHS (1U) 450 451 #endif 452
