1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_FEATURE_H 8 #define BSP_FEATURE_H 9 10 /*********************************************************************************************************************** 11 * Includes <System Includes> , "Project Includes" 12 **********************************************************************************************************************/ 13 #include "bsp_feature_gen.h" 14 15 /*********************************************************************************************************************** 16 * Macro definitions 17 **********************************************************************************************************************/ 18 19 /** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ 20 #if (BSP_CFG_XTAL_HZ > (9999999)) 21 #define CGC_MAINCLOCK_DRIVE (0x00U) 22 #else 23 #define CGC_MAINCLOCK_DRIVE (0x01U) 24 #endif 25 26 /*********************************************************************************************************************** 27 * Typedef definitions 28 **********************************************************************************************************************/ 29 30 /*********************************************************************************************************************** 31 * Exported global variables (to be accessed by other files) 32 **********************************************************************************************************************/ 33 34 /*********************************************************************************************************************** 35 * Private global variables and functions 36 **********************************************************************************************************************/ 37 38 #define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU 39 #define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU 40 41 #define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) 42 #define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) 43 44 #define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) 45 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U) 46 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0U) 47 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U) 48 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U) 49 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) 50 #define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) 51 #define BSP_FEATURE_ADC_D_CHANNELS (0) // Feature not available on this MCU 52 #define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0) // Feature not available on this MCU 53 #define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) 54 #define BSP_FEATURE_ADC_HAS_ADBUF (0U) 55 #define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) 56 #define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) 57 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (1U) 58 #define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU 59 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) 60 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) 61 #define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (14U) 62 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) 63 #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) 64 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) 65 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0U) 66 #define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) 67 #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) 68 #define BSP_FEATURE_ADC_TSN_SLOPE (-3650) 69 #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x3FF7FFF) // 0 to 14, 16 to 25 in unit 0 70 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) 71 #define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) 72 73 #define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0) 74 #define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2) 75 #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL 76 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) 77 78 #define BSP_FEATURE_BSP_FLASH_CACHE (1) 79 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) 80 #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) 81 #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU 82 #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU 83 #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) 84 #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) 85 #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) 86 #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU 87 #define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock 88 #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) 89 #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) 90 #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) 91 #define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU 92 #define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0) 93 #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) 94 #define BSP_FEATURE_BSP_HAS_OFS2 (0) 95 #define BSP_FEATURE_BSP_HAS_OFS3 (0) 96 #define BSP_FEATURE_BSP_HAS_SCE5 (1) 97 #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU 98 #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU 99 #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) 100 #define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) 101 #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) 102 #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) 103 #define BSP_FEATURE_BSP_HAS_SP_MON (1U) 104 #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) 105 #define BSP_FEATURE_BSP_HAS_TZFSAR (0) 106 #define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU 107 #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) 108 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) 109 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. 110 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) 111 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) 112 #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) 113 #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) 114 #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (1U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. 115 #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) 116 #define BSP_FEATURE_BSP_NUM_PMSAR (0U) 117 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) 118 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) 119 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) 120 #define BSP_FEATURE_BSP_OSIS_PADDING (1) 121 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) 122 #define BSP_FEATURE_BSP_RESET_TRNG (1U) 123 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). 124 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). 125 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. 126 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. 127 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). 128 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0U) // The maximum frequency allowed without having two ROM wait cycles. 129 #define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14) 130 #define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) \ 131 + \ 132 BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) 133 #define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (1U) 134 135 #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) 136 #define BSP_FEATURE_CANFD_LITE (0U) 137 #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU 138 #define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) 139 140 #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) 141 #define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) 142 #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) 143 #define BSP_FEATURE_CAN_NUM_CHANNELS (1U) 144 145 #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) 146 #define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK 147 #define BSP_FEATURE_CGC_HAS_CPUCLK (0U) 148 #define BSP_FEATURE_CGC_HAS_FCLK (1U) 149 #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) 150 #define BSP_FEATURE_CGC_HAS_FLL (0U) 151 #define BSP_FEATURE_CGC_HAS_FLWT (0U) 152 #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) 153 #define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) 154 #define BSP_FEATURE_CGC_HAS_PCLKA (1U) 155 #define BSP_FEATURE_CGC_HAS_PCLKB (1U) 156 #define BSP_FEATURE_CGC_HAS_PCLKC (1U) 157 #define BSP_FEATURE_CGC_HAS_PCLKD (1U) 158 #define BSP_FEATURE_CGC_HAS_PCLKE (0U) 159 #define BSP_FEATURE_CGC_HAS_PLL (1U) 160 #define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. 161 #define BSP_FEATURE_CGC_HAS_SOPCCR (1U) 162 #define BSP_FEATURE_CGC_HAS_SOSC (1U) 163 #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. 164 #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) 165 #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) 166 #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) 167 #define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) 168 #define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) 169 #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) 170 #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) 171 #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz 172 #define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz 173 #define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz 174 #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) 175 #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk) 176 #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) 177 #define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0U) 178 #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1U) 179 #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0U) 180 #define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (64000000U) 181 #define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (24000000U) 182 #define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (12500000U) 183 #define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (4000000U) 184 #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU 185 #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU 186 #define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU 187 #define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU 188 #define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) 189 #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) // This MCU does not use PLLCCR to set PLL frequency 190 #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP 191 #define BSP_FEATURE_CGC_REGISTER_SET_B (0) 192 #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4M1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB 193 #define BSP_FEATURE_CGC_SODRV_MASK (0x03U) 194 #define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) 195 #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) 196 #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) 197 #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) 198 #define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU 199 #define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) 200 #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44044444) 201 #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) 202 #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) 203 204 #define BSP_FEATURE_CRC_HAS_SNOOP (1U) 205 #define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) 206 #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1) 207 #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) 208 209 #define BSP_FEATURE_CRYPTO_HAS_AES (1) 210 #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) 211 #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) 212 #define BSP_FEATURE_CRYPTO_HAS_ECC (0) 213 #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) 214 #define BSP_FEATURE_CRYPTO_HAS_HASH (0) 215 #define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU 216 #define BSP_FEATURE_CRYPTO_HAS_RSA (0) 217 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) 218 #define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) 219 #define BSP_FEATURE_CRYPTO_HAS_SCE5 (1) 220 #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) 221 #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) 222 #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU 223 224 #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) 225 #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (5U) 226 #define BSP_FEATURE_CTSU_HAS_TXVSEL (0) 227 #define BSP_FEATURE_CTSU_VERSION (1) 228 229 #define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0U) 230 #define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0U) 231 #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) 232 #define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) 233 234 #define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Do not need to select ADC Unit on this MCU 235 #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) 236 #define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) 237 #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) 238 #define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U) 239 #define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) 240 #define BSP_FEATURE_DAC_MAX_CHANNELS (1U) 241 242 #define BSP_FEATURE_DMAC_HAS_DELSR (0U) 243 #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) 244 #define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) 245 246 #define BSP_FEATURE_DOC_VERSION (1U) 247 248 #define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M1 has Data Watchpoint Cycle Count Register 249 250 #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Deprecated (Removing in FSP v6.0) 251 #define BSP_FEATURE_ELC_VERSION (1U) 252 253 #define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU 254 #define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU 255 #define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU 256 257 #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) 258 #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) 259 #define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU 260 #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU 261 #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU 262 #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU 263 #define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU 264 #define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU 265 #define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU 266 #define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU 267 #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) 268 #define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU 269 #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) 270 #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) 271 #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) 272 #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) 273 #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) 274 #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) 275 #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4M1 FlashIF uses FCLK 276 #define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU 277 #define BSP_FEATURE_FLASH_LP_VERSION (3) 278 #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) 279 #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) 280 281 #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3) 282 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) 283 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) 284 #define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) 285 #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU 286 #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU 287 #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU 288 #define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU 289 #define BSP_FEATURE_GPT_TPCS_SHIFT (1U) 290 #define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFF) 291 292 #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU 293 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU 294 #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU 295 #define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU 296 297 #define BSP_FEATURE_ICU_HAS_FILTER (1U) 298 #define BSP_FEATURE_ICU_HAS_IELSR (1U) 299 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) 300 #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) 301 #define BSP_FEATURE_ICU_SBYEDCR_MASK (0U) // Feature not available on this MCU 302 #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xDFFFU) 303 #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB9FDFFFU) 304 #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) 305 306 #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) 307 #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU 308 #define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU 309 #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) 310 #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) 311 #define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU 312 313 #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) 314 #define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) 315 #define BSP_FEATURE_IOPORT_VERSION (1U) 316 317 #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) 318 #define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0U) // Feature not available on this MCU 319 320 #define BSP_FEATURE_KINT_HAS_MSTP (0U) 321 322 #define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU 323 #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) 324 #define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU 325 #define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU 326 #define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) 327 #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) 328 #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) 329 #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) 330 #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) 331 #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) 332 #define BSP_FEATURE_LPM_HAS_LPSCR (0U) 333 #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) 334 #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) 335 #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) 336 #define BSP_FEATURE_LPM_HAS_SNOOZE (1U) 337 #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) 338 #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) 339 #define BSP_FEATURE_LPM_HAS_STCONR (0U) 340 #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0U) // Feature not available on this MCU 341 #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0U) // Feature not available on this MCU 342 #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0U) // Feature not available on this MCU 343 #define BSP_FEATURE_LPM_SNOOZE_REQUEST_DTCST_DTCST (0U) // Feature not available on this MCU 344 #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) 345 #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) 346 #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382DFFFU) 347 #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) 348 349 #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) 350 #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) 351 #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) 352 #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V 353 #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V 354 #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V 355 #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V 356 #define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled 357 #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // LVD2 operation stabilization time after LVD2 is enabled 358 #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) 359 #define BSP_FEATURE_LVD_VERSION (1U) 360 361 #define BSP_FEATURE_MACL_SUPPORTED (0U) 362 363 #define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) 364 #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) 365 #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) 366 #define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (1U) 367 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) 368 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. 369 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported 370 #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) 371 #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0xFU) 372 373 #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) 374 #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) 375 376 #define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) 377 378 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) 379 380 #define BSP_FEATURE_RTC_IS_AVAILABLE (1U) 381 #define BSP_FEATURE_RTC_IS_IRTC (0U) 382 #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) 383 #define BSP_FEATURE_RTC_HAS_TCEN (1U) 384 #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) 385 #define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) 386 387 #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU 388 389 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) 390 #define BSP_FEATURE_SCI_CHANNELS (0x207U) 391 #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) 392 #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU 393 #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) 394 #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) 395 #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) 396 #define BSP_FEATURE_SCI_VERSION (1U) 397 #define BSP_FEATURE_SCI_LIN_CHANNELS (0U) // Feature not available on this MCU 398 399 #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) 400 #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU 401 #define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU 402 #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU 403 #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU 404 405 #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) 406 407 #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (1U) 408 #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (1U) 409 #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (38U) 410 #define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) 411 #define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (6U) 412 #define BSP_FEATURE_SLCDC_CONTRAST_MAX (15U) 413 414 #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) 415 #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) 416 #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) 417 #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) 418 #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) 419 420 #define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU 421 422 #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (8U) 423 #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) 424 425 #define BSP_FEATURE_TAU_CLOCK_SOURCE (NULL) // Feature not available on this MCU 426 #define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0) // Feature not available on this MCU 427 428 #define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0U) // Feature not available on this MCU 429 #define BSP_FEATURE_TML_NUM_CHANNELS (0) // Feature not available on this MCU 430 #define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU 431 432 #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU 433 434 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) 435 #define BSP_FEATURE_TZ_NS_OFFSET (0U) 436 #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) 437 #define BSP_FEATURE_TZ_HAS_DLM (0U) 438 #define BSP_FEATURE_TZ_VERSION (0U) 439 440 #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) 441 #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) 442 443 #define BSP_FEATURE_USB_NUM_IP (1U) 444 #define BSP_FEATURE_USB_HAS_USBHS (0U) 445 446 #endif 447
