1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_ELC_H 8 #define BSP_ELC_H 9 10 /*******************************************************************************************************************//** 11 * @addtogroup BSP_MCU_RA4E2 12 * @{ 13 **********************************************************************************************************************/ 14 15 /*********************************************************************************************************************** 16 * Macro definitions 17 **********************************************************************************************************************/ 18 19 /*********************************************************************************************************************** 20 * Typedef definitions 21 **********************************************************************************************************************/ 22 23 /*********************************************************************************************************************** 24 * Exported global variables 25 **********************************************************************************************************************/ 26 27 /*********************************************************************************************************************** 28 * Exported global functions (to be accessed by other files) 29 **********************************************************************************************************************/ 30 31 /* UNCRUSTIFY-OFF */ 32 33 /** Sources of event signals to be linked to other peripherals or the CPU 34 * @note This list is device specific. 35 * */ 36 typedef enum e_elc_event_ra4e2 37 { 38 ELC_EVENT_NONE = (0x0), // Link disabled 39 ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 40 ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 41 ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 42 ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 43 ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 44 ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 45 ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 46 ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 47 ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 48 ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 49 ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 50 ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 51 ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 52 ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 53 ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 54 ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end 55 ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end 56 ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end 57 ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end 58 ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end 59 ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end 60 ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end 61 ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end 62 ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete 63 ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error 64 ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode 65 ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt 66 ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt 67 ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt 68 ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt 69 ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop 70 ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry 71 ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt 72 ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A 73 ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B 74 ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt 75 ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A 76 ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B 77 ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow 78 ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT0 underflow 79 ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt 80 ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt 81 ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt 82 ELC_EVENT_CAN_RXF = (0x059), // Global recieve FIFO interrupt 83 ELC_EVENT_CAN_GLERR = (0x05A), // Global error 84 ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 85 ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 86 ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt 87 ELC_EVENT_CAN0_CHERR = (0x064), // Channel error 88 ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO recieve interrupt 89 ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request 90 ELC_EVENT_CAN0_RXMB = (0x067), // Receive message buffer interrupt 91 ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt 92 ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt 93 ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty 94 ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full 95 ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt 96 ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt 97 ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt 98 ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt 99 ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt 100 ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt 101 ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt 102 ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event 103 ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event 104 ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event 105 ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event 106 ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 107 ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 108 ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt 109 ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt 110 ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt 111 ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt 112 ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A 113 ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B 114 ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C 115 ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D 116 ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E 117 ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F 118 ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow 119 ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow 120 ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish 121 ELC_EVENT_GPT0_AD_TRIG_A = (0x0C9), // A/D converter start request A 122 ELC_EVENT_GPT0_AD_TRIG_B = (0x0CA), // A/D converter start request B 123 ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0CB), // Capture/Compare match A 124 ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CC), // Capture/Compare match B 125 ELC_EVENT_GPT1_COMPARE_C = (0x0CD), // Compare match C 126 ELC_EVENT_GPT1_COMPARE_D = (0x0CE), // Compare match D 127 ELC_EVENT_GPT1_COMPARE_E = (0x0CF), // Compare match E 128 ELC_EVENT_GPT1_COMPARE_F = (0x0D0), // Compare match F 129 ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0D1), // Overflow 130 ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D2), // Underflow 131 ELC_EVENT_GPT1_PC = (0x0D3), // Period count function finish 132 ELC_EVENT_GPT1_AD_TRIG_A = (0x0D4), // A/D converter start request A 133 ELC_EVENT_GPT1_AD_TRIG_B = (0x0D5), // A/D converter start request B 134 ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A 135 ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B 136 ELC_EVENT_GPT4_COMPARE_C = (0x0EE), // Compare match C 137 ELC_EVENT_GPT4_COMPARE_D = (0x0EF), // Compare match D 138 ELC_EVENT_GPT4_COMPARE_E = (0x0F0), // Compare match E 139 ELC_EVENT_GPT4_COMPARE_F = (0x0F1), // Compare match F 140 ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0F2), // Overflow 141 ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0F3), // Underflow 142 ELC_EVENT_GPT4_PC = (0x0F4), // Period count function finish 143 ELC_EVENT_GPT4_AD_TRIG_A = (0x0F5), // A/D converter start request A 144 ELC_EVENT_GPT4_AD_TRIG_B = (0x0F6), // A/D converter start request B 145 ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0F7), // Capture/Compare match A 146 ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0F8), // Capture/Compare match B 147 ELC_EVENT_GPT5_COMPARE_C = (0x0F9), // Compare match C 148 ELC_EVENT_GPT5_COMPARE_D = (0x0FA), // Compare match D 149 ELC_EVENT_GPT5_COMPARE_E = (0x0FB), // Compare match E 150 ELC_EVENT_GPT5_COMPARE_F = (0x0FC), // Compare match F 151 ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0FD), // Overflow 152 ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0FE), // Underflow 153 ELC_EVENT_GPT5_PC = (0x0FF), // Period count function finish 154 ELC_EVENT_GPT5_AD_TRIG_A = (0x100), // A/D converter start request A 155 ELC_EVENT_GPT5_AD_TRIG_B = (0x101), // A/D converter start request B 156 ELC_EVENT_OPS_UVW_EDGE = (0x15C), // UVW edge event 157 ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation 158 ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B 159 ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt 160 ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt 161 ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match 162 ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch 163 ELC_EVENT_SCI0_RXI = (0x180), // Receive data full 164 ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty 165 ELC_EVENT_SCI0_TEI = (0x182), // Transmit end 166 ELC_EVENT_SCI0_ERI = (0x183), // Receive error 167 ELC_EVENT_SCI0_AM = (0x184), // Address match event 168 ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error 169 ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full 170 ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty 171 ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end 172 ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error 173 ELC_EVENT_SCI9_AM = (0x1BA), // Address match event 174 ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full 175 ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty 176 ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle 177 ELC_EVENT_SPI0_ERI = (0x1C7), // Error 178 ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event 179 ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full 180 ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty 181 ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle 182 ELC_EVENT_SPI1_ERI = (0x1CC), // Error 183 ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event 184 ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error 185 ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt 186 ELC_EVENT_I3C0_RESPONSE = (0x1DC), // Response status buffer full 187 ELC_EVENT_I3C0_COMMAND = (0x1DD), // Command buffer empty 188 ELC_EVENT_I3C0_IBI = (0x1DE), // IBI status buffer full 189 ELC_EVENT_I3C0_RX = (0x1DF), // Receive 190 ELC_EVENT_I3C0_TX = (0x1E0), // Transmit 191 ELC_EVENT_I3C0_RCV_STATUS = (0x1E1), // Receive status buffer full 192 ELC_EVENT_I3C0_HRESP = (0x1E2), // High priority response queue full 193 ELC_EVENT_I3C0_HCMD = (0x1E3), // High priority command queue empty 194 ELC_EVENT_I3C0_HRX = (0x1E4), // High priority rx data buffer full 195 ELC_EVENT_I3C0_HTX = (0x1E5), // High priority tx data buffer empty 196 ELC_EVENT_I3C0_TEND = (0x1E6), // Transmit end 197 ELC_EVENT_I3C0_EEI = (0x1E7), // Error 198 ELC_EVENT_I3C0_STEV = (0x1E8), // Synchronous timing 199 ELC_EVENT_I3C0_MREFOVF = (0x1E9), // MREF counter overflow 200 ELC_EVENT_I3C0_MREFCPT = (0x1EA), // MREF capture 201 ELC_EVENT_I3C0_AMEV = (0x1EB), // Additional master-initiated bus event 202 ELC_EVENT_I3C0_WU = (0x1EC), // Wake-up Condition Detection interrupt 203 ELC_EVENT_TRNG_RDREQ = (0x1F3) // TRNG Read Request 204 } elc_event_t; 205 206 #define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) 207 208 #define ELC_PERIPHERAL_NUM (24U) 209 #define BSP_OVERRIDE_ELC_PERIPHERAL_T 210 /** Possible peripherals to be linked to event signals 211 * @note This list is device specific. 212 * */ 213 typedef enum e_elc_peripheral 214 { 215 ELC_PERIPHERAL_GPT_A = (0), 216 ELC_PERIPHERAL_GPT_B = (1), 217 ELC_PERIPHERAL_GPT_C = (2), 218 ELC_PERIPHERAL_GPT_D = (3), 219 ELC_PERIPHERAL_GPT_E = (4), 220 ELC_PERIPHERAL_GPT_F = (5), 221 ELC_PERIPHERAL_GPT_G = (6), 222 ELC_PERIPHERAL_GPT_H = (7), 223 ELC_PERIPHERAL_ADC0 = (8), 224 ELC_PERIPHERAL_ADC0_B = (9), 225 ELC_PERIPHERAL_DAC0 = (12), 226 ELC_PERIPHERAL_IOPORT1 = (14), 227 ELC_PERIPHERAL_IOPORT2 = (15), 228 ELC_PERIPHERAL_IOPORT3 = (16), 229 ELC_PERIPHERAL_IOPORT4 = (17), 230 ELC_PERIPHERAL_I3C = (23) 231 } elc_peripheral_t; 232 233 /** Positions of event link set registers (ELSRs) available on this MCU */ 234 #define BSP_ELC_PERIPHERAL_MASK (0x0083D3FFU) 235 236 /* UNCRUSTIFY-ON */ 237 /** @} (end addtogroup BSP_MCU_RA4E2) */ 238 239 #endif 240
