1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 /***********************************************************************************************************************
8  * Includes   <System Includes> , "Project Includes"
9  **********************************************************************************************************************/
10 #include "bsp_api.h"
11 
12 /***********************************************************************************************************************
13  * Macro definitions
14  **********************************************************************************************************************/
15 #define RA_NOT_DEFINED    (0)
16 
17 /** OR in the HOCO frequency setting from bsp_clock_cfg.h with the OFS1 setting from bsp_cfg.h. */
18 #define BSP_ROM_REG_OFS1_SETTING                                             \
19     (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \
20      ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET))
21 
22 /** Build up SECMPUAC register based on MPU settings. */
23 #define BSP_ROM_REG_MPU_CONTROL_SETTING                     \
24     ((0xFFFFFCF0U) |                                        \
25      ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) |     \
26      ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) |     \
27      ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE) |      \
28      ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \
29      ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \
30      ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3))
31 
32 /*******************************************************************************************************************//**
33  * @addtogroup BSP_MCU
34  * @{
35  **********************************************************************************************************************/
36 
37 /***********************************************************************************************************************
38  * Typedef definitions
39  **********************************************************************************************************************/
40 
41 /***********************************************************************************************************************
42  * Exported global variables (to be accessed by other files)
43  **********************************************************************************************************************/
44 
45 /***********************************************************************************************************************
46  * Private global variables and functions
47  **********************************************************************************************************************/
48 
49 #if !BSP_CFG_BOOT_IMAGE
50 
51  #if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
52 
53 /** ID code definitions defined here. */
54 BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
55 {
56     BSP_CFG_ID_CODE_LONG_1,
57   #if BSP_FEATURE_BSP_OSIS_PADDING
58     0xFFFFFFFFU,
59   #endif
60     BSP_CFG_ID_CODE_LONG_2,
61   #if BSP_FEATURE_BSP_OSIS_PADDING
62     0xFFFFFFFFU,
63   #endif
64     BSP_CFG_ID_CODE_LONG_3,
65   #if BSP_FEATURE_BSP_OSIS_PADDING
66     0xFFFFFFFFU,
67   #endif
68     BSP_CFG_ID_CODE_LONG_4
69 };
70  #endif
71 
72  #if 33U != __CORTEX_M && 85U != __CORTEX_M // NOLINT(readability-magic-numbers)
73 
74  #if !defined(CONFIG_SOC_OPTION_SETTING_MEMORY)
75 /** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */
76 BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (BSP_SECTION_ROM_REGISTERS) =
77 {
78     (uint32_t) BSP_CFG_ROM_REG_OFS0,
79     (uint32_t) BSP_ROM_REG_OFS1_SETTING,
80   #if __MPU_PRESENT
81     ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU),
82     ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U),
83     ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU),
84     ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U),
85     ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU),
86     (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U),
87     ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU),
88     ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U),
89     (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U),
90     (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U),
91     (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U),
92     (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U),
93     (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
94   #endif
95 };
96  #endif /* !defined(CONFIG_SOC_OPTION_SETTING_MEMORY) */
97 
98  #elif BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1
99 
100   #if !BSP_TZ_NONSECURE_BUILD
101 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
102     BSP_CFG_ROM_REG_OFS0;
103 
104 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
105     0xFFFFFFFF;
106 
107 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 =
108     BSP_ROM_REG_OFS1_SETTING;
109 
110 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 =
111     BSP_CFG_ROM_REG_BPS0;
112 
113 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 =
114     BSP_CFG_ROM_REG_PBPS0;
115 
116   #endif
117 
118  #else                                 /* CM33 & CM85 parts */
119 
120   #if !BSP_TZ_NONSECURE_BUILD
121 
122 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
123     BSP_CFG_ROM_REG_OFS0;
124 
125    #if BSP_FEATURE_BSP_HAS_OFS2
126 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs2") g_bsp_rom_ofs2 =
127     BSP_CFG_ROM_REG_OFS2;
128 
129    #endif
130    #if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK
131 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_rom_dualsel =
132     BSP_CFG_ROM_REG_DUALSEL;
133 
134    #endif
135 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
136     0xFFFFFFFF;
137 
138   #else
139 
140 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_rom_ofs1 =
141     BSP_ROM_REG_OFS1_SETTING;
142 
143    #if BSP_FEATURE_BSP_HAS_OFS3
144 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3") g_bsp_rom_ofs3 =
145     BSP_CFG_ROM_REG_OFS3;
146 
147    #endif
148 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_rom_banksel =
149     0xFFFFFFFF;
150 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps0") g_bsp_rom_bps0 =
151     BSP_CFG_ROM_REG_BPS0;
152 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps1") g_bsp_rom_bps1 =
153     BSP_CFG_ROM_REG_BPS1;
154 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps2") g_bsp_rom_bps2 =
155     BSP_CFG_ROM_REG_BPS2;
156 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps3") g_bsp_rom_bps3 =
157     BSP_CFG_ROM_REG_BPS3;
158 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps0") g_bsp_rom_pbps0 =
159     BSP_CFG_ROM_REG_PBPS0;
160 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps1") g_bsp_rom_pbps1 =
161     BSP_CFG_ROM_REG_PBPS1;
162 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps2") g_bsp_rom_pbps2 =
163     BSP_CFG_ROM_REG_PBPS2;
164 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps3") g_bsp_rom_pbps3 =
165     BSP_CFG_ROM_REG_PBPS3;
166 
167   #endif
168 
169   #if !BSP_TZ_NONSECURE_BUILD
170 
171 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1_sec =
172     BSP_ROM_REG_OFS1_SETTING;
173 
174    #if BSP_FEATURE_BSP_HAS_OFS3
175 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sec") g_bsp_rom_ofs3_sec =
176     BSP_CFG_ROM_REG_OFS3;
177 
178    #endif
179 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_rom_banksel_sec =
180     0xFFFFFFFF;
181 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps_sec0 =
182     BSP_CFG_ROM_REG_BPS0;
183 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec1") g_bsp_rom_bps_sec1 =
184     BSP_CFG_ROM_REG_BPS1;
185 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec2") g_bsp_rom_bps_sec2 =
186     BSP_CFG_ROM_REG_BPS2;
187 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec3") g_bsp_rom_bps_sec3 =
188     BSP_CFG_ROM_REG_BPS3;
189 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps_sec0 =
190     BSP_CFG_ROM_REG_PBPS0;
191 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec1") g_bsp_rom_pbps_sec1 =
192     BSP_CFG_ROM_REG_PBPS1;
193 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec2") g_bsp_rom_pbps_sec2 =
194     BSP_CFG_ROM_REG_PBPS2;
195 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec3") g_bsp_rom_pbps_sec3 =
196     BSP_CFG_ROM_REG_PBPS3;
197 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_rom_ofs1_sel =
198     BSP_CFG_ROM_REG_OFS1_SEL;
199 
200    #if BSP_FEATURE_BSP_HAS_OFS3
201 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sel") g_bsp_rom_ofs3_sel =
202     BSP_CFG_ROM_REG_OFS3_SEL;
203 
204    #endif
205    #if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK
206 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_rom_banksel_sel =
207     BSP_CFG_ROM_REG_BANKSEL_SEL;
208 
209    #endif
210 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel0") g_bsp_rom_bps_sel0 =
211     BSP_CFG_ROM_REG_BPS_SEL0;
212 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel1") g_bsp_rom_bps_sel1 =
213     BSP_CFG_ROM_REG_BPS_SEL1;
214 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel2") g_bsp_rom_bps_sel2 =
215     BSP_CFG_ROM_REG_BPS_SEL2;
216 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel3") g_bsp_rom_bps_sel3 =
217     BSP_CFG_ROM_REG_BPS_SEL3;
218 
219   #endif
220 
221   #if 85U == __CORTEX_M && !BSP_TZ_NONSECURE_BUILD
222 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl0") g_bsp_rom_fsblctrl0 =
223     BSP_CFG_ROM_REG_FSBLCTRL0;
224 
225 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl1") g_bsp_rom_fsblctrl1 =
226     BSP_CFG_ROM_REG_FSBLCTRL1;
227 
228 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl2") g_bsp_rom_fsblctrl2 =
229     BSP_CFG_ROM_REG_FSBLCTRL2;
230 
231 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_sacc0") g_bsp_rom_sacc0 =
232     BSP_CFG_ROM_REG_SACC0;
233 
234 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_sacc1") g_bsp_rom_sacc1 =
235     BSP_CFG_ROM_REG_SACC1;
236 
237 BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_samr") g_bsp_rom_samr =
238     BSP_CFG_ROM_REG_SAMR;
239 
240   #endif
241 
242  #endif
243 
244 #endif
245 
246 /** @} (end addtogroup BSP_MCU) */
247