1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 /** @} (end addtogroup BSP_MCU) */
8 
9 #ifndef BSP_EXCEPTIONS_H
10  #define BSP_EXCEPTIONS_H
11 
12  #ifdef __cplusplus
13 extern "C" {
14  #endif
15 
16 /***********************************************************************************************************************
17  * Macro definitions
18  **********************************************************************************************************************/
19 
20 /***********************************************************************************************************************
21  * Typedef definitions
22  **********************************************************************************************************************/
23 
24 /* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */
25 typedef enum IRQn
26 {
27     Reset_IRQn            = -15,       /*  1 Reset Vector invoked on Power up and warm reset */
28     NonMaskableInt_IRQn   = -14,       /*  2 Non maskable Interrupt cannot be stopped or preempted */
29     HardFault_IRQn        = -13,       /*  3 Hard Fault all classes of Fault */
30     MemoryManagement_IRQn = -12,       /*  4 Memory Management MPU mismatch, including Access Violation and No Match */
31     BusFault_IRQn         = -11,       /*  5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */
32     UsageFault_IRQn       = -10,       /*  6 Usage Fault i.e. Undef Instruction, Illegal State Transition */
33     SecureFault_IRQn      = -9,        /*  7 Secure Fault Interrupt */
34     SVCall_IRQn           = -5,        /* 11 System Service Call via SVC instruction */
35     DebugMonitor_IRQn     = -4,        /* 12 Debug Monitor */
36     PendSV_IRQn           = -2,        /* 14 Pendable request for system service */
37     SysTick_IRQn          = -1,        /* 15 System Tick Timer */
38 } IRQn_Type;
39 
40  #ifdef __cplusplus
41 }
42  #endif
43 
44 #endif
45