1 /*
2 ** ###################################################################
3 ** Processors: RV32M1_zero_riscy
4 ** RV32M1_zero_riscy
5 **
6 ** Compilers: Keil ARM C/C++ Compiler
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** MCUXpresso Compiler
10 **
11 ** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
12 ** Version: rev. 1.0, 2018-10-02
13 ** Build: b180926
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2018 NXP
22 ** All rights reserved.
23 **
24 ** SPDX-License-Identifier: BSD-3-Clause
25 **
26 ** http: www.nxp.com
27 ** mail: support@nxp.com
28 **
29 ** Revisions:
30 ** - rev. 1.0 (2018-10-02)
31 ** Initial version.
32 **
33 ** ###################################################################
34 */
35
36 /*!
37 * @file RV32M1_zero_riscy
38 * @version 1.0
39 * @date 2018-10-02
40 * @brief Device specific configuration file for RV32M1_zero_riscy
41 * (implementation file)
42 *
43 * Provides a system configuration function and a global variable that contains
44 * the system frequency. It configures the device and initializes the oscillator
45 * (PLL) that is part of the microcontroller device.
46 */
47
48 #include <stdint.h>
49 #include "fsl_device_registers.h"
50 #include "fsl_common.h"
51
52 typedef void (*irq_handler_t)(void);
53
54 extern void CTI1_IRQHandler(void);
55 extern void DMA1_04_DriverIRQHandler(void);
56 extern void DMA1_15_DriverIRQHandler(void);
57 extern void DMA1_26_DriverIRQHandler(void);
58 extern void DMA1_37_DriverIRQHandler(void);
59 extern void DMA1_Error_DriverIRQHandler(void);
60 extern void CMC1_IRQHandler(void);
61 extern void LLWU1_IRQHandler(void);
62 extern void MUB_IRQHandler(void);
63 extern void WDOG1_IRQHandler(void);
64 extern void CAU3_Task_Complete_IRQHandler(void);
65 extern void CAU3_Security_Violation_IRQHandler(void);
66 extern void TRNG_IRQHandler(void);
67 extern void LPIT1_IRQHandler(void);
68 extern void LPTMR2_IRQHandler(void);
69 extern void TPM3_IRQHandler(void);
70 extern void LPI2C3_DriverIRQHandler(void);
71 extern void RF0_0_IRQHandler(void);
72 extern void RF0_1_IRQHandler(void);
73 extern void LPSPI3_DriverIRQHandler(void);
74 extern void LPUART3_DriverIRQHandler(void);
75 extern void PORTE_IRQHandler(void);
76 extern void LPCMP1_IRQHandler(void);
77 extern void RTC_IRQHandler(void);
78 extern void INTMUX1_0_DriverIRQHandler(void);
79 extern void INTMUX1_1_DriverIRQHandler(void);
80 extern void INTMUX1_2_DriverIRQHandler(void);
81 extern void INTMUX1_3_DriverIRQHandler(void);
82 extern void INTMUX1_4_DriverIRQHandler(void);
83 extern void INTMUX1_5_DriverIRQHandler(void);
84 extern void INTMUX1_6_DriverIRQHandler(void);
85 extern void INTMUX1_7_DriverIRQHandler(void);
86 extern void EWM_IRQHandler(void);
87 extern void FTFE_Command_Complete_IRQHandler(void);
88 extern void FTFE_Read_Collision_IRQHandler(void);
89 extern void SPM_IRQHandler(void);
90 extern void SCG_IRQHandler(void);
91 extern void LPIT0_IRQHandler(void);
92 extern void LPTMR0_IRQHandler(void);
93 extern void LPTMR1_IRQHandler(void);
94 extern void TPM0_IRQHandler(void);
95 extern void TPM1_IRQHandler(void);
96 extern void TPM2_IRQHandler(void);
97 extern void EMVSIM0_IRQHandler(void);
98 extern void FLEXIO0_DriverIRQHandler(void);
99 extern void LPI2C0_DriverIRQHandler(void);
100 extern void LPI2C1_DriverIRQHandler(void);
101 extern void LPI2C2_DriverIRQHandler(void);
102 extern void I2S0_DriverIRQHandler(void);
103 extern void USDHC0_DriverIRQHandler(void);
104 extern void LPSPI0_DriverIRQHandler(void);
105 extern void LPSPI1_DriverIRQHandler(void);
106 extern void LPSPI2_DriverIRQHandler(void);
107 extern void LPUART0_DriverIRQHandler(void);
108 extern void LPUART1_DriverIRQHandler(void);
109 extern void LPUART2_DriverIRQHandler(void);
110 extern void USB0_IRQHandler(void);
111 extern void PORTA_IRQHandler(void);
112 extern void PORTB_IRQHandler(void);
113 extern void PORTC_IRQHandler(void);
114 extern void PORTD_IRQHandler(void);
115 extern void ADC0_IRQHandler(void);
116 extern void LPCMP0_IRQHandler(void);
117 extern void LPDAC0_IRQHandler(void);
118 extern void DMA1_15_IRQHandler(void);
119 extern void DMA1_26_IRQHandler(void);
120 extern void DMA1_37_IRQHandler(void);
121 extern void DMA1_Error_IRQHandler(void);
122 extern void LPI2C3_IRQHandler(void);
123 extern void LPSPI3_IRQHandler(void);
124 extern void LPUART3_IRQHandler(void);
125 extern void INTMUX1_0_IRQHandler(void);
126 extern void INTMUX1_1_IRQHandler(void);
127 extern void INTMUX1_2_IRQHandler(void);
128 extern void INTMUX1_3_IRQHandler(void);
129 extern void INTMUX1_4_IRQHandler(void);
130 extern void INTMUX1_5_IRQHandler(void);
131 extern void INTMUX1_6_IRQHandler(void);
132 extern void INTMUX1_7_IRQHandler(void);
133 extern void FLEXIO0_IRQHandler(void);
134 extern void LPI2C0_IRQHandler(void);
135 extern void LPI2C1_IRQHandler(void);
136 extern void LPI2C2_IRQHandler(void);
137 extern void I2S0_IRQHandler(void);
138 extern void USDHC0_IRQHandler(void);
139 extern void LPSPI0_IRQHandler(void);
140 extern void LPSPI1_IRQHandler(void);
141 extern void LPSPI2_IRQHandler(void);
142 extern void LPUART0_IRQHandler(void);
143 extern void LPUART1_IRQHandler(void);
144 extern void LPUART2_IRQHandler(void);
145
146 /* ----------------------------------------------------------------------------
147 -- Core clock
148 ---------------------------------------------------------------------------- */
149
150 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
151
152 extern uint32_t __etext;
153 extern uint32_t __data_start__;
154 extern uint32_t __data_end__;
155
156 extern uint32_t __bss_start__;
157 extern uint32_t __bss_end__;
158
copy_section(uint32_t * p_load,uint32_t * p_vma,uint32_t * p_vma_end)159 static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
160 {
161 while(p_vma <= p_vma_end)
162 {
163 *p_vma = *p_load;
164 ++p_load;
165 ++p_vma;
166 }
167 }
168
zero_section(uint32_t * start,uint32_t * end)169 static void zero_section(uint32_t * start, uint32_t * end)
170 {
171 uint32_t * p_zero = start;
172
173 while(p_zero <= end)
174 {
175 *p_zero = 0;
176 ++p_zero;
177 }
178 }
179
180 #define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
181 void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
182
183 #define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
184
185 DEFINE_DEFAULT_IRQ_HANDLER(CTI1_IRQHandler);
186 DEFINE_DEFAULT_IRQ_HANDLER(DMA1_04_DriverIRQHandler);
187 DEFINE_DEFAULT_IRQ_HANDLER(DMA1_15_DriverIRQHandler);
188 DEFINE_DEFAULT_IRQ_HANDLER(DMA1_26_DriverIRQHandler);
189 DEFINE_DEFAULT_IRQ_HANDLER(DMA1_37_DriverIRQHandler);
190 DEFINE_DEFAULT_IRQ_HANDLER(DMA1_Error_DriverIRQHandler);
191 DEFINE_DEFAULT_IRQ_HANDLER(CMC1_IRQHandler);
192 DEFINE_DEFAULT_IRQ_HANDLER(LLWU1_IRQHandler);
193 DEFINE_DEFAULT_IRQ_HANDLER(MUB_IRQHandler);
194 DEFINE_DEFAULT_IRQ_HANDLER(WDOG1_IRQHandler);
195 DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
196 DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
197 DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
198 DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
199 DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
200 DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
201 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
202 DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
203 DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
204 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
205 DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
206 DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
207 DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
208 DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
209 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_0_DriverIRQHandler);
210 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_1_DriverIRQHandler);
211 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_2_DriverIRQHandler);
212 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_3_DriverIRQHandler);
213 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_4_DriverIRQHandler);
214 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_5_DriverIRQHandler);
215 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_6_DriverIRQHandler);
216 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_7_DriverIRQHandler);
217 DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
218 DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
219 DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
220 DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
221 DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
222 DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
223 DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
224 DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
225 DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
226 DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
227 DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
228 DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
229 DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
230 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
231 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
232 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
233 DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
234 DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
235 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
236 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
237 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
238 DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
239 DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
240 DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
241 DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
242 DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
243 DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
244 DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
245 DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
246 DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
247 DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
248 DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
249
250 DEFINE_IRQ_HANDLER(DMA1_04_IRQHandler, DMA1_04_DriverIRQHandler);
251 DEFINE_IRQ_HANDLER(DMA1_15_IRQHandler, DMA1_15_DriverIRQHandler);
252 DEFINE_IRQ_HANDLER(DMA1_26_IRQHandler, DMA1_26_DriverIRQHandler);
253 DEFINE_IRQ_HANDLER(DMA1_37_IRQHandler, DMA1_37_DriverIRQHandler);
254 DEFINE_IRQ_HANDLER(DMA1_Error_IRQHandler, DMA1_Error_DriverIRQHandler);
255 DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
256 DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
257 DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
258 DEFINE_IRQ_HANDLER(INTMUX1_0_IRQHandler, INTMUX1_0_DriverIRQHandler);
259 DEFINE_IRQ_HANDLER(INTMUX1_1_IRQHandler, INTMUX1_1_DriverIRQHandler);
260 DEFINE_IRQ_HANDLER(INTMUX1_2_IRQHandler, INTMUX1_2_DriverIRQHandler);
261 DEFINE_IRQ_HANDLER(INTMUX1_3_IRQHandler, INTMUX1_3_DriverIRQHandler);
262 DEFINE_IRQ_HANDLER(INTMUX1_4_IRQHandler, INTMUX1_4_DriverIRQHandler);
263 DEFINE_IRQ_HANDLER(INTMUX1_5_IRQHandler, INTMUX1_5_DriverIRQHandler);
264 DEFINE_IRQ_HANDLER(INTMUX1_6_IRQHandler, INTMUX1_6_DriverIRQHandler);
265 DEFINE_IRQ_HANDLER(INTMUX1_7_IRQHandler, INTMUX1_7_DriverIRQHandler);
266 DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
267 DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
268 DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
269 DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
270 DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
271 DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
272 DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
273 DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
274 DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
275 DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
276 DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
277 DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
278
279 __attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
280 {
281 CTI1_IRQHandler,
282 DMA1_04_IRQHandler,
283 DMA1_15_IRQHandler,
284 DMA1_26_IRQHandler,
285 DMA1_37_IRQHandler,
286 DMA1_Error_IRQHandler,
287 CMC1_IRQHandler,
288 LLWU1_IRQHandler,
289 MUB_IRQHandler,
290 WDOG1_IRQHandler,
291 CAU3_Task_Complete_IRQHandler,
292 CAU3_Security_Violation_IRQHandler,
293 TRNG_IRQHandler,
294 LPIT1_IRQHandler,
295 LPTMR2_IRQHandler,
296 TPM3_IRQHandler,
297 LPI2C3_IRQHandler,
298 RF0_0_IRQHandler,
299 RF0_1_IRQHandler,
300 LPSPI3_IRQHandler,
301 LPUART3_IRQHandler,
302 PORTE_IRQHandler,
303 LPCMP1_IRQHandler,
304 RTC_IRQHandler,
305 INTMUX1_0_IRQHandler,
306 INTMUX1_1_IRQHandler,
307 INTMUX1_2_IRQHandler,
308 INTMUX1_3_IRQHandler,
309 INTMUX1_4_IRQHandler,
310 INTMUX1_5_IRQHandler,
311 INTMUX1_6_IRQHandler,
312 INTMUX1_7_IRQHandler,
313 EWM_IRQHandler,
314 FTFE_Command_Complete_IRQHandler,
315 FTFE_Read_Collision_IRQHandler,
316 SPM_IRQHandler,
317 SCG_IRQHandler,
318 LPIT0_IRQHandler,
319 LPTMR0_IRQHandler,
320 LPTMR1_IRQHandler,
321 TPM0_IRQHandler,
322 TPM1_IRQHandler,
323 TPM2_IRQHandler,
324 EMVSIM0_IRQHandler,
325 FLEXIO0_IRQHandler,
326 LPI2C0_IRQHandler,
327 LPI2C1_IRQHandler,
328 LPI2C2_IRQHandler,
329 I2S0_IRQHandler,
330 USDHC0_IRQHandler,
331 LPSPI0_IRQHandler,
332 LPSPI1_IRQHandler,
333 LPSPI2_IRQHandler,
334 LPUART0_IRQHandler,
335 LPUART1_IRQHandler,
336 LPUART2_IRQHandler,
337 USB0_IRQHandler,
338 PORTA_IRQHandler,
339 PORTB_IRQHandler,
340 PORTC_IRQHandler,
341 PORTD_IRQHandler,
342 ADC0_IRQHandler,
343 LPCMP0_IRQHandler,
344 LPDAC0_IRQHandler,
345 };
346
347 extern uint32_t __VECTOR_TABLE[];
348
349 static uint32_t irqNesting = 0;
350
DefaultIRQHandler(void)351 static void DefaultIRQHandler(void)
352 {
353 for (;;)
354 {
355 }
356 }
357
358 /* ----------------------------------------------------------------------------
359 -- SystemInit()
360 ---------------------------------------------------------------------------- */
361
SystemInit(void)362 void SystemInit (void) {
363 #if (DISABLE_WDOG)
364 WDOG1->CNT = 0xD928C520U;
365 WDOG1->TOVAL = 0xFFFF;
366 WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
367 #endif /* (DISABLE_WDOG) */
368
369 SystemInitHook();
370
371 copy_section(&__etext, &__data_start__, &__data_end__);
372 zero_section(&__bss_start__, &__bss_end__);
373
374 /* Setup the vector table address. */
375 irqNesting = 0;
376
377 __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
378 __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
379
380 /* Clear all pending flags. */
381 EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
382 EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
383 /* Set all interrupt as secure interrupt. */
384 EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
385 }
386
387 /* ----------------------------------------------------------------------------
388 -- SystemCoreClockUpdate()
389 ---------------------------------------------------------------------------- */
390
SystemCoreClockUpdate(void)391 void SystemCoreClockUpdate (void) {
392
393 uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */
394 uint16_t Divider;
395 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
396
397 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
398 case 0x1:
399 /* System OSC */
400 SCGOUTClock = CPU_XTAL_CLK_HZ;
401 break;
402 case 0x2:
403 /* Slow IRC */
404 SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
405 break;
406 case 0x3:
407 /* Fast IRC */
408 SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
409 break;
410 case 0x5:
411 /* Low Power FLL */
412 SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
413 break;
414 default:
415 return;
416 }
417 SystemCoreClock = (SCGOUTClock / Divider);
418 }
419
420 /* ----------------------------------------------------------------------------
421 -- SystemInitHook()
422 ---------------------------------------------------------------------------- */
423
SystemInitHook(void)424 __attribute__ ((weak)) void SystemInitHook (void) {
425 /* Void implementation of the weak function. */
426 }
427
428 #if defined(__IAR_SYSTEMS_ICC__)
429 #pragma weak SystemIrqHandler
SystemIrqHandler(uint32_t mcause)430 void SystemIrqHandler(uint32_t mcause) {
431 #elif defined(__GNUC__)
432 __attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
433 #else
434 #error Not supported compiler type
435 #endif
436 uint32_t intNum;
437
438 if (mcause & 0x80000000) /* For external interrupt. */
439 {
440 intNum = mcause & 0x1FUL;
441
442 irqNesting++;
443
444 /* Clear pending flag in EVENT unit .*/
445 EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
446
447 /* Read back to make sure write finished. */
448 (void)(EVENT_UNIT->INTPTPENDCLEAR);
449
450 __enable_irq(); /* Support nesting interrupt */
451
452 /* Now call the real irq handler for intNum */
453 isrTable[intNum]();
454
455 __disable_irq();
456
457 irqNesting--;
458 }
459 }
460
461 /* Use LIPT1 channel 0 for systick. */
462 #define SYSTICK_LPIT LPIT1
463 #define SYSTICK_LPIT_CH 0
464 #define SYSTICK_LPIT_IRQn LPIT1_IRQn
465
466 /* Leverage LPIT0 to provide Systick */
467 void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
468 {
469 /* Init pit module */
470 CLOCK_EnableClock(kCLOCK_Lpit1);
471
472 /* Reset the timer channels and registers except the MCR register */
473 SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
474 SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
475
476 /* Setup timer operation in debug and doze modes and enable the module */
477 SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
478
479 /* Set timer period for channel 0 */
480 SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1;
481
482 /* Enable timer interrupts for channel 0 */
483 SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
484
485 /* Set interrupt priority. */
486 EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
487
488 /* Enable interrupt at the EVENT unit */
489 EnableIRQ(SYSTICK_LPIT_IRQn);
490
491 /* Start channel 0 */
492 SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
493 }
494
495 uint32_t SystemGetIRQNestingLevel(void)
496 {
497 return irqNesting;
498 }
499
500 void SystemClearSystickFlag(void)
501 {
502 /* Channel 0. */
503 SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
504 }
505
506 void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
507 {
508 uint8_t regIdx;
509 uint8_t regOffset;
510
511 if ((IRQn < 32) && (intPriority < 8))
512 {
513 /*
514 * 4 priority control registers, each register controls 8 interrupts.
515 * Bit 0-2: interrupt 0
516 * Bit 4-7: interrupt 1
517 * ...
518 * Bit 28-30: interrupt 7
519 */
520 regIdx = IRQn >> 3U;
521 regOffset = (IRQn & 0x07U) * 4U;
522
523 EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
524 }
525 }
526
527 bool SystemInISR(void)
528 {
529 return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
530 }
531
532 void EVENT_SystemReset(void)
533 {
534 EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
535 }
536
