1/* ------------------------------------------------------------------------- */
2/*  @file:    startup_RV32M1_zero_riscy.s                                    */
3/*  @purpose: ZERO_RISCY Core Device Startup File                            */
4/*            RV32M1_zero_riscy                                              */
5/*  @version: 1.0                                                            */
6/*  @date:    2018-10-2                                                      */
7/*  @build:   b180926                                                        */
8/* ------------------------------------------------------------------------- */
9/*                                                                           */
10/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
11/* Copyright 2016-2018 NXP                                                   */
12/* All rights reserved.                                                      */
13/*                                                                           */
14/* SPDX-License-Identifier: BSD-3-Clause                                     */
15
16// Copyright 2017 ETH Zurich and University of Bologna.
17// Copyright and related rights are licensed under the Solderpad Hardware
18// License, Version 0.51 (the "License"); you may not use this file except in
19// compliance with the License.  You may obtain a copy of the License at
20// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
21// or agreed to in writing, software, hardware and materials distributed under
22// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
23// CONDITIONS OF ANY KIND, either express or implied. See the License for the
24// specific language governing permissions and limitations under the License.
25
26#define EXCEPTION_STACK_SIZE 0x58
27
28    .text
29    .section .vectors, "ax"
30    .option norvc;
31
32    jal x0, IRQ_Handler
33    jal x0, IRQ_Handler
34    jal x0, IRQ_Handler
35    jal x0, IRQ_Handler
36    jal x0, IRQ_Handler
37    jal x0, IRQ_Handler
38    jal x0, IRQ_Handler
39    jal x0, IRQ_Handler
40    jal x0, IRQ_Handler
41    jal x0, IRQ_Handler
42    jal x0, IRQ_Handler
43    jal x0, IRQ_Handler
44    jal x0, IRQ_Handler
45    jal x0, IRQ_Handler
46    jal x0, IRQ_Handler
47    jal x0, IRQ_Handler
48    jal x0, IRQ_Handler
49    jal x0, IRQ_Handler
50    jal x0, IRQ_Handler
51    jal x0, IRQ_Handler
52    jal x0, IRQ_Handler
53    jal x0, IRQ_Handler
54    jal x0, IRQ_Handler
55    jal x0, IRQ_Handler
56    jal x0, IRQ_Handler
57    jal x0, IRQ_Handler
58    jal x0, IRQ_Handler
59    jal x0, IRQ_Handler
60    jal x0, IRQ_Handler
61    jal x0, IRQ_Handler
62    jal x0, IRQ_Handler
63    jal x0, IRQ_Handler
64
65    // reset vector
66    jal x0, Reset_Handler
67
68    // Illegal instrution exception
69    jal x0, IllegalInstruction_Handler
70
71    // ecall handler
72    jal x0, Ecall_Handler
73
74    // LSU error
75    jal x0, LSU_Handler
76
77    .section .startup
78
79/* Reset Handler */
80Reset_Handler:
81
82    # Disable global interrupt. */
83    csrci mstatus, 8
84
85    # initialize stack pointer
86    la sp, __StackTop
87
88    # initialize global pointer
89    la gp, __global_pointer
90
91#ifndef __NO_SYSTEM_INIT
92    jal SystemInit
93#endif
94
95    call __libc_init_array
96
97    # Enable global interrupt. */
98    csrsi mstatus, 8
99
100    jal main
101    ebreak
102
103    .size Reset_Handler, . - Reset_Handler
104
105    .global _init
106    .global _fini
107_init:
108_fini:
109    ret
110
111  // saves all caller-saved registers (except return address)
112store_regs:
113    sw  x3, 0x00(x2)  // gp
114    sw  x4, 0x04(x2)  // tp
115    sw  x5, 0x08(x2)  // t0
116    sw  x6, 0x0c(x2)  // t1
117    sw  x7, 0x10(x2)  // t2
118    sw x10, 0x14(x2)  // a0
119    sw x11, 0x18(x2)  // a1
120    sw x12, 0x1c(x2)  // a2
121    sw x13, 0x20(x2)  // a3
122    sw x14, 0x24(x2)  // a4
123    sw x15, 0x28(x2)  // a5
124    sw x16, 0x2c(x2)  // a6
125    sw x17, 0x30(x2)  // a7
126
127    csrr a0, 0x7B0
128    csrr a1, 0x7B1
129    csrr a2, 0x7B2
130    sw a0, 0x34(x2)  // lpstart[0]
131    sw a1, 0x38(x2)  // lpend[0]
132    sw a2, 0x3c(x2)  // lpcount[0]
133    csrr a0, 0x7B4
134    csrr a1, 0x7B5
135    csrr a2, 0x7B6
136    sw a0, 0x40(x2)  // lpstart[1]
137    sw a1, 0x44(x2)  // lpend[1]
138    sw a2, 0x48(x2)  // lpcount[1]
139
140    csrr a0, 0x341
141    sw a0, 0x4c(x2)  // mepc
142    csrr a1, 0x300
143    sw a1, 0x50(x2)  // mstatus
144    jalr x0, x1
145
146    // load back registers from stack
147end_except:
148    lw a1, 0x50(x2)  // mstatus
149    csrrw x0, 0x300, a1
150    lw a0, 0x4c(x2)  // mepc
151    csrrw x0, 0x341, a0
152
153    lw a0, 0x40(x2)  // lpstart[1]
154    lw a1, 0x44(x2)  // lpend[1]
155    lw a2, 0x48(x2)  // lpcount[1]
156    csrrw x0, 0x7B4, a0
157    csrrw x0, 0x7B5, a1
158    csrrw x0, 0x7B6, a2
159    lw a0, 0x34(x2)  // lpstart[0]
160    lw a1, 0x38(x2)  // lpend[0]
161    lw a2, 0x3c(x2)  // lpcount[0]
162    csrrw x0, 0x7B0, a0
163    csrrw x0, 0x7B1, a1
164    csrrw x0, 0x7B2, a2
165
166    lw  x3, 0x00(x2)  // gp
167    lw  x4, 0x04(x2)  // tp
168    lw  x5, 0x08(x2)  // t0
169    lw  x6, 0x0c(x2)  // t1
170    lw  x7, 0x10(x2)  // t2
171    lw x10, 0x14(x2)  // a0
172    lw x11, 0x18(x2)  // a1
173    lw x12, 0x1c(x2)  // a2
174    lw x13, 0x20(x2)  // a3
175    lw x14, 0x24(x2)  // a4
176    lw x15, 0x28(x2)  // a5
177    lw x16, 0x2c(x2)  // a6
178    lw x17, 0x30(x2)  // a7
179
180    lw  x1, 0x54(x2)
181    addi x2, x2, EXCEPTION_STACK_SIZE
182    mret
183
184    .weak IRQ_Handler
185    .type IRQ_Handler, %function
186IRQ_Handler:
187    addi x2, x2, -EXCEPTION_STACK_SIZE
188    sw x1, 0x54(x2)
189    jal x1, store_regs
190    la x1, end_except
191    csrr a0, mcause
192    jal x0, SystemIrqHandler
193    .size IRQ_Handler, . - IRQ_Handler
194
195    .macro define_exception_entry entry_name handler_name
196    .weak \entry_name
197\entry_name:
198    addi x2, x2, -EXCEPTION_STACK_SIZE
199    sw x1, 0x54(x2)
200    jal x1, store_regs
201    la x1, end_except
202    jal x0, \handler_name
203    .endm
204
205define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
206define_exception_entry Ecall_Handler Ecall_HandlerFunc
207define_exception_entry LSU_Handler LSU_HandlerFunc
208
209    .weak IllegalInstruction_HandlerFunc
210    .type IllegalInstruction_HandlerFunc, %function
211IllegalInstruction_HandlerFunc:
212    j .
213    .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
214
215    .weak Ecall_HandlerFunc
216    .type Ecall_HandlerFunc, %function
217Ecall_HandlerFunc:
218    j .
219    .size Ecall_HandlerFunc, . - Ecall_HandlerFunc
220
221    .weak LSU_HandlerFunc
222    .type LSU_HandlerFunc, %function
223LSU_HandlerFunc:
224    j .
225    .size LSU_HandlerFunc, . - LSU_HandlerFunc
226