1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_xrdc.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 #define XRDC_DERR_W1_EST_VAL(w1) ((w1 & XRDC_DERR_W_EST_MASK) >> XRDC_DERR_W_EST_SHIFT)
16 #define XRDC_DERR_W1_EPORT_VAL(w1) ((w1 & XRDC_DERR_W_EPORT_MASK) >> XRDC_DERR_W_EPORT_SHIFT)
17 #define XRDC_DERR_W1_ERW_VAL(w1) ((w1 & XRDC_DERR_W_ERW_MASK) >> XRDC_DERR_W_ERW_SHIFT)
18 #define XRDC_DERR_W1_EATR_VAL(w1) ((w1 & XRDC_DERR_W_EATR_MASK) >> XRDC_DERR_W_EATR_SHIFT)
19 #define XRDC_DERR_W1_EDID_VAL(w1) ((w1 & XRDC_DERR_W_EDID_MASK) >> XRDC_DERR_W_EDID_SHIFT)
20
21 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP)
22 #define XRDC_MRGD_DXACP_WIDTH (3U) /* The width of XRDC_MRDG_DxACP. */
23 #elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL)
24 #define XRDC_MRGD_DXSEL_WIDTH (3U) /* The width of XRDC_MRDG_DxSEL. */
25 #endif
26 #define XRDC_PDAC_DXACP_WIDTH (3U) /* The width of XRDC_PDAC_DxACP. */
27
28 /* For the force exclusive accesss lock release procedure. */
29 #define XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL1 (0x02000046U) /* The width of XRDC_MRDG_DxACP. */
30 #define XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL2 (0x02000052U) /* The width of XRDC_PDAC_DxACP. */
31
32 /*******************************************************************************
33 * Variables
34 ******************************************************************************/
35 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
36 /* Clock name of XRDC. */
37 #if (FSL_CLOCK_XRDC_GATE_COUNT > 1)
38 static const clock_ip_name_t s_xrdcClock[] = XRDC_CLOCKS;
39 #endif
40 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
41
42 /*******************************************************************************
43 * Code
44 ******************************************************************************/
45
46 #if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || defined(__riscv))
47 /*!
48 * @brief Count the leading zeros.
49 *
50 * Count the leading zeros of an 32-bit data. This function is only defined
51 * for CM0 and CM0+ for IAR, because other cortex series have the clz instruction,
52 * KEIL and ARMGCC have toolchain build in function for this purpose.
53 *
54 * @param data The data to process.
55 * @return Count of the leading zeros.
56 */
XRDC_CountLeadingZeros(uint32_t data)57 static uint32_t XRDC_CountLeadingZeros(uint32_t data)
58 {
59 uint32_t count = 0U;
60 uint32_t mask = 0x80000000U;
61
62 while ((data & mask) == 0U)
63 {
64 count++;
65 mask >>= 1U;
66 }
67
68 return count;
69 }
70 #endif
71
XRDC_Init(XRDC_Type * base)72 void XRDC_Init(XRDC_Type *base)
73 {
74 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
75
76 #if FSL_CLOCK_XRDC_GATE_COUNT
77 #if (FSL_CLOCK_XRDC_GATE_COUNT == 1)
78 CLOCK_EnableClock(kCLOCK_Xrdc0);
79 #else
80 uint8_t i;
81
82 for (i = 0; i < ARRAY_SIZE(s_xrdcClock); i++)
83 {
84 CLOCK_EnableClock(s_xrdcClock[i]);
85 }
86 #endif
87 #endif
88
89 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
90 }
91
XRDC_Deinit(XRDC_Type * base)92 void XRDC_Deinit(XRDC_Type *base)
93 {
94 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
95
96 #if FSL_CLOCK_XRDC_GATE_COUNT
97 #if (FSL_CLOCK_XRDC_GATE_COUNT == 1)
98 CLOCK_EnableClock(kCLOCK_Xrdc0);
99 #else
100 uint8_t i;
101
102 for (i = 0; i < ARRAY_SIZE(s_xrdcClock); i++)
103 {
104 CLOCK_DisableClock(s_xrdcClock[i]);
105 }
106 #endif
107 #endif
108
109 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
110 }
111
XRDC_GetHardwareConfig(XRDC_Type * base,xrdc_hardware_config_t * config)112 void XRDC_GetHardwareConfig(XRDC_Type *base, xrdc_hardware_config_t *config)
113 {
114 assert(config);
115
116 config->masterNumber = ((base->HWCFG0 & XRDC_HWCFG0_NMSTR_MASK) >> XRDC_HWCFG0_NMSTR_SHIFT) + 1U;
117 config->domainNumber = ((base->HWCFG0 & XRDC_HWCFG0_NDID_MASK) >> XRDC_HWCFG0_NDID_SHIFT) + 1U;
118 config->pacNumber = ((base->HWCFG0 & XRDC_HWCFG0_NPAC_MASK) >> XRDC_HWCFG0_NPAC_SHIFT) + 1U;
119 config->mrcNumber = ((base->HWCFG0 & XRDC_HWCFG0_NMRC_MASK) >> XRDC_HWCFG0_NMRC_SHIFT) + 1U;
120 }
121
XRDC_GetAndClearFirstDomainError(XRDC_Type * base,xrdc_error_t * error)122 status_t XRDC_GetAndClearFirstDomainError(XRDC_Type *base, xrdc_error_t *error)
123 {
124 return XRDC_GetAndClearFirstSpecificDomainError(base, error, XRDC_GetCurrentMasterDomainId(base));
125 }
126
XRDC_GetAndClearFirstSpecificDomainError(XRDC_Type * base,xrdc_error_t * error,uint8_t domainId)127 status_t XRDC_GetAndClearFirstSpecificDomainError(XRDC_Type *base, xrdc_error_t *error, uint8_t domainId)
128 {
129 assert(error);
130
131 uint32_t errorBitMap; /* Domain error location bit map. */
132 uint32_t errorIndex; /* The index of first domain error. */
133 uint32_t regW1; /* To save XRDC_DERR_W1. */
134
135 /* Get the error bitmap. */
136 errorBitMap = base->DERRLOC[domainId];
137
138 if (!errorBitMap) /* No error captured. */
139 {
140 return kStatus_XRDC_NoError;
141 }
142
143 /* Get the first error controller index. */
144 #if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || defined(__riscv))
145 errorIndex = 31U - XRDC_CountLeadingZeros(errorBitMap);
146 #else
147 errorIndex = 31U - __CLZ(errorBitMap);
148 #endif
149
150 #if (defined(FSL_FEATURE_XRDC_HAS_FDID) && FSL_FEATURE_XRDC_HAS_FDID)
151 /* Must write FDID[FDID] with the domain ID before reading the Domain Error registers. */
152 base->FDID = XRDC_FDID_FDID(domainId);
153 #endif /* FSL_FEATURE_XRDC_HAS_FDID */
154 /* Get the error information. */
155 regW1 = base->DERR_W[errorIndex][1];
156 error->controller = (xrdc_controller_t)errorIndex;
157 error->address = base->DERR_W[errorIndex][0];
158 error->errorState = (xrdc_error_state_t)XRDC_DERR_W1_EST_VAL(regW1);
159 error->errorAttr = (xrdc_error_attr_t)XRDC_DERR_W1_EATR_VAL(regW1);
160 error->errorType = (xrdc_error_type_t)XRDC_DERR_W1_ERW_VAL(regW1);
161 error->errorPort = XRDC_DERR_W1_EPORT_VAL(regW1);
162 error->domainId = XRDC_DERR_W1_EDID_VAL(regW1);
163
164 /* Clear error pending. */
165 base->DERR_W[errorIndex][3] = XRDC_DERR_W_RECR(0x01U);
166
167 return kStatus_Success;
168 }
169
XRDC_GetMemAccessDefaultConfig(xrdc_mem_access_config_t * config)170 void XRDC_GetMemAccessDefaultConfig(xrdc_mem_access_config_t *config)
171 {
172 assert(config);
173
174 uint8_t i;
175
176 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE)
177 config->enableSema = false;
178 config->semaNum = 0U;
179 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SE */
180
181 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ)
182 config->size = kXRDC_MemSizeNone;
183 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */
184 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SRD) && FSL_FEATURE_XRDC_NO_MRGD_SRD)
185 config->subRegionDisableMask = 0U;
186 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SRD */
187
188 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR)
189 config->codeRegion = kXRDC_MemCodeRegion0;
190 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_CR */
191
192 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET)
193 config->enableAccset1Lock = false;
194 config->enableAccset2Lock = false;
195 config->accset1 = 0x000U;
196 config->accset2 = 0x000U;
197 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */
198
199 config->lockMode = kXRDC_AccessConfigLockWritable;
200
201 config->baseAddress = 0U;
202 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) && FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR)
203 config->endAddress = 0U;
204 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR */
205
206 for (i = 0U; i < FSL_FEATURE_XRDC_DOMAIN_COUNT; i++)
207 {
208 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP)
209 config->policy[i] = kXRDC_AccessPolicyNone;
210 #elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL)
211 config->policy[i] = kXRDC_AccessFlagsNone;
212 #endif
213 }
214
215 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL)
216 config->exclAccessLockMode = kXRDC_ExclAccessLockDisabled;
217 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_EAL */
218 }
219
XRDC_SetMemAccessConfig(XRDC_Type * base,const xrdc_mem_access_config_t * config)220 void XRDC_SetMemAccessConfig(XRDC_Type *base, const xrdc_mem_access_config_t *config)
221 {
222 assert(config);
223 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ)
224 /* Not allowed to set sub-region disable mask for memory region smaller than 256-bytes. */
225 assert(!((config->size < kXRDC_MemSize256B) && (config->subRegionDisableMask)));
226 /* Memory region minimum size = 32 bytes and base address must be aligned to 0-module-2**(SZ+1). */
227 assert(config->size >= kXRDC_MemSize32B);
228 assert(!(config->baseAddress & ((1U << (config->size + 1U)) - 1U)));
229 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */
230
231 uint32_t i;
232 uint32_t regValue;
233 uint8_t index = (uint8_t)config->mem;
234
235 /* Set MRGD_W0. */
236 base->MRGD[index].MRGD_W[0] = config->baseAddress;
237
238 /* Set MRGD_W1. */
239 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ)
240 base->MRGD[index].MRGD_W[1] = XRDC_MRGD_W_SZ(config->size) | XRDC_MRGD_W_SRD(config->subRegionDisableMask);
241 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */
242
243 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) && FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR)
244 base->MRGD[index].MRGD_W[1] = config->endAddress;
245 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR */
246
247 /* Set MRGD_W2. */
248 regValue = 0U;
249 /* Set MRGD_W2[D0ACP ~ D7ACP] or MRGD_W2[D0SEL ~ D2SEL]. */
250 #if (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 8U)
251 i = FSL_FEATURE_XRDC_DOMAIN_COUNT;
252 #elif(FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16U)
253 i = 8U;
254 #else
255 #error Does not support more than 16 domain.
256 #endif
257
258 while (i--)
259 {
260 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP)
261 regValue <<= XRDC_MRGD_DXACP_WIDTH;
262 #elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL)
263 regValue <<= XRDC_MRGD_DXSEL_WIDTH;
264 #endif
265 regValue |= config->policy[i];
266 }
267
268 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE)
269 regValue |= XRDC_MRGD_W_SE(config->enableSema) | XRDC_MRGD_W_SNUM(config->semaNum);
270 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SE */
271
272 base->MRGD[index].MRGD_W[2] = regValue;
273
274 /* Set MRGD_W3. */
275 regValue = 0U;
276
277 #if ((FSL_FEATURE_XRDC_DOMAIN_COUNT > 8U) && (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16))
278 /* Set MRGD_W3[D8ACP ~ D15ACP]. */
279 for (i = FSL_FEATURE_XRDC_DOMAIN_COUNT - 1U; i > 7U; i--)
280 {
281 regValue <<= XRDC_MRGD_DXACP_WIDTH;
282 regValue |= config->policy[i];
283 }
284 #endif
285
286 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR)
287 regValue |= XRDC_MRGD_W_CR(config->codeRegion);
288 #endif
289
290 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_W3_VLD) && FSL_FEATURE_XRDC_NO_MRGD_W3_VLD)
291 regValue |= XRDC_MRGD_W_VLD_MASK | XRDC_MRGD_W_LK2(config->lockMode);
292 #endif
293
294 base->MRGD[index].MRGD_W[3] = regValue;
295
296 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL)
297 /*
298 * Set MRGD_W3[EAL].
299 * If write with a value of MRGD_W3[EAL]=0, then the other fields of MRGD_W3 are updated.
300 * If write with a value of MRGD_W3[EAL]!=0, then only the EAL is updated.
301 */
302 if (kXRDC_ExclAccessLockDisabled != config->exclAccessLockMode)
303 {
304 base->MRGD[index].MRGD_W[3] = XRDC_MRGD_W_EAL(config->exclAccessLockMode);
305 }
306 #endif
307
308 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET)
309 /* Set MRGD_W4. */
310 base->MRGD[index].MRGD_W[4] = XRDC_MRGD_W_LKAS1(config->enableAccset1Lock) | XRDC_MRGD_W_ACCSET1(config->accset1) |
311 XRDC_MRGD_W_LKAS2(config->enableAccset2Lock) | XRDC_MRGD_W_ACCSET2(config->accset2) |
312 XRDC_MRGD_W_VLD_MASK | XRDC_MRGD_W_LK2(config->lockMode);
313 #endif
314 }
315
316 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL)
XRDC_SetMemExclAccessLockMode(XRDC_Type * base,xrdc_mem_t mem,xrdc_excl_access_lock_config_t lockMode)317 void XRDC_SetMemExclAccessLockMode(XRDC_Type *base, xrdc_mem_t mem, xrdc_excl_access_lock_config_t lockMode)
318 {
319 /* Write kXRDC_ExclAccessLockDisabled is not allowed. */
320 assert(kXRDC_ExclAccessLockDisabled != lockMode);
321
322 uint32_t reg = base->MRGD[mem].MRGD_W[4];
323
324 /* Step 1. Set the memory region exclusive access lock mode configuration. */
325 base->MRGD[mem].MRGD_W[3] = XRDC_MRGD_W_EAL(lockMode);
326
327 /* Step 2. Set MRGD_W3 will clear the MRGD_W4[VLD]. So should re-assert it. */
328 base->MRGD[mem].MRGD_W[4] = reg;
329 }
330
XRDC_ForceMemExclAccessLockRelease(XRDC_Type * base,xrdc_mem_t mem)331 void XRDC_ForceMemExclAccessLockRelease(XRDC_Type *base, xrdc_mem_t mem)
332 {
333 uint32_t primask;
334
335 primask = DisableGlobalIRQ();
336 base->MRGD[mem].MRGD_W[3] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL1;
337 base->MRGD[mem].MRGD_W[3] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL2;
338 EnableGlobalIRQ(primask);
339 }
340 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_EAL */
341
342 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET)
XRDC_SetMemAccsetLock(XRDC_Type * base,xrdc_mem_t mem,xrdc_mem_accset_t accset,bool lock)343 void XRDC_SetMemAccsetLock(XRDC_Type *base, xrdc_mem_t mem, xrdc_mem_accset_t accset, bool lock)
344 {
345 uint32_t lkasMask = 0U;
346
347 switch (accset)
348 {
349 case kXRDC_MemAccset1:
350 lkasMask = XRDC_MRGD_W_LKAS1_MASK;
351 break;
352 case kXRDC_MemAccset2:
353 lkasMask = XRDC_MRGD_W_LKAS2_MASK;
354 break;
355 default:
356 break;
357 }
358
359 if (lock)
360 {
361 base->MRGD[mem].MRGD_W[4] |= lkasMask;
362 }
363 else
364 {
365 base->MRGD[mem].MRGD_W[4] &= ~lkasMask;
366 }
367 }
368 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */
369
XRDC_GetPeriphAccessDefaultConfig(xrdc_periph_access_config_t * config)370 void XRDC_GetPeriphAccessDefaultConfig(xrdc_periph_access_config_t *config)
371 {
372 assert(config);
373
374 uint8_t i;
375
376 #if !(defined(FSL_FEATURE_XRDC_NO_PDAC_SE) && FSL_FEATURE_XRDC_NO_PDAC_SE)
377 config->enableSema = false;
378 config->semaNum = 0U;
379 #endif /* FSL_FEATURE_XRDC_NO_PDAC_SE */
380 config->lockMode = kXRDC_AccessConfigLockWritable;
381 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL)
382 config->exclAccessLockMode = kXRDC_ExclAccessLockDisabled;
383 #endif /* FSL_FEATURE_XRDC_HAS_PDAC_EAL */
384 for (i = 0U; i < FSL_FEATURE_XRDC_DOMAIN_COUNT; i++)
385 {
386 config->policy[i] = kXRDC_AccessPolicyNone;
387 }
388 }
389
XRDC_SetPeriphAccessConfig(XRDC_Type * base,const xrdc_periph_access_config_t * config)390 void XRDC_SetPeriphAccessConfig(XRDC_Type *base, const xrdc_periph_access_config_t *config)
391 {
392 assert(config);
393
394 uint32_t i;
395 uint32_t regValue;
396 uint8_t index = (uint8_t)config->periph;
397
398 /* Set PDAC_W0[D0ACP ~ D7ACP]. */
399 regValue = 0U;
400 #if (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 8U)
401 i = FSL_FEATURE_XRDC_DOMAIN_COUNT;
402 #elif(FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16U)
403 i = 8U;
404 #else
405 #error Does not support more than 16 domain.
406 #endif
407
408 while (i--)
409 {
410 regValue <<= XRDC_PDAC_DXACP_WIDTH;
411 regValue |= config->policy[i];
412 }
413
414 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE)
415 regValue |= (XRDC_PDAC_W_SE(config->enableSema) | XRDC_PDAC_W_SNUM(config->semaNum));
416 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SE */
417
418 /* Set PDAC_W0. */
419 base->PDAC_W[index][0U] = regValue;
420
421 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL)
422 /*
423 * If write with a value of PDAC_W1[EAL]=0, then the other fields of PDAC_W1 are updated.
424 * If write with a value of PDAC_W1[EAL]!=0, then only the EAL is updated.
425 */
426 base->PDAC_W[index][1U] = XRDC_PDAC_W_EAL(config->exclAccessLockMode);
427 #endif
428
429 regValue = 0U;
430 #if ((FSL_FEATURE_XRDC_DOMAIN_COUNT > 8U) && (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16))
431 /* Set PDAC_W1[D8ACP ~ D15ACP]. */
432
433 for (i = FSL_FEATURE_XRDC_DOMAIN_COUNT - 1U; i > 7U; i--)
434 {
435 regValue <<= XRDC_PDAC_DXACP_WIDTH;
436 regValue |= config->policy[i];
437 }
438 #endif
439 /* Set PDAC_W1. */
440 base->PDAC_W[index][1] = regValue | XRDC_PDAC_W_VLD_MASK | XRDC_PDAC_W_LK2(config->lockMode);
441 }
442
443 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL)
XRDC_ForcePeriphExclAccessLockRelease(XRDC_Type * base,xrdc_periph_t periph)444 void XRDC_ForcePeriphExclAccessLockRelease(XRDC_Type *base, xrdc_periph_t periph)
445 {
446 uint32_t primask;
447
448 primask = DisableGlobalIRQ();
449 base->PDAC_W[periph][1] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL1;
450 base->PDAC_W[periph][1] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL2;
451 EnableGlobalIRQ(primask);
452 }
453 #endif /* FSL_FEATURE_XRDC_HAS_PDAC_EAL */
454
