1 /* 2 * Copyright 2022-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /** 8 * @file Clock_Ip_Cfg.c 9 * @version 2.0.0 10 * 11 * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. 12 * @details Code template for Post-Build(PB) configuration file generation. 13 * 14 * @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver 15 * @{ 16 */ 17 18 19 #ifdef __cplusplus 20 extern "C"{ 21 #endif 22 23 24 /*================================================================================================== 25 INCLUDE FILES 26 1) system and project includes 27 2) needed interfaces from external units 28 3) internal and external interfaces from this unit 29 ==================================================================================================*/ 30 #include "Std_Types.h" 31 #include "Clock_Ip_Private.h" 32 33 /*================================================================================================== 34 * SOURCE FILE VERSION INFORMATION 35 ==================================================================================================*/ 36 #define CLOCK_IP_CFG_VENDOR_ID_C 43 37 #define CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C 4 38 #define CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C 7 39 #define CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C 0 40 #define CLOCK_IP_CFG_SW_MAJOR_VERSION_C 2 41 #define CLOCK_IP_CFG_SW_MINOR_VERSION_C 0 42 #define CLOCK_IP_CFG_SW_PATCH_VERSION_C 0 43 44 /*================================================================================================== 45 * FILE VERSION CHECKS 46 ==================================================================================================*/ 47 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 48 /* Check if source file and Std_Types.h file are of the same Autosar version */ 49 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != STD_AR_RELEASE_MAJOR_VERSION) || \ 50 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != STD_AR_RELEASE_MINOR_VERSION) \ 51 ) 52 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and Std_Types.h are different" 53 #endif 54 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */ 55 /* Check if source file and Clock_Ip_Private.h file are of the same vendor */ 56 #if (CLOCK_IP_CFG_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID) 57 #error "Clock_Ip_Cfg.c and Clock_Ip_Private.h have different vendor ids" 58 #endif 59 60 /* Check if source file and Clock_Ip_Private.h file are of the same Autosar version */ 61 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \ 62 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \ 63 (CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \ 64 ) 65 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Private.h are different" 66 #endif 67 68 /* Check if source file and Clock_Ip_Private.h file are of the same Software version */ 69 #if ((CLOCK_IP_CFG_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \ 70 (CLOCK_IP_CFG_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \ 71 (CLOCK_IP_CFG_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \ 72 ) 73 #error "Software Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Private.h are different" 74 #endif 75 76 /*================================================================================================== 77 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) 78 ==================================================================================================*/ 79 80 /*================================================================================================== 81 LOCAL MACROS 82 ==================================================================================================*/ 83 84 /*================================================================================================== 85 LOCAL CONSTANTS 86 ==================================================================================================*/ 87 88 /*================================================================================================== 89 LOCAL VARIABLES 90 ==================================================================================================*/ 91 92 /*================================================================================================== 93 GLOBAL CONSTANTS 94 ==================================================================================================*/ 95 96 /*================================================================================================== 97 GLOBAL VARIABLES 98 ==================================================================================================*/ 99 100 101 #define MCU_START_SEC_CONFIG_DATA_UNSPECIFIED 102 #include "Mcu_MemMap.h" 103 104 105 106 static const Clock_Ip_XoscConfigType Clock_Ip_XoscConfigurations_0[CLOCK_IP_CONFIGURED_XOSCS_0_NO] = { 107 108 #if CLOCK_IP_CONFIGURED_XOSCS_0_NO > 0U 109 { 110 FXOSC_CLK, /* Clock name associated to xosc */ 111 40000000U, /* External oscillator frequency. */ 112 1U, /* Enable xosc. */ 113 157U, /* Startup stabilization time. */ 114 0U, /* XOSC bypass option */ 115 1U, /* Comparator enable */ 116 12U, /* TransConductance */ 117 0U, /* Gain value */ 118 0U, /* Monitor type */ 119 0U, /* Automatic level controller */ 120 }, 121 #endif 122 }; 123 124 125 static const Clock_Ip_PllConfigType Clock_Ip_PllConfigurations_0[CLOCK_IP_CONFIGURED_PLLS_0_NO] = { 126 127 #if CLOCK_IP_CONFIGURED_PLLS_0_NO > 0U 128 { 129 COREPLL_CLK, /* name */ 130 1U, /* enable */ 131 FXOSC_CLK, /* inputReference */ 132 0U, /* Bypass */ 133 2U, /* predivider */ 134 0U, /* multiplier */ 135 0U, /* postdivider */ 136 0U, /* numeratorFracLoopDiv */ 137 100U, /* mulFactorDiv */ 138 1U, /* ModulationBypass */ 139 0U, /* Modulation type: Spread spectrum modulation bypassed */ 140 0U, /* modulationPeriod */ 141 0U, /* incrementStep */ 142 0U, /* sigmaDelta */ 143 0U, /* ditherControl */ 144 0U, /* ditherControlValue */ 145 0U, /* Monitor type */ 146 { /* Dividers */ 147 0U, 148 0U, 149 0U, 150 }, 151 0U, /* SoftwareDisable */ 152 }, 153 #endif 154 155 #if CLOCK_IP_CONFIGURED_PLLS_0_NO > 1U 156 { 157 PERIPHPLL_CLK, /* name */ 158 1U, /* enable */ 159 FXOSC_CLK, /* inputReference */ 160 0U, /* Bypass */ 161 2U, /* predivider */ 162 0U, /* multiplier */ 163 0U, /* postdivider */ 164 0U, /* numeratorFracLoopDiv */ 165 120U, /* mulFactorDiv */ 166 0U, /* ModulationBypass */ 167 0U, /* Modulation type: Spread spectrum modulation bypassed */ 168 0U, /* modulationPeriod */ 169 0U, /* incrementStep */ 170 0U, /* sigmaDelta */ 171 0U, /* ditherControl */ 172 0U, /* ditherControlValue */ 173 0U, /* Monitor type */ 174 { /* Dividers */ 175 0U, 176 0U, 177 0U, 178 }, 179 0U, /* SoftwareDisable */ 180 }, 181 #endif 182 183 #if CLOCK_IP_CONFIGURED_PLLS_0_NO > 2U 184 { 185 DDRPLL_CLK, /* name */ 186 1U, /* enable */ 187 FXOSC_CLK, /* inputReference */ 188 0U, /* Bypass */ 189 1U, /* predivider */ 190 0U, /* multiplier */ 191 0U, /* postdivider */ 192 0U, /* numeratorFracLoopDiv */ 193 40U, /* mulFactorDiv */ 194 1U, /* ModulationBypass */ 195 0U, /* Modulation type: Spread spectrum modulation bypassed */ 196 0U, /* modulationPeriod */ 197 0U, /* incrementStep */ 198 0U, /* sigmaDelta */ 199 0U, /* ditherControl */ 200 0U, /* ditherControlValue */ 201 0U, /* Monitor type */ 202 { /* Dividers */ 203 0U, 204 0U, 205 0U, 206 }, 207 0U, /* SoftwareDisable */ 208 }, 209 #endif 210 211 #if CLOCK_IP_CONFIGURED_PLLS_0_NO > 3U 212 { 213 LFAST0_PLL_CLK, /* name */ 214 1U, /* enable */ 215 P1_LFAST0_REF_CLK, /* inputReference */ 216 0U, /* Bypass */ 217 1U, /* predivider */ 218 0U, /* multiplier */ 219 0U, /* postdivider */ 220 0U, /* numeratorFracLoopDiv */ 221 20U, /* mulFactorDiv */ 222 0U, /* ModulationBypass */ 223 0U, /* Modulation type: Spread spectrum modulation bypassed */ 224 0U, /* modulationPeriod */ 225 0U, /* incrementStep */ 226 0U, /* sigmaDelta */ 227 0U, /* ditherControl */ 228 0U, /* ditherControlValue */ 229 0U, /* Monitor type */ 230 { /* Dividers */ 231 0U, 232 0U, 233 0U, 234 }, 235 0U, /* SoftwareDisable */ 236 }, 237 #endif 238 239 #if CLOCK_IP_CONFIGURED_PLLS_0_NO > 4U 240 { 241 LFAST1_PLL_CLK, /* name */ 242 1U, /* enable */ 243 P1_LFAST1_REF_CLK, /* inputReference */ 244 0U, /* Bypass */ 245 1U, /* predivider */ 246 0U, /* multiplier */ 247 0U, /* postdivider */ 248 0U, /* numeratorFracLoopDiv */ 249 20U, /* mulFactorDiv */ 250 0U, /* ModulationBypass */ 251 0U, /* Modulation type: Spread spectrum modulation bypassed */ 252 0U, /* modulationPeriod */ 253 0U, /* incrementStep */ 254 0U, /* sigmaDelta */ 255 0U, /* ditherControl */ 256 0U, /* ditherControlValue */ 257 0U, /* Monitor type */ 258 { /* Dividers */ 259 0U, 260 0U, 261 0U, 262 }, 263 0U, /* SoftwareDisable */ 264 }, 265 #endif 266 }; 267 268 static const Clock_Ip_SelectorConfigType Clock_Ip_SelectorConfigurations_0[CLOCK_IP_CONFIGURED_SELECTORS_0_NO] = { 269 270 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 0U 271 { 272 P0_SYS_CLK, /* Clock name associated to selector */ 273 COREPLL_DFS1_CLK, /* Name of the selected input source */ 274 }, 275 #endif 276 277 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 1U 278 { 279 P0_REG_INTF_CLK, /* Clock name associated to selector */ 280 COREPLL_DFS4_CLK, /* Name of the selected input source */ 281 }, 282 #endif 283 284 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 2U 285 { 286 P0_PSI5_1US_CLK, /* Clock name associated to selector */ 287 FIRC_CLK, /* Name of the selected input source */ 288 }, 289 #endif 290 291 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 3U 292 { 293 P0_PSI5_S_TRIG0_CLK, /* Clock name associated to selector */ 294 FIRC_CLK, /* Name of the selected input source */ 295 }, 296 #endif 297 298 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 4U 299 { 300 P0_LIN_BAUD_CLK, /* Clock name associated to selector */ 301 FIRC_CLK, /* Name of the selected input source */ 302 }, 303 #endif 304 305 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 5U 306 { 307 P0_DSPI_CLK, /* Clock name associated to selector */ 308 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */ 309 }, 310 #endif 311 312 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 6U 313 { 314 P0_FR_PE_CLK, /* Clock name associated to selector */ 315 FIRC_CLK, /* Name of the selected input source */ 316 }, 317 #endif 318 319 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 7U 320 { 321 P0_NANO_CLK, /* Clock name associated to selector */ 322 PERIPHPLL_PHI0_CLK, /* Name of the selected input source */ 323 }, 324 #endif 325 326 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 8U 327 { 328 GLB_LBIST_CLK, /* Clock name associated to selector */ 329 COREPLL_DFS5_CLK, /* Name of the selected input source */ 330 }, 331 #endif 332 333 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 9U 334 { 335 P0_EMIOS_LCU_CLK, /* Clock name associated to selector */ 336 FIRC_CLK, /* Name of the selected input source */ 337 }, 338 #endif 339 340 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 10U 341 { 342 CLKOUT0_CLK, /* Clock name associated to selector */ 343 FIRC_CLK, /* Name of the selected input source */ 344 }, 345 #endif 346 347 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 11U 348 { 349 P1_SYS_CLK, /* Clock name associated to selector */ 350 COREPLL_DFS1_CLK, /* Name of the selected input source */ 351 }, 352 #endif 353 354 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 12U 355 { 356 P1_REG_INTF_CLK, /* Clock name associated to selector */ 357 COREPLL_DFS4_CLK, /* Name of the selected input source */ 358 }, 359 #endif 360 361 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 13U 362 { 363 P1_DSPI_CLK, /* Clock name associated to selector */ 364 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */ 365 }, 366 #endif 367 368 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 14U 369 { 370 P1_DSPI60_CLK, /* Clock name associated to selector */ 371 PERIPHPLL_PHI2_CLK, /* Name of the selected input source */ 372 }, 373 #endif 374 375 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 15U 376 { 377 P1_LIN_BAUD_CLK, /* Clock name associated to selector */ 378 FIRC_CLK, /* Name of the selected input source */ 379 }, 380 #endif 381 382 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 16U 383 { 384 ETH_TS_CLK, /* Clock name associated to selector */ 385 FIRC_CLK, /* Name of the selected input source */ 386 }, 387 #endif 388 389 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 17U 390 { 391 ETH0_TX_MII_CLK, /* Clock name associated to selector */ 392 COREPLL_DFS3_CLK, /* Name of the selected input source */ 393 }, 394 #endif 395 396 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 18U 397 { 398 ETH0_RX_MII_CLK, /* Clock name associated to selector */ 399 ETH0_EXT_RX_CLK, /* Name of the selected input source */ 400 }, 401 #endif 402 403 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 19U 404 { 405 ETH1_TX_MII_CLK, /* Clock name associated to selector */ 406 COREPLL_DFS3_CLK, /* Name of the selected input source */ 407 }, 408 #endif 409 410 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 20U 411 { 412 ETH1_RX_MII_CLK, /* Clock name associated to selector */ 413 COREPLL_DFS3_CLK, /* Name of the selected input source */ 414 }, 415 #endif 416 417 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 21U 418 { 419 CLKOUT1_CLK, /* Clock name associated to selector */ 420 FIRC_CLK, /* Name of the selected input source */ 421 }, 422 #endif 423 424 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 22U 425 { 426 P1_LFAST0_REF_CLK, /* Clock name associated to selector */ 427 FXOSC_CLK, /* Name of the selected input source */ 428 }, 429 #endif 430 431 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 23U 432 { 433 P1_LFAST1_REF_CLK, /* Clock name associated to selector */ 434 FXOSC_CLK, /* Name of the selected input source */ 435 }, 436 #endif 437 438 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 24U 439 { 440 P1_NETC_AXI_CLK, /* Clock name associated to selector */ 441 PERIPHPLL_DFS5_CLK, /* Name of the selected input source */ 442 }, 443 #endif 444 445 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 25U 446 { 447 P2_SYS_CLK, /* Clock name associated to selector */ 448 COREPLL_DFS4_CLK, /* Name of the selected input source */ 449 }, 450 #endif 451 452 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 26U 453 { 454 P2_REG_INTF_CLK, /* Clock name associated to selector */ 455 FIRC_CLK, /* Name of the selected input source */ 456 }, 457 #endif 458 459 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 27U 460 { 461 P2_DBG_ATB_CLK, /* Clock name associated to selector */ 462 FIRC_CLK, /* Name of the selected input source */ 463 }, 464 #endif 465 466 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 28U 467 { 468 P2_MATH_CLK, /* Clock name associated to selector */ 469 COREPLL_DFS2_CLK, /* Name of the selected input source */ 470 }, 471 #endif 472 473 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 29U 474 { 475 P3_SYS_CLK, /* Clock name associated to selector */ 476 COREPLL_DFS1_CLK, /* Name of the selected input source */ 477 }, 478 #endif 479 480 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 30U 481 { 482 P3_REG_INTF_CLK, /* Clock name associated to selector */ 483 FIRC_CLK, /* Name of the selected input source */ 484 }, 485 #endif 486 487 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 31U 488 { 489 P3_DBG_TS_CLK, /* Clock name associated to selector */ 490 FIRC_CLK, /* Name of the selected input source */ 491 }, 492 #endif 493 494 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 32U 495 { 496 P3_CAN_PE_CLK, /* Clock name associated to selector */ 497 PERIPHPLL_PHI5_CLK, /* Name of the selected input source */ 498 }, 499 #endif 500 501 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 33U 502 { 503 CLKOUT4_CLK, /* Clock name associated to selector */ 504 FIRC_CLK, /* Name of the selected input source */ 505 }, 506 #endif 507 508 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 34U 509 { 510 P4_SYS_CLK, /* Clock name associated to selector */ 511 COREPLL_DFS4_CLK, /* Name of the selected input source */ 512 }, 513 #endif 514 515 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 35U 516 { 517 P4_REG_INTF_CLK, /* Clock name associated to selector */ 518 COREPLL_DFS1_CLK, /* Name of the selected input source */ 519 }, 520 #endif 521 522 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 36U 523 { 524 P4_PSI5_1US_CLK, /* Clock name associated to selector */ 525 FIRC_CLK, /* Name of the selected input source */ 526 }, 527 #endif 528 529 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 37U 530 { 531 P4_PSI5_S_TRIG0_CLK, /* Clock name associated to selector */ 532 FIRC_CLK, /* Name of the selected input source */ 533 }, 534 #endif 535 536 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 38U 537 { 538 P4_DSPI_CLK, /* Clock name associated to selector */ 539 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */ 540 }, 541 #endif 542 543 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 39U 544 { 545 P4_DSPI60_CLK, /* Clock name associated to selector */ 546 PERIPHPLL_PHI2_CLK, /* Name of the selected input source */ 547 }, 548 #endif 549 550 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 40U 551 { 552 CLKOUT2_CLK, /* Clock name associated to selector */ 553 FIRC_CLK, /* Name of the selected input source */ 554 }, 555 #endif 556 557 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 41U 558 { 559 P4_QSPI0_2X_CLK, /* Clock name associated to selector */ 560 FIRC_CLK, /* Name of the selected input source */ 561 }, 562 #endif 563 564 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 42U 565 { 566 P4_LIN_BAUD_CLK, /* Clock name associated to selector */ 567 FIRC_CLK, /* Name of the selected input source */ 568 }, 569 #endif 570 571 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 43U 572 { 573 P4_SDHC_CLK, /* Clock name associated to selector */ 574 FIRC_CLK, /* Name of the selected input source */ 575 }, 576 #endif 577 578 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 44U 579 { 580 P4_SDHC_IP_CLK, /* Clock name associated to selector */ 581 FIRC_CLK, /* Name of the selected input source */ 582 }, 583 #endif 584 585 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 45U 586 { 587 P4_EMIOS_LCU_CLK, /* Clock name associated to selector */ 588 FIRC_CLK, /* Name of the selected input source */ 589 }, 590 #endif 591 592 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 46U 593 { 594 P5_SYS_CLK, /* Clock name associated to selector */ 595 COREPLL_DFS4_CLK, /* Name of the selected input source */ 596 }, 597 #endif 598 599 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 47U 600 { 601 P5_REG_INTF_CLK, /* Clock name associated to selector */ 602 FIRC_CLK, /* Name of the selected input source */ 603 }, 604 #endif 605 606 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 48U 607 { 608 P5_LIN_BAUD_CLK, /* Clock name associated to selector */ 609 FIRC_CLK, /* Name of the selected input source */ 610 }, 611 #endif 612 613 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 49U 614 { 615 P5_DSPI_CLK, /* Clock name associated to selector */ 616 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */ 617 }, 618 #endif 619 620 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 50U 621 { 622 CLKOUT3_CLK, /* Clock name associated to selector */ 623 FIRC_CLK, /* Name of the selected input source */ 624 }, 625 #endif 626 627 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 51U 628 { 629 P5_DIPORT_CLK, /* Clock name associated to selector */ 630 PERIPHPLL_DFS1_CLK, /* Name of the selected input source */ 631 }, 632 #endif 633 634 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 52U 635 { 636 DDR_CLK, /* Clock name associated to selector */ 637 DDRPLL_PHI0_CLK, /* Name of the selected input source */ 638 }, 639 #endif 640 641 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 53U 642 { 643 P6_REG_INTF_CLK, /* Clock name associated to selector */ 644 FIRC_CLK, /* Name of the selected input source */ 645 }, 646 #endif 647 648 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 54U 649 { 650 RTU0_CORE_CLK, /* Clock name associated to selector */ 651 COREPLL_DFS0_CLK, /* Name of the selected input source */ 652 }, 653 #endif 654 655 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 55U 656 { 657 RTU0_REG_INTF_CLK, /* Clock name associated to selector */ 658 COREPLL_DFS1_CLK, /* Name of the selected input source */ 659 }, 660 #endif 661 662 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 56U 663 { 664 RTU1_CORE_CLK, /* Clock name associated to selector */ 665 COREPLL_DFS0_CLK, /* Name of the selected input source */ 666 }, 667 #endif 668 669 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 57U 670 { 671 RTU1_REG_INTF_CLK, /* Clock name associated to selector */ 672 COREPLL_DFS1_CLK, /* Name of the selected input source */ 673 }, 674 #endif 675 676 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 58U 677 { 678 P0_CLKOUT_SRC_CLK, /* Clock name associated to selector */ 679 FIRC_CLK, /* Name of the selected input source */ 680 }, 681 #endif 682 683 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 59U 684 { 685 P1_CLKOUT_SRC_CLK, /* Clock name associated to selector */ 686 P1_SYS_CLK, /* Name of the selected input source */ 687 }, 688 #endif 689 690 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 60U 691 { 692 P3_CLKOUT_SRC_CLK, /* Clock name associated to selector */ 693 P3_SYS_CLK, /* Name of the selected input source */ 694 }, 695 #endif 696 697 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 61U 698 { 699 P4_CLKOUT_SRC_CLK, /* Clock name associated to selector */ 700 P4_SYS_CLK, /* Name of the selected input source */ 701 }, 702 #endif 703 704 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 62U 705 { 706 P5_CLKOUT_SRC_CLK, /* Clock name associated to selector */ 707 P5_SYS_CLK, /* Name of the selected input source */ 708 }, 709 #endif 710 }; 711 712 713 static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_IP_CONFIGURED_DIVIDERS_0_NO] = { 714 715 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 0U 716 { 717 CLKOUT0_CLK, /* name */ 718 2U, /* value */ 719 { 720 0U, 721 } 722 }, 723 #endif 724 725 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 1U 726 { 727 CLKOUT1_CLK, /* name */ 728 2U, /* value */ 729 { 730 0U, 731 } 732 }, 733 #endif 734 735 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 2U 736 { 737 COREPLL_PHI0_CLK, /* name */ 738 3U, /* value */ 739 { 740 0U, 741 } 742 }, 743 #endif 744 745 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 3U 746 { 747 DDR_CLK, /* name */ 748 2U, /* value */ 749 { 750 0U, 751 } 752 }, 753 #endif 754 755 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 4U 756 { 757 DDRPLL_PHI0_CLK, /* name */ 758 4U, /* value */ 759 { 760 0U, 761 } 762 }, 763 #endif 764 765 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 5U 766 { 767 ETH_TS_CLK, /* name */ 768 1U, /* value */ 769 { 770 0U, 771 } 772 }, 773 #endif 774 775 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 6U 776 { 777 ETH0_REF_RMII_CLK, /* name */ 778 5U, /* value */ 779 { 780 0U, 781 } 782 }, 783 #endif 784 785 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 7U 786 { 787 ETH0_RX_MII_CLK, /* name */ 788 5U, /* value */ 789 { 790 0U, 791 } 792 }, 793 #endif 794 795 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 8U 796 { 797 ETH0_RX_RGMII_CLK, /* name */ 798 1U, /* value */ 799 { 800 0U, 801 } 802 }, 803 #endif 804 805 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 9U 806 { 807 ETH0_TX_MII_CLK, /* name */ 808 20U, /* value */ 809 { 810 0U, 811 } 812 }, 813 #endif 814 815 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 10U 816 { 817 ETH0_TX_RGMII_CLK, /* name */ 818 4U, /* value */ 819 { 820 0U, 821 } 822 }, 823 #endif 824 825 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 11U 826 { 827 ETH1_REF_RMII_CLK, /* name */ 828 10U, /* value */ 829 { 830 0U, 831 } 832 }, 833 #endif 834 835 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 12U 836 { 837 ETH1_RX_MII_CLK, /* name */ 838 20U, /* value */ 839 { 840 0U, 841 } 842 }, 843 #endif 844 845 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 13U 846 { 847 ETH1_RX_RGMII_CLK, /* name */ 848 10U, /* value */ 849 { 850 0U, 851 } 852 }, 853 #endif 854 855 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 14U 856 { 857 ETH1_TX_MII_CLK, /* name */ 858 20U, /* value */ 859 { 860 0U, 861 } 862 }, 863 #endif 864 865 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 15U 866 { 867 ETH1_TX_RGMII_CLK, /* name */ 868 4U, /* value */ 869 { 870 0U, 871 } 872 }, 873 #endif 874 875 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 16U 876 { 877 GLB_LBIST_CLK, /* name */ 878 1U, /* value */ 879 { 880 0U, 881 } 882 }, 883 #endif 884 885 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 17U 886 { 887 P0_CTU_PER_CLK, /* name */ 888 1U, /* value */ 889 { 890 0U, 891 } 892 }, 893 #endif 894 895 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 18U 896 { 897 P0_DSPI_MSC_CLK, /* name */ 898 10U, /* value */ 899 { 900 0U, 901 } 902 }, 903 #endif 904 905 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 19U 906 { 907 P0_FR_PE_CLK, /* name */ 908 1U, /* value */ 909 { 910 0U, 911 } 912 }, 913 #endif 914 915 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 20U 916 { 917 P0_GTM_CLK, /* name */ 918 3U, /* value */ 919 { 920 0U, 921 } 922 }, 923 #endif 924 925 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 21U 926 { 927 P0_LIN_BAUD_CLK, /* name */ 928 1U, /* value */ 929 { 930 0U, 931 } 932 }, 933 #endif 934 935 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 22U 936 { 937 P0_PSI5_125K_CLK, /* name */ 938 12U, /* value */ 939 { 940 0U, 941 } 942 }, 943 #endif 944 945 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 23U 946 { 947 P0_PSI5_189K_CLK, /* name */ 948 3306U, /* value */ 949 { 950 2U, 951 } 952 }, 953 #endif 954 955 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 24U 956 { 957 P0_PSI5_1US_CLK, /* name */ 958 48U, /* value */ 959 { 960 0U, 961 } 962 }, 963 #endif 964 965 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 25U 966 { 967 P0_PSI5_S_BAUD_CLK, /* name */ 968 1U, /* value */ 969 { 970 0U, 971 } 972 }, 973 #endif 974 975 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 26U 976 { 977 P0_PSI5_S_TRIG0_CLK, /* name */ 978 513U, /* value */ 979 { 980 0U, 981 } 982 }, 983 #endif 984 985 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 27U 986 { 987 P0_PSI5_S_TRIG1_CLK, /* name */ 988 513U, /* value */ 989 { 990 0U, 991 } 992 }, 993 #endif 994 995 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 28U 996 { 997 P0_PSI5_S_TRIG2_CLK, /* name */ 998 513U, /* value */ 999 { 1000 0U, 1001 } 1002 }, 1003 #endif 1004 1005 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 29U 1006 { 1007 P0_PSI5_S_TRIG3_CLK, /* name */ 1008 513U, /* value */ 1009 { 1010 0U, 1011 } 1012 }, 1013 #endif 1014 1015 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 30U 1016 { 1017 P0_PSI5_S_UART_CLK, /* name */ 1018 1U, /* value */ 1019 { 1020 0U, 1021 } 1022 }, 1023 #endif 1024 1025 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 31U 1026 { 1027 P0_PSI5_S_UTIL_CLK, /* name */ 1028 48U, /* value */ 1029 { 1030 0U, 1031 } 1032 }, 1033 #endif 1034 1035 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 32U 1036 { 1037 P0_PSI5_S_WDOG0_CLK, /* name */ 1038 513U, /* value */ 1039 { 1040 0U, 1041 } 1042 }, 1043 #endif 1044 1045 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 33U 1046 { 1047 P0_PSI5_S_WDOG1_CLK, /* name */ 1048 513U, /* value */ 1049 { 1050 0U, 1051 } 1052 }, 1053 #endif 1054 1055 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 34U 1056 { 1057 P0_PSI5_S_WDOG2_CLK, /* name */ 1058 513U, /* value */ 1059 { 1060 0U, 1061 } 1062 }, 1063 #endif 1064 1065 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 35U 1066 { 1067 P0_PSI5_S_WDOG3_CLK, /* name */ 1068 513U, /* value */ 1069 { 1070 0U, 1071 } 1072 }, 1073 #endif 1074 1075 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 36U 1076 { 1077 P1_LFAST0_REF_CLK, /* name */ 1078 2U, /* value */ 1079 { 1080 0U, 1081 } 1082 }, 1083 #endif 1084 1085 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 37U 1086 { 1087 P1_LFAST1_REF_CLK, /* name */ 1088 2U, /* value */ 1089 { 1090 0U, 1091 } 1092 }, 1093 #endif 1094 1095 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 38U 1096 { 1097 P1_LIN_BAUD_CLK, /* name */ 1098 1U, /* value */ 1099 { 1100 0U, 1101 } 1102 }, 1103 #endif 1104 1105 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 39U 1106 { 1107 P1_NETC_AXI_CLK, /* name */ 1108 1U, /* value */ 1109 { 1110 0U, 1111 } 1112 }, 1113 #endif 1114 1115 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 40U 1116 { 1117 P1_REG_INTF_CLK, /* name */ 1118 3U, /* value */ 1119 { 1120 0U, 1121 } 1122 }, 1123 #endif 1124 1125 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 41U 1126 { 1127 P2_REG_INTF_CLK, /* name */ 1128 3U, /* value */ 1129 { 1130 0U, 1131 } 1132 }, 1133 #endif 1134 1135 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 42U 1136 { 1137 P3_AES_CLK, /* name */ 1138 200U, /* value */ 1139 { 1140 0U, 1141 } 1142 }, 1143 #endif 1144 1145 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 43U 1146 { 1147 P3_CAN_PE_CLK, /* name */ 1148 2U, /* value */ 1149 { 1150 0U, 1151 } 1152 }, 1153 #endif 1154 1155 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 44U 1156 { 1157 CLKOUT4_CLK, /* name */ 1158 1U, /* value */ 1159 { 1160 0U, 1161 } 1162 }, 1163 #endif 1164 1165 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 45U 1166 { 1167 P3_DBG_TS_CLK, /* name */ 1168 1U, /* value */ 1169 { 1170 0U, 1171 } 1172 }, 1173 #endif 1174 1175 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 46U 1176 { 1177 P3_REG_INTF_CLK, /* name */ 1178 1U, /* value */ 1179 { 1180 0U, 1181 } 1182 }, 1183 #endif 1184 1185 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 47U 1186 { 1187 CLKOUT2_CLK, /* name */ 1188 2U, /* value */ 1189 { 1190 0U, 1191 } 1192 }, 1193 #endif 1194 1195 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 48U 1196 { 1197 P4_LIN_BAUD_CLK, /* name */ 1198 1U, /* value */ 1199 { 1200 0U, 1201 } 1202 }, 1203 #endif 1204 1205 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 49U 1206 { 1207 P4_PSI5_125K_CLK, /* name */ 1208 12U, /* value */ 1209 { 1210 0U, 1211 } 1212 }, 1213 #endif 1214 1215 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 50U 1216 { 1217 P4_PSI5_189K_CLK, /* name */ 1218 3306U, /* value */ 1219 { 1220 2U, 1221 } 1222 }, 1223 #endif 1224 1225 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 51U 1226 { 1227 P4_PSI5_1US_CLK, /* name */ 1228 48U, /* value */ 1229 { 1230 0U, 1231 } 1232 }, 1233 #endif 1234 1235 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 52U 1236 { 1237 P4_PSI5_S_BAUD_CLK, /* name */ 1238 1U, /* value */ 1239 { 1240 0U, 1241 } 1242 }, 1243 #endif 1244 1245 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 53U 1246 { 1247 P4_PSI5_S_TRIG0_CLK, /* name */ 1248 48U, /* value */ 1249 { 1250 0U, 1251 } 1252 }, 1253 #endif 1254 1255 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 54U 1256 { 1257 P4_PSI5_S_TRIG1_CLK, /* name */ 1258 48U, /* value */ 1259 { 1260 0U, 1261 } 1262 }, 1263 #endif 1264 1265 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 55U 1266 { 1267 P4_PSI5_S_TRIG2_CLK, /* name */ 1268 48U, /* value */ 1269 { 1270 0U, 1271 } 1272 }, 1273 #endif 1274 1275 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 56U 1276 { 1277 P4_PSI5_S_TRIG3_CLK, /* name */ 1278 48U, /* value */ 1279 { 1280 0U, 1281 } 1282 }, 1283 #endif 1284 1285 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 57U 1286 { 1287 P4_PSI5_S_UART_CLK, /* name */ 1288 1U, /* value */ 1289 { 1290 0U, 1291 } 1292 }, 1293 #endif 1294 1295 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 58U 1296 { 1297 P4_PSI5_S_UTIL_CLK, /* name */ 1298 48U, /* value */ 1299 { 1300 0U, 1301 } 1302 }, 1303 #endif 1304 1305 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 59U 1306 { 1307 P4_PSI5_S_WDOG0_CLK, /* name */ 1308 481U, /* value */ 1309 { 1310 0U, 1311 } 1312 }, 1313 #endif 1314 1315 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 60U 1316 { 1317 P4_PSI5_S_WDOG1_CLK, /* name */ 1318 48U, /* value */ 1319 { 1320 0U, 1321 } 1322 }, 1323 #endif 1324 1325 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 61U 1326 { 1327 P4_PSI5_S_WDOG2_CLK, /* name */ 1328 48U, /* value */ 1329 { 1330 0U, 1331 } 1332 }, 1333 #endif 1334 1335 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 62U 1336 { 1337 P4_PSI5_S_WDOG3_CLK, /* name */ 1338 48U, /* value */ 1339 { 1340 0U, 1341 } 1342 }, 1343 #endif 1344 1345 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 63U 1346 { 1347 P4_QSPI0_2X_CLK, /* name */ 1348 1U, /* value */ 1349 { 1350 0U, 1351 } 1352 }, 1353 #endif 1354 1355 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 64U 1356 { 1357 P4_QSPI1_2X_CLK, /* name */ 1358 2U, /* value */ 1359 { 1360 0U, 1361 } 1362 }, 1363 #endif 1364 1365 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 65U 1366 { 1367 P5_AE_CLK, /* name */ 1368 6U, /* value */ 1369 { 1370 0U, 1371 } 1372 }, 1373 #endif 1374 1375 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 66U 1376 { 1377 P5_CANXL_PE_CLK, /* name */ 1378 10U, /* value */ 1379 { 1380 0U, 1381 } 1382 }, 1383 #endif 1384 1385 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 67U 1386 { 1387 P5_CANXL_CHI_CLK, /* name */ 1388 5U, /* value */ 1389 { 1390 0U, 1391 } 1392 }, 1393 #endif 1394 1395 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 68U 1396 { 1397 CLKOUT3_CLK, /* name */ 1398 2U, /* value */ 1399 { 1400 0U, 1401 } 1402 }, 1403 #endif 1404 1405 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 69U 1406 { 1407 P5_LIN_BAUD_CLK, /* name */ 1408 1U, /* value */ 1409 { 1410 0U, 1411 } 1412 }, 1413 #endif 1414 1415 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 70U 1416 { 1417 P5_REG_INTF_CLK, /* name */ 1418 1U, /* value */ 1419 { 1420 0U, 1421 } 1422 }, 1423 #endif 1424 1425 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 71U 1426 { 1427 P5_SYS_CLK, /* name */ 1428 2U, /* value */ 1429 { 1430 0U, 1431 } 1432 }, 1433 #endif 1434 1435 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 72U 1436 { 1437 P6_REG_INTF_CLK, /* name */ 1438 1U, /* value */ 1439 { 1440 0U, 1441 } 1442 }, 1443 #endif 1444 1445 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 73U 1446 { 1447 PERIPHPLL_PHI0_CLK, /* name */ 1448 2U, /* value */ 1449 { 1450 0U, 1451 } 1452 }, 1453 #endif 1454 1455 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 74U 1456 { 1457 PERIPHPLL_PHI1_CLK, /* name */ 1458 24U, /* value */ 1459 { 1460 0U, 1461 } 1462 }, 1463 #endif 1464 1465 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 75U 1466 { 1467 PERIPHPLL_PHI2_CLK, /* name */ 1468 20U, /* value */ 1469 { 1470 0U, 1471 } 1472 }, 1473 #endif 1474 1475 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 76U 1476 { 1477 PERIPHPLL_PHI3_CLK, /* name */ 1478 9U, /* value */ 1479 { 1480 0U, 1481 } 1482 }, 1483 #endif 1484 1485 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 77U 1486 { 1487 PERIPHPLL_PHI4_CLK, /* name */ 1488 12U, /* value */ 1489 { 1490 0U, 1491 } 1492 }, 1493 #endif 1494 1495 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 78U 1496 { 1497 PERIPHPLL_PHI5_CLK, /* name */ 1498 15U, /* value */ 1499 { 1500 0U, 1501 } 1502 }, 1503 #endif 1504 1505 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 79U 1506 { 1507 PERIPHPLL_PHI6_CLK, /* name */ 1508 3U, /* value */ 1509 { 1510 0U, 1511 } 1512 }, 1513 #endif 1514 1515 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 80U 1516 { 1517 RTU0_CORE_CLK, /* name */ 1518 1U, /* value */ 1519 { 1520 0U, 1521 } 1522 }, 1523 #endif 1524 1525 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 81U 1526 { 1527 RTU0_REG_INTF_CLK, /* name */ 1528 3U, /* value */ 1529 { 1530 0U, 1531 } 1532 }, 1533 #endif 1534 1535 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 82U 1536 { 1537 RTU1_CORE_CLK, /* name */ 1538 1U, /* value */ 1539 { 1540 0U, 1541 } 1542 }, 1543 #endif 1544 1545 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 83U 1546 { 1547 RTU1_REG_INTF_CLK, /* name */ 1548 3U, /* value */ 1549 { 1550 0U, 1551 } 1552 }, 1553 #endif 1554 1555 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 84U 1556 { 1557 P4_SDHC_CLK, /* name */ 1558 1U, /* value */ 1559 { 1560 0U, 1561 } 1562 }, 1563 #endif 1564 }; 1565 1566 1567 static const Clock_Ip_DividerTriggerConfigType Clock_Ip_DividerTriggerConfigurations_0[CLOCK_IP_CONFIGURED_DIVIDER_TRIGGERS_0_NO] = { 1568 1569 #if CLOCK_IP_CONFIGURED_DIVIDER_TRIGGERS_0_NO > 0U 1570 { 1571 P0_GTM_CLK, /* divider name */ 1572 IMMEDIATE_DIVIDER_UPDATE, /* trigger value */ 1573 P0_GTM_CLK, /* input source name */ 1574 }, 1575 #endif 1576 }; 1577 1578 1579 static const Clock_Ip_FracDivConfigType Clock_Ip_FracDivsConfigurations_0[CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO] = { 1580 1581 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 0U 1582 { 1583 COREPLL_DFS0_CLK, /* name */ 1584 1U, /* Enabled */ 1585 { 1586 1U, /* integer part */ 1587 0U, /* fractional part */ 1588 }, 1589 }, 1590 #endif 1591 1592 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 1U 1593 { 1594 COREPLL_DFS1_CLK, /* name */ 1595 1U, /* Enabled */ 1596 { 1597 2U, /* integer part */ 1598 18U, /* fractional part */ 1599 }, 1600 }, 1601 #endif 1602 1603 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 2U 1604 { 1605 COREPLL_DFS2_CLK, /* name */ 1606 1U, /* Enabled */ 1607 { 1608 2U, /* integer part */ 1609 18U, /* fractional part */ 1610 }, 1611 }, 1612 #endif 1613 1614 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 3U 1615 { 1616 COREPLL_DFS3_CLK, /* name */ 1617 1U, /* Enabled */ 1618 { 1619 2U, /* integer part */ 1620 0U, /* fractional part */ 1621 }, 1622 }, 1623 #endif 1624 1625 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 4U 1626 { 1627 COREPLL_DFS4_CLK, /* name */ 1628 1U, /* Enabled */ 1629 { 1630 2U, /* integer part */ 1631 18U, /* fractional part */ 1632 }, 1633 }, 1634 #endif 1635 1636 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 5U 1637 { 1638 COREPLL_DFS5_CLK, /* name */ 1639 1U, /* Enabled */ 1640 { 1641 2U, /* integer part */ 1642 18U, /* fractional part */ 1643 }, 1644 }, 1645 #endif 1646 1647 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 6U 1648 { 1649 PERIPHPLL_DFS0_CLK, /* name */ 1650 1U, /* Enabled */ 1651 { 1652 1U, /* integer part */ 1653 18U, /* fractional part */ 1654 }, 1655 }, 1656 #endif 1657 1658 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 7U 1659 { 1660 PERIPHPLL_DFS1_CLK, /* name */ 1661 1U, /* Enabled */ 1662 { 1663 1U, /* integer part */ 1664 18U, /* fractional part */ 1665 }, 1666 }, 1667 #endif 1668 1669 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 8U 1670 { 1671 PERIPHPLL_DFS2_CLK, /* name */ 1672 1U, /* Enabled */ 1673 { 1674 2U, /* integer part */ 1675 18U, /* fractional part */ 1676 }, 1677 }, 1678 #endif 1679 1680 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 9U 1681 { 1682 PERIPHPLL_DFS3_CLK, /* name */ 1683 1U, /* Enabled */ 1684 { 1685 2U, /* integer part */ 1686 14U, /* fractional part */ 1687 }, 1688 }, 1689 #endif 1690 1691 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 10U 1692 { 1693 PERIPHPLL_DFS4_CLK, /* name */ 1694 1U, /* Enabled */ 1695 { 1696 2U, /* integer part */ 1697 14U, /* fractional part */ 1698 }, 1699 }, 1700 #endif 1701 1702 #if CLOCK_IP_CONFIGURED_FRACTIONAL_DIVIDERS_0_NO > 11U 1703 { 1704 PERIPHPLL_DFS5_CLK, /* name */ 1705 1U, /* Enabled */ 1706 { 1707 4U, /* integer part */ 1708 0U, /* fractional part */ 1709 }, 1710 }, 1711 #endif 1712 }; 1713 1714 1715 static const Clock_Ip_ExtClkConfigType Clock_Ip_ExtClkConfigurations_0[CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO] = { 1716 1717 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 0U 1718 { 1719 ETH_RGMII_REF_CLK, /* name */ 1720 50000000U, /* value */ 1721 }, 1722 #endif 1723 1724 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 1U 1725 { 1726 TMR_1588_CLK, /* name */ 1727 0U, /* value */ 1728 }, 1729 #endif 1730 1731 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 2U 1732 { 1733 ETH0_EXT_RX_CLK, /* name */ 1734 125000000U, /* value */ 1735 }, 1736 #endif 1737 1738 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 3U 1739 { 1740 ETH0_EXT_TX_CLK, /* name */ 1741 50000000U, /* value */ 1742 }, 1743 #endif 1744 1745 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 4U 1746 { 1747 ETH1_EXT_RX_CLK, /* name */ 1748 125000000U, /* value */ 1749 }, 1750 #endif 1751 1752 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 5U 1753 { 1754 ETH1_EXT_TX_CLK, /* name */ 1755 50000000U, /* value */ 1756 }, 1757 #endif 1758 1759 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 6U 1760 { 1761 LFAST0_EXT_REF_CLK, /* name */ 1762 20000000U, /* value */ 1763 }, 1764 #endif 1765 1766 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 7U 1767 { 1768 LFAST1_EXT_REF_CLK, /* name */ 1769 20000000U, /* value */ 1770 }, 1771 #endif 1772 }; 1773 1774 1775 static const Clock_Ip_GateConfigType Clock_Ip_GatesConfigurations_0[CLOCK_IP_CONFIGURED_GATES_0_NO] = { 1776 1777 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 0U 1778 { 1779 DDR_CLK, /* name */ 1780 1U, /* enable */ 1781 }, 1782 #endif 1783 1784 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 1U 1785 { 1786 ADC0_CLK, /* name */ 1787 1U, /* enable */ 1788 }, 1789 #endif 1790 1791 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 2U 1792 { 1793 ADC1_CLK, /* name */ 1794 1U, /* enable */ 1795 }, 1796 #endif 1797 1798 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 3U 1799 { 1800 CE_EDMA_CLK, /* name */ 1801 1U, /* enable */ 1802 }, 1803 #endif 1804 1805 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 4U 1806 { 1807 CE_PIT0_CLK, /* name */ 1808 1U, /* enable */ 1809 }, 1810 #endif 1811 1812 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 5U 1813 { 1814 CE_PIT1_CLK, /* name */ 1815 1U, /* enable */ 1816 }, 1817 #endif 1818 1819 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 6U 1820 { 1821 CE_PIT2_CLK, /* name */ 1822 1U, /* enable */ 1823 }, 1824 #endif 1825 1826 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 7U 1827 { 1828 CE_PIT3_CLK, /* name */ 1829 1U, /* enable */ 1830 }, 1831 #endif 1832 1833 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 8U 1834 { 1835 CE_PIT4_CLK, /* name */ 1836 1U, /* enable */ 1837 }, 1838 #endif 1839 1840 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 9U 1841 { 1842 CE_PIT5_CLK, /* name */ 1843 1U, /* enable */ 1844 }, 1845 #endif 1846 1847 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 10U 1848 { 1849 CTU_CLK, /* name */ 1850 1U, /* enable */ 1851 }, 1852 #endif 1853 1854 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 11U 1855 { 1856 DMACRC0_CLK, /* name */ 1857 1U, /* enable */ 1858 }, 1859 #endif 1860 1861 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 12U 1862 { 1863 DMACRC1_CLK, /* name */ 1864 1U, /* enable */ 1865 }, 1866 #endif 1867 1868 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 13U 1869 { 1870 DMACRC4_CLK, /* name */ 1871 1U, /* enable */ 1872 }, 1873 #endif 1874 1875 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 14U 1876 { 1877 DMACRC5_CLK, /* name */ 1878 1U, /* enable */ 1879 }, 1880 #endif 1881 1882 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 15U 1883 { 1884 DMAMUX0_CLK, /* name */ 1885 1U, /* enable */ 1886 }, 1887 #endif 1888 1889 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 16U 1890 { 1891 DMAMUX1_CLK, /* name */ 1892 1U, /* enable */ 1893 }, 1894 #endif 1895 1896 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 17U 1897 { 1898 DMAMUX4_CLK, /* name */ 1899 1U, /* enable */ 1900 }, 1901 #endif 1902 1903 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 18U 1904 { 1905 DMAMUX5_CLK, /* name */ 1906 1U, /* enable */ 1907 }, 1908 #endif 1909 1910 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 19U 1911 { 1912 EDMA0_CLK, /* name */ 1913 1U, /* enable */ 1914 }, 1915 #endif 1916 1917 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 20U 1918 { 1919 EDMA1_CLK, /* name */ 1920 1U, /* enable */ 1921 }, 1922 #endif 1923 1924 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 21U 1925 { 1926 EDMA3_CLK, /* name */ 1927 1U, /* enable */ 1928 }, 1929 #endif 1930 1931 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 22U 1932 { 1933 EDMA4_CLK, /* name */ 1934 1U, /* enable */ 1935 }, 1936 #endif 1937 1938 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 23U 1939 { 1940 EDMA5_CLK, /* name */ 1941 1U, /* enable */ 1942 }, 1943 #endif 1944 1945 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 24U 1946 { 1947 ENET0_CLK, /* name */ 1948 1U, /* enable */ 1949 }, 1950 #endif 1951 1952 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 25U 1953 { 1954 FLEXCAN0_CLK, /* name */ 1955 1U, /* enable */ 1956 }, 1957 #endif 1958 1959 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 26U 1960 { 1961 FLEXCAN1_CLK, /* name */ 1962 1U, /* enable */ 1963 }, 1964 #endif 1965 1966 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 27U 1967 { 1968 FLEXCAN2_CLK, /* name */ 1969 1U, /* enable */ 1970 }, 1971 #endif 1972 1973 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 28U 1974 { 1975 FLEXCAN3_CLK, /* name */ 1976 1U, /* enable */ 1977 }, 1978 #endif 1979 1980 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 29U 1981 { 1982 FLEXCAN4_CLK, /* name */ 1983 1U, /* enable */ 1984 }, 1985 #endif 1986 1987 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 30U 1988 { 1989 FLEXCAN5_CLK, /* name */ 1990 1U, /* enable */ 1991 }, 1992 #endif 1993 1994 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 31U 1995 { 1996 FLEXCAN6_CLK, /* name */ 1997 1U, /* enable */ 1998 }, 1999 #endif 2000 2001 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 32U 2002 { 2003 FLEXCAN7_CLK, /* name */ 2004 1U, /* enable */ 2005 }, 2006 #endif 2007 2008 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 33U 2009 { 2010 FLEXCAN8_CLK, /* name */ 2011 1U, /* enable */ 2012 }, 2013 #endif 2014 2015 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 34U 2016 { 2017 FLEXCAN9_CLK, /* name */ 2018 1U, /* enable */ 2019 }, 2020 #endif 2021 2022 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 35U 2023 { 2024 FLEXCAN10_CLK, /* name */ 2025 1U, /* enable */ 2026 }, 2027 #endif 2028 2029 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 36U 2030 { 2031 FLEXCAN11_CLK, /* name */ 2032 1U, /* enable */ 2033 }, 2034 #endif 2035 2036 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 37U 2037 { 2038 FLEXCAN12_CLK, /* name */ 2039 1U, /* enable */ 2040 }, 2041 #endif 2042 2043 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 38U 2044 { 2045 FLEXCAN13_CLK, /* name */ 2046 1U, /* enable */ 2047 }, 2048 #endif 2049 2050 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 39U 2051 { 2052 FLEXCAN14_CLK, /* name */ 2053 1U, /* enable */ 2054 }, 2055 #endif 2056 2057 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 40U 2058 { 2059 FLEXCAN15_CLK, /* name */ 2060 1U, /* enable */ 2061 }, 2062 #endif 2063 2064 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 41U 2065 { 2066 FLEXCAN16_CLK, /* name */ 2067 1U, /* enable */ 2068 }, 2069 #endif 2070 2071 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 42U 2072 { 2073 FLEXCAN17_CLK, /* name */ 2074 1U, /* enable */ 2075 }, 2076 #endif 2077 2078 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 43U 2079 { 2080 FLEXCAN18_CLK, /* name */ 2081 1U, /* enable */ 2082 }, 2083 #endif 2084 2085 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 44U 2086 { 2087 FLEXCAN19_CLK, /* name */ 2088 1U, /* enable */ 2089 }, 2090 #endif 2091 2092 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 45U 2093 { 2094 FLEXCAN20_CLK, /* name */ 2095 1U, /* enable */ 2096 }, 2097 #endif 2098 2099 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 46U 2100 { 2101 FLEXCAN21_CLK, /* name */ 2102 1U, /* enable */ 2103 }, 2104 #endif 2105 2106 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 47U 2107 { 2108 FLEXCAN22_CLK, /* name */ 2109 1U, /* enable */ 2110 }, 2111 #endif 2112 2113 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 48U 2114 { 2115 FLEXCAN23_CLK, /* name */ 2116 1U, /* enable */ 2117 }, 2118 #endif 2119 2120 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 49U 2121 { 2122 FRAY0_CLK, /* name */ 2123 1U, /* enable */ 2124 }, 2125 #endif 2126 2127 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 50U 2128 { 2129 FRAY1_CLK, /* name */ 2130 1U, /* enable */ 2131 }, 2132 #endif 2133 2134 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 51U 2135 { 2136 GTM_CLK, /* name */ 2137 1U, /* enable */ 2138 }, 2139 #endif 2140 2141 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 52U 2142 { 2143 IIIC0_CLK, /* name */ 2144 1U, /* enable */ 2145 }, 2146 #endif 2147 2148 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 53U 2149 { 2150 IIIC1_CLK, /* name */ 2151 1U, /* enable */ 2152 }, 2153 #endif 2154 2155 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 54U 2156 { 2157 IIIC2_CLK, /* name */ 2158 1U, /* enable */ 2159 }, 2160 #endif 2161 2162 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 55U 2163 { 2164 LIN0_CLK, /* name */ 2165 1U, /* enable */ 2166 }, 2167 #endif 2168 2169 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 56U 2170 { 2171 LIN1_CLK, /* name */ 2172 1U, /* enable */ 2173 }, 2174 #endif 2175 2176 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 57U 2177 { 2178 LIN2_CLK, /* name */ 2179 1U, /* enable */ 2180 }, 2181 #endif 2182 2183 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 58U 2184 { 2185 LIN3_CLK, /* name */ 2186 1U, /* enable */ 2187 }, 2188 #endif 2189 2190 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 59U 2191 { 2192 LIN4_CLK, /* name */ 2193 1U, /* enable */ 2194 }, 2195 #endif 2196 2197 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 60U 2198 { 2199 LIN5_CLK, /* name */ 2200 1U, /* enable */ 2201 }, 2202 #endif 2203 2204 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 61U 2205 { 2206 LIN6_CLK, /* name */ 2207 1U, /* enable */ 2208 }, 2209 #endif 2210 2211 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 62U 2212 { 2213 LIN7_CLK, /* name */ 2214 1U, /* enable */ 2215 }, 2216 #endif 2217 2218 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 63U 2219 { 2220 LIN8_CLK, /* name */ 2221 1U, /* enable */ 2222 }, 2223 #endif 2224 2225 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 64U 2226 { 2227 LIN9_CLK, /* name */ 2228 1U, /* enable */ 2229 }, 2230 #endif 2231 2232 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 65U 2233 { 2234 LIN10_CLK, /* name */ 2235 1U, /* enable */ 2236 }, 2237 #endif 2238 2239 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 66U 2240 { 2241 LIN11_CLK, /* name */ 2242 1U, /* enable */ 2243 }, 2244 #endif 2245 2246 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 67U 2247 { 2248 MSCDSPI_CLK, /* name */ 2249 1U, /* enable */ 2250 }, 2251 #endif 2252 2253 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 68U 2254 { 2255 MSCLIN_CLK, /* name */ 2256 1U, /* enable */ 2257 }, 2258 #endif 2259 2260 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 69U 2261 { 2262 NANO_CLK, /* name */ 2263 1U, /* enable */ 2264 }, 2265 #endif 2266 2267 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 70U 2268 { 2269 PIT0_CLK, /* name */ 2270 1U, /* enable */ 2271 }, 2272 #endif 2273 2274 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 71U 2275 { 2276 PIT1_CLK, /* name */ 2277 1U, /* enable */ 2278 }, 2279 #endif 2280 2281 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 72U 2282 { 2283 PIT4_CLK, /* name */ 2284 1U, /* enable */ 2285 }, 2286 #endif 2287 2288 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 73U 2289 { 2290 PIT5_CLK, /* name */ 2291 1U, /* enable */ 2292 }, 2293 #endif 2294 2295 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 74U 2296 { 2297 PSI5_0_CLK, /* name */ 2298 1U, /* enable */ 2299 }, 2300 #endif 2301 2302 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 75U 2303 { 2304 PSI5_1_CLK, /* name */ 2305 1U, /* enable */ 2306 }, 2307 #endif 2308 2309 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 76U 2310 { 2311 PSI5S_0_CLK, /* name */ 2312 1U, /* enable */ 2313 }, 2314 #endif 2315 2316 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 77U 2317 { 2318 PSI5S_1_CLK, /* name */ 2319 1U, /* enable */ 2320 }, 2321 #endif 2322 2323 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 78U 2324 { 2325 QSPI0_CLK, /* name */ 2326 1U, /* enable */ 2327 }, 2328 #endif 2329 2330 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 79U 2331 { 2332 QSPI1_CLK, /* name */ 2333 1U, /* enable */ 2334 }, 2335 #endif 2336 2337 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 80U 2338 { 2339 RXLUT_CLK, /* name */ 2340 1U, /* enable */ 2341 }, 2342 #endif 2343 2344 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 81U 2345 { 2346 SDHC0_CLK, /* name */ 2347 1U, /* enable */ 2348 }, 2349 #endif 2350 2351 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 82U 2352 { 2353 SINC_CLK, /* name */ 2354 1U, /* enable */ 2355 }, 2356 #endif 2357 2358 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 83U 2359 { 2360 SIPI0_CLK, /* name */ 2361 1U, /* enable */ 2362 }, 2363 #endif 2364 2365 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 84U 2366 { 2367 SIPI1_CLK, /* name */ 2368 1U, /* enable */ 2369 }, 2370 #endif 2371 2372 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 85U 2373 { 2374 SIUL2_0_CLK, /* name */ 2375 1U, /* enable */ 2376 }, 2377 #endif 2378 2379 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 86U 2380 { 2381 SIUL2_1_CLK, /* name */ 2382 1U, /* enable */ 2383 }, 2384 #endif 2385 2386 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 87U 2387 { 2388 SIUL2_4_CLK, /* name */ 2389 1U, /* enable */ 2390 }, 2391 #endif 2392 2393 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 88U 2394 { 2395 SIUL2_5_CLK, /* name */ 2396 1U, /* enable */ 2397 }, 2398 #endif 2399 2400 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 89U 2401 { 2402 SPI0_CLK, /* name */ 2403 1U, /* enable */ 2404 }, 2405 #endif 2406 2407 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 90U 2408 { 2409 SPI1_CLK, /* name */ 2410 1U, /* enable */ 2411 }, 2412 #endif 2413 2414 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 91U 2415 { 2416 SPI2_CLK, /* name */ 2417 1U, /* enable */ 2418 }, 2419 #endif 2420 2421 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 92U 2422 { 2423 SPI3_CLK, /* name */ 2424 1U, /* enable */ 2425 }, 2426 #endif 2427 2428 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 93U 2429 { 2430 SPI4_CLK, /* name */ 2431 1U, /* enable */ 2432 }, 2433 #endif 2434 2435 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 94U 2436 { 2437 SPI5_CLK, /* name */ 2438 1U, /* enable */ 2439 }, 2440 #endif 2441 2442 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 95U 2443 { 2444 SPI6_CLK, /* name */ 2445 1U, /* enable */ 2446 }, 2447 #endif 2448 2449 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 96U 2450 { 2451 SPI7_CLK, /* name */ 2452 1U, /* enable */ 2453 }, 2454 #endif 2455 2456 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 97U 2457 { 2458 SPI8_CLK, /* name */ 2459 1U, /* enable */ 2460 }, 2461 #endif 2462 2463 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 98U 2464 { 2465 SPI9_CLK, /* name */ 2466 1U, /* enable */ 2467 }, 2468 #endif 2469 2470 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 99U 2471 { 2472 SRX0_CLK, /* name */ 2473 1U, /* enable */ 2474 }, 2475 #endif 2476 2477 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 100U 2478 { 2479 SRX1_CLK, /* name */ 2480 1U, /* enable */ 2481 }, 2482 #endif 2483 }; 2484 2485 2486 static const Clock_Ip_CmuConfigType Clock_Ip_CmuConfigurations_0[CLOCK_IP_CONFIGURED_CMUS_0_NO] = { 2487 2488 2489 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U 2490 { 2491 P2_SYS_CLK, /* Clock name associated to clock monitor. */ 2492 0U, /*Enable/disable clock monitor SMU__CMU_FC */ 2493 ( /* IER for SMU__CMU_FC */ 2494 CMU_FC_IER_FLLIE(0) | 2495 CMU_FC_IER_FHHIE(0) | 2496 CMU_FC_IER_FLLAIE(0) | 2497 CMU_FC_IER_FHHAIE(0) 2498 ), 2499 400000000U, 2500 { 2501 0U, /* Start index in register values array */ 2502 0U, /* End index in register values array */ 2503 }, 2504 }, 2505 #endif 2506 2507 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 1U 2508 { 2509 P0_REG_INTF_CLK, /* Clock name associated to clock monitor. */ 2510 0U, /*Enable/disable clock monitor CMU_FC_0 */ 2511 ( /* IER for CMU_FC_0 */ 2512 CMU_FC_IER_FLLIE(0) | 2513 CMU_FC_IER_FHHIE(0) | 2514 CMU_FC_IER_FLLAIE(0) | 2515 CMU_FC_IER_FHHAIE(0) 2516 ), 2517 133333333U, 2518 { 2519 0U, /* Start index in register values array */ 2520 0U, /* End index in register values array */ 2521 }, 2522 }, 2523 #endif 2524 2525 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 2U 2526 { 2527 P1_REG_INTF_CLK, /* Clock name associated to clock monitor. */ 2528 0U, /*Enable/disable clock monitor CMU_FC_1 */ 2529 ( /* IER for CMU_FC_1 */ 2530 CMU_FC_IER_FLLIE(0) | 2531 CMU_FC_IER_FHHIE(0) | 2532 CMU_FC_IER_FLLAIE(0) | 2533 CMU_FC_IER_FHHAIE(0) 2534 ), 2535 133333333U, 2536 { 2537 0U, /* Start index in register values array */ 2538 0U, /* End index in register values array */ 2539 }, 2540 }, 2541 #endif 2542 2543 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 3U 2544 { 2545 FIRC_CLK, /* Clock name associated to clock monitor. */ 2546 0U, /*Enable/disable clock monitor CMU_FC_2A */ 2547 ( /* IER for CMU_FC_2A */ 2548 CMU_FC_IER_FLLIE(0) | 2549 CMU_FC_IER_FHHIE(0) | 2550 CMU_FC_IER_FLLAIE(0) | 2551 CMU_FC_IER_FHHAIE(0) 2552 ), 2553 48000000U, 2554 { 2555 0U, /* Start index in register values array */ 2556 0U, /* End index in register values array */ 2557 }, 2558 }, 2559 #endif 2560 2561 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 4U 2562 { 2563 FXOSC_CLK, /* Clock name associated to clock monitor. */ 2564 0U, /*Enable/disable clock monitor CMU_FC_2B */ 2565 ( /* IER for CMU_FC_2B */ 2566 CMU_FC_IER_FLLIE(0) | 2567 CMU_FC_IER_FHHIE(0) | 2568 CMU_FC_IER_FLLAIE(0) | 2569 CMU_FC_IER_FHHAIE(0) 2570 ), 2571 40000000U, 2572 { 2573 0U, /* Start index in register values array */ 2574 0U, /* End index in register values array */ 2575 }, 2576 }, 2577 #endif 2578 2579 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 5U 2580 { 2581 P2_MATH_CLK, /* Clock name associated to clock monitor. */ 2582 0U, /*Enable/disable clock monitor CMU_FC_2C */ 2583 ( /* IER for CMU_FC_2C */ 2584 CMU_FC_IER_FLLIE(0) | 2585 CMU_FC_IER_FHHIE(0) | 2586 CMU_FC_IER_FLLAIE(0) | 2587 CMU_FC_IER_FHHAIE(0) 2588 ), 2589 400000000U, 2590 { 2591 0U, /* Start index in register values array */ 2592 0U, /* End index in register values array */ 2593 }, 2594 }, 2595 #endif 2596 2597 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 6U 2598 { 2599 P3_SYS_MON1_CLK, /* Clock name associated to clock monitor. */ 2600 0U, /*Enable/disable clock monitor CMU_FC_3 */ 2601 ( /* IER for CMU_FC_3 */ 2602 CMU_FC_IER_FLLIE(0) | 2603 CMU_FC_IER_FHHIE(0) | 2604 CMU_FC_IER_FLLAIE(0) | 2605 CMU_FC_IER_FHHAIE(0) 2606 ), 2607 400000000U, 2608 { 2609 0U, /* Start index in register values array */ 2610 0U, /* End index in register values array */ 2611 }, 2612 }, 2613 #endif 2614 2615 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 7U 2616 { 2617 P4_REG_INTF_CLK, /* Clock name associated to clock monitor. */ 2618 0U, /*Enable/disable clock monitor CMU_FC_4 */ 2619 ( /* IER for CMU_FC_4 */ 2620 CMU_FC_IER_FLLIE(0) | 2621 CMU_FC_IER_FHHIE(0) | 2622 CMU_FC_IER_FLLAIE(0) | 2623 CMU_FC_IER_FHHAIE(0) 2624 ), 2625 133333333U, 2626 { 2627 0U, /* Start index in register values array */ 2628 0U, /* End index in register values array */ 2629 }, 2630 }, 2631 #endif 2632 2633 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 8U 2634 { 2635 P5_REG_INTF_CLK, /* Clock name associated to clock monitor. */ 2636 0U, /*Enable/disable clock monitor CMU_FC_5 */ 2637 ( /* IER for CMU_FC_5 */ 2638 CMU_FC_IER_FLLIE(0) | 2639 CMU_FC_IER_FHHIE(0) | 2640 CMU_FC_IER_FLLAIE(0) | 2641 CMU_FC_IER_FHHAIE(0) 2642 ), 2643 48000000U, 2644 { 2645 0U, /* Start index in register values array */ 2646 0U, /* End index in register values array */ 2647 }, 2648 }, 2649 #endif 2650 2651 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 9U 2652 { 2653 DDR_CLK, /* Clock name associated to clock monitor. */ 2654 0U, /*Enable/disable clock monitor CMU_FC_6 */ 2655 ( /* IER for CMU_FC_6 */ 2656 CMU_FC_IER_FLLIE(0) | 2657 CMU_FC_IER_FHHIE(0) | 2658 CMU_FC_IER_FLLAIE(0) | 2659 CMU_FC_IER_FHHAIE(0) 2660 ), 2661 200000000U, 2662 { 2663 0U, /* Start index in register values array */ 2664 0U, /* End index in register values array */ 2665 }, 2666 }, 2667 #endif 2668 2669 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 10U 2670 { 2671 P3_SYS_MON2_CLK, /* Clock name associated to clock monitor. */ 2672 0U, /*Enable/disable clock monitor CE_CMU_FC_0 */ 2673 ( /* IER for CE_CMU_FC_0 */ 2674 CMU_FC_IER_FLLIE(0) | 2675 CMU_FC_IER_FHHIE(0) | 2676 CMU_FC_IER_FLLAIE(0) | 2677 CMU_FC_IER_FHHAIE(0) 2678 ), 2679 400000000U, 2680 { 2681 0U, /* Start index in register values array */ 2682 0U, /* End index in register values array */ 2683 }, 2684 }, 2685 #endif 2686 2687 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 11U 2688 { 2689 P3_SYS_MON3_CLK, /* Clock name associated to clock monitor. */ 2690 0U, /*Enable/disable clock monitor CE_CMU_FC_1 */ 2691 ( /* IER for CE_CMU_FC_1 */ 2692 CMU_FC_IER_FLLIE(0) | 2693 CMU_FC_IER_FHHIE(0) | 2694 CMU_FC_IER_FLLAIE(0) | 2695 CMU_FC_IER_FHHAIE(0) 2696 ), 2697 400000000U, 2698 { 2699 0U, /* Start index in register values array */ 2700 0U, /* End index in register values array */ 2701 }, 2702 }, 2703 #endif 2704 2705 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 12U 2706 { 2707 CE_SYS_DIV2_CLK, /* Clock name associated to clock monitor. */ 2708 0U, /*Enable/disable clock monitor CE_CMU_FC_2 */ 2709 ( /* IER for CE_CMU_FC_2 */ 2710 CMU_FC_IER_FLLIE(0) | 2711 CMU_FC_IER_FHHIE(0) | 2712 CMU_FC_IER_FLLAIE(0) | 2713 CMU_FC_IER_FHHAIE(0) 2714 ), 2715 200000000U, 2716 { 2717 0U, /* Start index in register values array */ 2718 0U, /* End index in register values array */ 2719 }, 2720 }, 2721 #endif 2722 2723 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 13U 2724 { 2725 P0_CLKOUT_SRC_CLK, /* Clock name associated to clock monitor. */ 2726 0U, /*Enable/disable clock monitor CMU_FC_DEBUG_1 */ 2727 ( /* IER for CMU_FC_DEBUG_1 */ 2728 CMU_FC_IER_FLLIE(0) | 2729 CMU_FC_IER_FHHIE(0) | 2730 CMU_FC_IER_FLLAIE(0) | 2731 CMU_FC_IER_FHHAIE(0) 2732 ), 2733 48000000U, 2734 { 2735 0U, /* Start index in register values array */ 2736 0U, /* End index in register values array */ 2737 }, 2738 }, 2739 #endif 2740 2741 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 14U 2742 { 2743 P1_CLKOUT_SRC_CLK, /* Clock name associated to clock monitor. */ 2744 0U, /*Enable/disable clock monitor CMU_FC_DEBUG_2 */ 2745 ( /* IER for CMU_FC_DEBUG_2 */ 2746 CMU_FC_IER_FLLIE(0) | 2747 CMU_FC_IER_FHHIE(0) | 2748 CMU_FC_IER_FLLAIE(0) | 2749 CMU_FC_IER_FHHAIE(0) 2750 ), 2751 400000000U, 2752 { 2753 0U, /* Start index in register values array */ 2754 0U, /* End index in register values array */ 2755 }, 2756 }, 2757 #endif 2758 }; 2759 2760 2761 static const Clock_Ip_ConfiguredFrequencyType Clock_Ip_ConfiguredFrequencyConfigurations_0[CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT] = { 2762 2763 { 2764 CLOCK_IS_OFF, 2765 0U, 2766 }, 2767 2768 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 1U 2769 { 2770 FIRC_CLK, 2771 48000000U, 2772 }, 2773 #endif 2774 2775 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 2U 2776 { 2777 FXOSC_CLK, 2778 40000000U, 2779 }, 2780 #endif 2781 2782 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 3U 2783 { 2784 CE_SYS_DIV4_CLK, 2785 100000000U, 2786 }, 2787 #endif 2788 2789 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 4U 2790 { 2791 P0_REG_INTF_CLK, 2792 133333333U, 2793 }, 2794 #endif 2795 2796 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 5U 2797 { 2798 P1_REG_INTF_CLK, 2799 133333333U, 2800 }, 2801 #endif 2802 2803 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 6U 2804 { 2805 P2_MATH_DIV3_CLK, 2806 133333333U, 2807 }, 2808 #endif 2809 2810 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 7U 2811 { 2812 P2_REG_INTF_CLK, 2813 16000000U, 2814 }, 2815 #endif 2816 2817 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 8U 2818 { 2819 P2_SYS_DIV4_CLK, 2820 100000000U, 2821 }, 2822 #endif 2823 2824 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 9U 2825 { 2826 P3_REG_INTF_CLK, 2827 48000000U, 2828 }, 2829 #endif 2830 2831 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 10U 2832 { 2833 P4_REG_INTF_CLK, 2834 133333333U, 2835 }, 2836 #endif 2837 2838 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 11U 2839 { 2840 P5_REG_INTF_CLK, 2841 48000000U, 2842 }, 2843 #endif 2844 2845 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 12U 2846 { 2847 P6_REG_INTF_CLK, 2848 48000000U, 2849 }, 2850 #endif 2851 2852 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 13U 2853 { 2854 RTU0_CORE_CLK, 2855 1000000000U, 2856 }, 2857 #endif 2858 2859 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 14U 2860 { 2861 RTU0_REG_INTF_CLK, 2862 133333333U, 2863 }, 2864 #endif 2865 2866 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 15U 2867 { 2868 RTU1_CORE_CLK, 2869 1000000000U, 2870 }, 2871 #endif 2872 2873 #if CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT > 16U 2874 { 2875 RTU1_REG_INTF_CLK, 2876 133333333U, 2877 }, 2878 #endif 2879 }; 2880 2881 2882 /* ************************************************************************* 2883 * Configuration structure for Clock Configuration 2884 * ************************************************************************* */ 2885 const Clock_Ip_ClockConfigType Clock_Ip_aClockConfig[1U] = { 2886 2887 /*! @brief User Configuration structure clock_Cfg_0 */ 2888 { 2889 0U, /* clkConfigId */ 2890 2891 (NULL_PTR), /* Register data if register value optimization is enabled */ 2892 0U, /* ircoscsCount */ 2893 1U, /* xoscsCount */ 2894 5U, /* pllsCount */ 2895 63U, /* selectorsCount */ 2896 85U, /* dividersCount */ 2897 1U, /* dividerTriggersCount */ 2898 12U, /* fracDivsCount */ 2899 8U, /* extClksCount */ 2900 101U, /* gatesCount */ 2901 0U, /* pcfsCount */ 2902 15U, /* cmusCount */ 2903 17U, /* configureFrequenciesCount */ 2904 2905 (NULL_PTR), /* Ircosc configurations */ 2906 (&Clock_Ip_XoscConfigurations_0), /* Xosc configurations */ 2907 (&Clock_Ip_PllConfigurations_0), /* Pll configurations */ 2908 (&Clock_Ip_SelectorConfigurations_0), /* Selectors configurations */ 2909 (&Clock_Ip_DividerConfigurations_0), /* dividers configurations */ 2910 (&Clock_Ip_DividerTriggerConfigurations_0), /* dividerTriggers configurations */ 2911 (&Clock_Ip_FracDivsConfigurations_0), /* fracDivs configurations */ 2912 (&Clock_Ip_ExtClkConfigurations_0), /* extClks configurations */ 2913 (&Clock_Ip_GatesConfigurations_0), /* gates configurations */ 2914 (NULL_PTR), /* pcfs configurations */ 2915 (&Clock_Ip_CmuConfigurations_0), /* cmus configurations */ 2916 (&Clock_Ip_ConfiguredFrequencyConfigurations_0), /* configureFrequencies configurations */ 2917 }, 2918 }; 2919 2920 2921 #define MCU_STOP_SEC_CONFIG_DATA_UNSPECIFIED 2922 #include "Mcu_MemMap.h" 2923 2924 2925 /*================================================================================================== 2926 LOCAL FUNCTION PROTOTYPES 2927 ==================================================================================================*/ 2928 2929 /*================================================================================================== 2930 LOCAL FUNCTIONS 2931 ==================================================================================================*/ 2932 2933 /*================================================================================================== 2934 GLOBAL FUNCTIONS 2935 ==================================================================================================*/ 2936 2937 #ifdef __cplusplus 2938 } 2939 #endif 2940 2941 /** @} */ 2942
