1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /** 8 * @file Clock_Ip_Cfg.c 9 * @version 3.0.0 10 * 11 * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. 12 * @details Code template for Post-Build(PB) configuration file generation. 13 * 14 * @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver 15 * @{ 16 */ 17 18 19 #ifdef __cplusplus 20 extern "C"{ 21 #endif 22 23 24 /*================================================================================================== 25 INCLUDE FILES 26 1) system and project includes 27 2) needed interfaces from external units 28 3) internal and external interfaces from this unit 29 ==================================================================================================*/ 30 #include "Clock_Ip_Cfg.h" 31 #include "StandardTypes.h" 32 #include "Clock_Ip.h" 33 #include "Clock_Ip_Private.h" 34 35 /*================================================================================================== 36 * SOURCE FILE VERSION INFORMATION 37 ==================================================================================================*/ 38 #define CLOCK_IP_CFG_VENDOR_ID_C 43 39 #define CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C 4 40 #define CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C 7 41 #define CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C 0 42 #define CLOCK_IP_CFG_SW_MAJOR_VERSION_C 3 43 #define CLOCK_IP_CFG_SW_MINOR_VERSION_C 0 44 #define CLOCK_IP_CFG_SW_PATCH_VERSION_C 0 45 46 /*================================================================================================== 47 * FILE VERSION CHECKS 48 ==================================================================================================*/ 49 /* Check if source file and Clock_Ip_Cfg.h file are of the same vendor */ 50 #if (CLOCK_IP_CFG_VENDOR_ID_C != CLOCK_IP_CFG_VENDOR_ID) 51 #error "Clock_Ip_Cfg.c and Clock_Ip_Cfg.h have different vendor ids" 52 #endif 53 54 /* Check if source file and Clock_Ip_Cfg.h file are of the same Autosar version */ 55 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \ 56 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION) || \ 57 (CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION) \ 58 ) 59 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Cfg.h are different" 60 #endif 61 62 /* Check if source file and Clock_Ip_Cfg.h file are of the same Software version */ 63 #if ((CLOCK_IP_CFG_SW_MAJOR_VERSION_C != CLOCK_IP_CFG_SW_MAJOR_VERSION) || \ 64 (CLOCK_IP_CFG_SW_MINOR_VERSION_C != CLOCK_IP_CFG_SW_MINOR_VERSION) || \ 65 (CLOCK_IP_CFG_SW_PATCH_VERSION_C != CLOCK_IP_CFG_SW_PATCH_VERSION) \ 66 ) 67 #error "Software Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Cfg.h are different" 68 #endif 69 70 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 71 /* Check if source file and StandardTypes.h file are of the same Autosar version */ 72 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != STD_AR_RELEASE_MAJOR_VERSION) || \ 73 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != STD_AR_RELEASE_MINOR_VERSION) \ 74 ) 75 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and StandardTypes.h are different" 76 #endif 77 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */ 78 79 /* Check if source file and Clock_Ip.h file are of the same vendor */ 80 #if (CLOCK_IP_CFG_VENDOR_ID_C != CLOCK_IP_VENDOR_ID) 81 #error "Clock_Ip_Cfg.c and Clock_Ip.h have different vendor ids" 82 #endif 83 84 /* Check if source file and Clock_Ip.h file are of the same Autosar version */ 85 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_AR_RELEASE_MAJOR_VERSION) || \ 86 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_AR_RELEASE_MINOR_VERSION) || \ 87 (CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_AR_RELEASE_REVISION_VERSION) \ 88 ) 89 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and Clock_Ip.h are different" 90 #endif 91 92 /* Check if source file and Clock_Ip.h file are of the same Software version */ 93 #if ((CLOCK_IP_CFG_SW_MAJOR_VERSION_C != CLOCK_IP_SW_MAJOR_VERSION) || \ 94 (CLOCK_IP_CFG_SW_MINOR_VERSION_C != CLOCK_IP_SW_MINOR_VERSION) || \ 95 (CLOCK_IP_CFG_SW_PATCH_VERSION_C != CLOCK_IP_SW_PATCH_VERSION) \ 96 ) 97 #error "Software Version Numbers of Clock_Ip_Cfg.c and Clock_Ip.h are different" 98 #endif 99 100 /* Check if source file and Clock_Ip_Private.h file are of the same vendor */ 101 #if (CLOCK_IP_CFG_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID) 102 #error "Clock_Ip_Cfg.c and Clock_Ip_Private.h have different vendor ids" 103 #endif 104 105 /* Check if source file and Clock_Ip_Private.h file are of the same Autosar version */ 106 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \ 107 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \ 108 (CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \ 109 ) 110 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Private.h are different" 111 #endif 112 113 /* Check if source file and Clock_Ip_Private.h file are of the same Software version */ 114 #if ((CLOCK_IP_CFG_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \ 115 (CLOCK_IP_CFG_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \ 116 (CLOCK_IP_CFG_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \ 117 ) 118 #error "Software Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Private.h are different" 119 #endif 120 121 /*================================================================================================== 122 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) 123 ==================================================================================================*/ 124 125 /*================================================================================================== 126 LOCAL MACROS 127 ==================================================================================================*/ 128 129 /*================================================================================================== 130 LOCAL CONSTANTS 131 ==================================================================================================*/ 132 133 /*================================================================================================== 134 LOCAL VARIABLES 135 ==================================================================================================*/ 136 137 /*================================================================================================== 138 GLOBAL CONSTANTS 139 ==================================================================================================*/ 140 141 /*================================================================================================== 142 GLOBAL VARIABLES 143 ==================================================================================================*/ 144 145 146 #define MCU_START_SEC_CONFIG_DATA_UNSPECIFIED 147 #include "Mcu_MemMap.h" 148 149 150 151 static const Clock_Ip_IrcoscConfigType Clock_Ip_IrcoscConfigurations_0[CLOCK_IP_CONFIGURED_IRCOSCS_0_NO] = { 152 153 #if CLOCK_IP_CONFIGURED_IRCOSCS_0_NO > 0U 154 { 155 FIRC_CLK, /* name */ 156 1U, /* Always enabled. */ 157 0U, /* Enable regulator */ 158 CLOCK_IP_SUPPORTS_48MHZ_FREQUENCY, /* Ircosc range */ 159 0U, /* Ircosc enable in VLP mode */ 160 0U, /* Ircosc enable in STOP mode */ 161 }, 162 #endif 163 164 #if CLOCK_IP_CONFIGURED_IRCOSCS_0_NO > 1U 165 { 166 FIRC_STANDBY_CLK, /* name */ 167 0U, /* Disabled in standby mode. */ 168 0U, /* Enable regulator */ 169 0U, /* Ircosc range */ 170 0U, /* Ircosc enable in VLP mode */ 171 0U, /* Ircosc enable in STOP mode */ 172 }, 173 #endif 174 175 #if CLOCK_IP_CONFIGURED_IRCOSCS_0_NO > 2U 176 { 177 SIRC_STANDBY_CLK, /* name */ 178 0U, /* Disabled in standby mode. */ 179 0U, /* Enable regulator */ 180 0U, /* Ircosc range */ 181 0U, /* Ircosc enable in VLP mode */ 182 0U, /* Ircosc enable in STOP mode */ 183 }, 184 #endif 185 }; 186 187 188 static const Clock_Ip_XoscConfigType Clock_Ip_XoscConfigurations_0[CLOCK_IP_CONFIGURED_XOSCS_0_NO] = { 189 190 #if CLOCK_IP_CONFIGURED_XOSCS_0_NO > 0U 191 { 192 FXOSC_CLK, /* name */ 193 16000000U, /* frequency */ 194 1U, /* enable */ 195 157U, /* startupDelay */ 196 0U, /* bypassOption: Xosc use crystal */ 197 1U, /* Comparator is enabled */ 198 12U, /* TransConductance */ 199 0U, /* Gain value */ 200 0U, /* Monitor type */ 201 0U, /* Automatic level controller */ 202 }, 203 #endif 204 205 #if CLOCK_IP_CONFIGURED_XOSCS_0_NO > 1U 206 { 207 SXOSC_CLK, /* name */ 208 32768U, /* frequency */ 209 1U, /* enable */ 210 125U, /* startupDelay */ 211 0U, /* bypassOption */ 212 0U, /* Comparator is not enabled */ 213 0U, /* Crystal overdrive protection */ 214 0U, /* Gain value */ 215 0U, /* Monitor type */ 216 0U, /* Automatic level controller */ 217 }, 218 #endif 219 }; 220 221 222 static const Clock_Ip_PllConfigType Clock_Ip_PllConfigurations_0[CLOCK_IP_CONFIGURED_PLLS_0_NO] = { 223 224 #if CLOCK_IP_CONFIGURED_PLLS_0_NO > 0U 225 { 226 PLL_CLK, /* name */ 227 1U, /* enable */ 228 FXOSC_CLK, /* inputReference */ 229 0U, /* Bypass */ 230 2U, /* predivider */ 231 0U, /* multiplier */ 232 0U, /* postdivider */ 233 0U, /* numeratorFracLoopDiv */ 234 120U, /* mulFactorDiv */ 235 1U, /* ModulationBypass */ 236 0U, /* Modulation type: Spread spectrum modulation bypassed */ 237 0U, /* modulationPeriod */ 238 0U, /* incrementStep */ 239 0U, /* sigmaDelta */ 240 0U, /* ditherControl */ 241 0U, /* ditherControlValue */ 242 0U, /* Monitor type */ 243 { 244 0U, 245 0U, 246 0U, 247 }, 248 }, 249 #endif 250 }; 251 252 253 static const Clock_Ip_SelectorConfigType Clock_Ip_SelectorConfigurations_0[CLOCK_IP_CONFIGURED_SELECTORS_0_NO] = { 254 255 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 0U 256 { 257 SCS_CLK, /* Clock name associated to selector */ 258 PLL_PHI0_CLK, /* Name of the selected input source */ 259 }, 260 #endif 261 262 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 1U 263 { 264 CLKOUT_RUN_CLK, /* Clock name associated to selector */ 265 FXOSC_CLK, /* Name of the selected input source */ 266 }, 267 #endif 268 269 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 2U 270 { 271 CLKOUT_STANDBY_CLK, /* Clock name associated to selector */ 272 FIRC_CLK, /* Name of the selected input source */ 273 }, 274 #endif 275 276 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 3U 277 { 278 EMAC_RX_CLK, /* Clock name associated to selector */ 279 FIRC_CLK, /* Name of the selected input source */ 280 }, 281 #endif 282 283 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 4U 284 { 285 EMAC_TS_CLK, /* Clock name associated to selector */ 286 FIRC_CLK, /* Name of the selected input source */ 287 }, 288 #endif 289 290 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 5U 291 { 292 EMAC_TX_CLK, /* Clock name associated to selector */ 293 FIRC_CLK, /* Name of the selected input source */ 294 }, 295 #endif 296 297 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 6U 298 { 299 FLEXCANA_CLK, /* Clock name associated to selector */ 300 AIPS_PLAT_CLK, /* Name of the selected input source */ 301 }, 302 #endif 303 304 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 7U 305 { 306 FLEXCANB_CLK, /* Clock name associated to selector */ 307 AIPS_PLAT_CLK, /* Name of the selected input source */ 308 }, 309 #endif 310 311 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 8U 312 { 313 QSPI_SFCK_CLK, /* Clock name associated to selector */ 314 FIRC_CLK, /* Name of the selected input source */ 315 }, 316 #endif 317 318 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 9U 319 { 320 RTC_CLK, /* Clock name associated to selector */ 321 SXOSC_CLK, /* Name of the selected input source */ 322 }, 323 #endif 324 325 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 10U 326 { 327 STMA_CLK, /* Clock name associated to selector */ 328 FIRC_CLK, /* Name of the selected input source */ 329 }, 330 #endif 331 332 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 11U 333 { 334 STMB_CLK, /* Clock name associated to selector */ 335 FIRC_CLK, /* Name of the selected input source */ 336 }, 337 #endif 338 339 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 12U 340 { 341 TRACE_CLK, /* Clock name associated to selector */ 342 FIRC_CLK, /* Name of the selected input source */ 343 }, 344 #endif 345 }; 346 347 348 static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_IP_CONFIGURED_DIVIDERS_0_NO] = { 349 350 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 0U 351 { 352 PLL_POSTDIV_CLK, /* name */ 353 2U, /* value */ 354 { 355 0U, 356 } 357 }, 358 #endif 359 360 361 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 1U 362 { 363 PLL_PHI0_CLK, /* name */ 364 3U, /* value */ 365 { 366 0U, 367 } 368 }, 369 #endif 370 371 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 2U 372 { 373 PLL_PHI1_CLK, /* name */ 374 3U, /* value */ 375 { 376 0U, 377 } 378 }, 379 #endif 380 381 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 3U 382 { 383 CORE_CLK, /* name */ 384 1U, /* value */ 385 { 386 0U, 387 } 388 }, 389 #endif 390 391 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 4U 392 { 393 AIPS_PLAT_CLK, /* name */ 394 2U, /* value */ 395 { 396 0U, 397 } 398 }, 399 #endif 400 401 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 5U 402 { 403 AIPS_SLOW_CLK, /* name */ 404 4U, /* value */ 405 { 406 0U, 407 } 408 }, 409 #endif 410 411 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 6U 412 { 413 HSE_CLK, /* name */ 414 2U, /* value */ 415 { 416 0U, 417 } 418 }, 419 #endif 420 421 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 7U 422 { 423 DCM_CLK, /* name */ 424 4U, /* value */ 425 { 426 0U, 427 } 428 }, 429 #endif 430 431 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 8U 432 { 433 LBIST_CLK, /* name */ 434 4U, /* value */ 435 { 436 0U, 437 } 438 }, 439 #endif 440 441 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 9U 442 { 443 QSPI_MEM_CLK, /* name */ 444 1U, /* value */ 445 { 446 0U, 447 } 448 }, 449 #endif 450 451 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 10U 452 { 453 CLKOUT_RUN_CLK, /* name */ 454 2U, /* value */ 455 { 456 0U, 457 } 458 }, 459 #endif 460 461 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 11U 462 { 463 CLKOUT_STANDBY_CLK, /* name */ 464 2U, /* value */ 465 { 466 0U, 467 } 468 }, 469 #endif 470 471 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 12U 472 { 473 EMAC_RX_CLK, /* name */ 474 1U, /* value */ 475 { 476 0U, 477 } 478 }, 479 #endif 480 481 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 13U 482 { 483 EMAC_TS_CLK, /* name */ 484 1U, /* value */ 485 { 486 0U, 487 } 488 }, 489 #endif 490 491 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 14U 492 { 493 EMAC_TX_CLK, /* name */ 494 1U, /* value */ 495 { 496 0U, 497 } 498 }, 499 #endif 500 501 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 15U 502 { 503 FLEXCANA_CLK, /* name */ 504 1U, /* value */ 505 { 506 0U, 507 } 508 }, 509 #endif 510 511 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 16U 512 { 513 FLEXCANB_CLK, /* name */ 514 1U, /* value */ 515 { 516 0U, 517 } 518 }, 519 #endif 520 521 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 17U 522 { 523 QSPI_SFCK_CLK, /* name */ 524 1U, /* value */ 525 { 526 0U, 527 } 528 }, 529 #endif 530 531 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 18U 532 { 533 STMA_CLK, /* name */ 534 1U, /* value */ 535 { 536 0U, 537 } 538 }, 539 #endif 540 541 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 19U 542 { 543 STMB_CLK, /* name */ 544 1U, /* value */ 545 { 546 0U, 547 } 548 }, 549 #endif 550 551 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 20U 552 { 553 TRACE_CLK, /* name */ 554 1U, /* value */ 555 { 556 0U, 557 } 558 }, 559 #endif 560 }; 561 562 563 static const Clock_Ip_DividerTriggerConfigType Clock_Ip_DividerTriggerConfigurations_0[CLOCK_IP_CONFIGURED_DIVIDER_TRIGGERS_0_NO] = { 564 565 #if CLOCK_IP_CONFIGURED_DIVIDER_TRIGGERS_0_NO > 0U 566 { 567 CORE_CLK, /* divider name */ 568 COMMON_TRIGGER_DIVIDER_UPDATE, /* trigger value */ 569 CORE_CLK, /* input source name */ 570 }, 571 #endif 572 }; 573 574 575 static const Clock_Ip_ExtClkConfigType Clock_Ip_ExtClkConfigurations_0[CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO] = { 576 577 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 0U 578 { 579 EMAC_MII_RX_CLK, /* name */ 580 0U, /* value */ 581 }, 582 #endif 583 584 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 1U 585 { 586 EMAC_MII_RMII_TX_CLK, /* name */ 587 0U, /* value */ 588 }, 589 #endif 590 }; 591 592 593 static const Clock_Ip_GateConfigType Clock_Ip_GatesConfigurations_0[CLOCK_IP_CONFIGURED_GATES_0_NO] = { 594 595 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 0U 596 { 597 ADC0_CLK, /* name */ 598 1U, /* enable */ 599 }, 600 #endif 601 602 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 1U 603 { 604 ADC1_CLK, /* name */ 605 1U, /* enable */ 606 }, 607 #endif 608 609 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 2U 610 { 611 ADC2_CLK, /* name */ 612 1U, /* enable */ 613 }, 614 #endif 615 616 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 3U 617 { 618 BCTU0_CLK, /* name */ 619 1U, /* enable */ 620 }, 621 #endif 622 623 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 4U 624 { 625 CMP0_CLK, /* name */ 626 1U, /* enable */ 627 }, 628 #endif 629 630 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 5U 631 { 632 CMP1_CLK, /* name */ 633 1U, /* enable */ 634 }, 635 #endif 636 637 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 6U 638 { 639 CMP2_CLK, /* name */ 640 1U, /* enable */ 641 }, 642 #endif 643 644 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 7U 645 { 646 CRC0_CLK, /* name */ 647 1U, /* enable */ 648 }, 649 #endif 650 651 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 8U 652 { 653 DMAMUX0_CLK, /* name */ 654 1U, /* enable */ 655 }, 656 #endif 657 658 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 9U 659 { 660 DMAMUX1_CLK, /* name */ 661 1U, /* enable */ 662 }, 663 #endif 664 665 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 10U 666 { 667 EDMA0_CLK, /* name */ 668 1U, /* enable */ 669 }, 670 #endif 671 672 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 11U 673 { 674 EDMA0_TCD0_CLK, /* name */ 675 1U, /* enable */ 676 }, 677 #endif 678 679 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 12U 680 { 681 EDMA0_TCD1_CLK, /* name */ 682 1U, /* enable */ 683 }, 684 #endif 685 686 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 13U 687 { 688 EDMA0_TCD2_CLK, /* name */ 689 1U, /* enable */ 690 }, 691 #endif 692 693 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 14U 694 { 695 EDMA0_TCD3_CLK, /* name */ 696 1U, /* enable */ 697 }, 698 #endif 699 700 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 15U 701 { 702 EDMA0_TCD4_CLK, /* name */ 703 1U, /* enable */ 704 }, 705 #endif 706 707 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 16U 708 { 709 EDMA0_TCD5_CLK, /* name */ 710 1U, /* enable */ 711 }, 712 #endif 713 714 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 17U 715 { 716 EDMA0_TCD6_CLK, /* name */ 717 1U, /* enable */ 718 }, 719 #endif 720 721 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 18U 722 { 723 EDMA0_TCD7_CLK, /* name */ 724 1U, /* enable */ 725 }, 726 #endif 727 728 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 19U 729 { 730 EDMA0_TCD8_CLK, /* name */ 731 1U, /* enable */ 732 }, 733 #endif 734 735 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 20U 736 { 737 EDMA0_TCD9_CLK, /* name */ 738 1U, /* enable */ 739 }, 740 #endif 741 742 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 21U 743 { 744 EDMA0_TCD10_CLK, /* name */ 745 1U, /* enable */ 746 }, 747 #endif 748 749 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 22U 750 { 751 EDMA0_TCD11_CLK, /* name */ 752 1U, /* enable */ 753 }, 754 #endif 755 756 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 23U 757 { 758 EDMA0_TCD12_CLK, /* name */ 759 1U, /* enable */ 760 }, 761 #endif 762 763 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 24U 764 { 765 EDMA0_TCD13_CLK, /* name */ 766 1U, /* enable */ 767 }, 768 #endif 769 770 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 25U 771 { 772 EDMA0_TCD14_CLK, /* name */ 773 1U, /* enable */ 774 }, 775 #endif 776 777 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 26U 778 { 779 EDMA0_TCD15_CLK, /* name */ 780 1U, /* enable */ 781 }, 782 #endif 783 784 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 27U 785 { 786 EDMA0_TCD16_CLK, /* name */ 787 1U, /* enable */ 788 }, 789 #endif 790 791 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 28U 792 { 793 EDMA0_TCD17_CLK, /* name */ 794 1U, /* enable */ 795 }, 796 #endif 797 798 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 29U 799 { 800 EDMA0_TCD18_CLK, /* name */ 801 1U, /* enable */ 802 }, 803 #endif 804 805 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 30U 806 { 807 EDMA0_TCD19_CLK, /* name */ 808 1U, /* enable */ 809 }, 810 #endif 811 812 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 31U 813 { 814 EDMA0_TCD20_CLK, /* name */ 815 1U, /* enable */ 816 }, 817 #endif 818 819 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 32U 820 { 821 EDMA0_TCD21_CLK, /* name */ 822 1U, /* enable */ 823 }, 824 #endif 825 826 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 33U 827 { 828 EDMA0_TCD22_CLK, /* name */ 829 1U, /* enable */ 830 }, 831 #endif 832 833 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 34U 834 { 835 EDMA0_TCD23_CLK, /* name */ 836 1U, /* enable */ 837 }, 838 #endif 839 840 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 35U 841 { 842 EDMA0_TCD24_CLK, /* name */ 843 1U, /* enable */ 844 }, 845 #endif 846 847 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 36U 848 { 849 EDMA0_TCD25_CLK, /* name */ 850 1U, /* enable */ 851 }, 852 #endif 853 854 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 37U 855 { 856 EDMA0_TCD26_CLK, /* name */ 857 1U, /* enable */ 858 }, 859 #endif 860 861 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 38U 862 { 863 EDMA0_TCD27_CLK, /* name */ 864 1U, /* enable */ 865 }, 866 #endif 867 868 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 39U 869 { 870 EDMA0_TCD28_CLK, /* name */ 871 1U, /* enable */ 872 }, 873 #endif 874 875 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 40U 876 { 877 EDMA0_TCD29_CLK, /* name */ 878 1U, /* enable */ 879 }, 880 #endif 881 882 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 41U 883 { 884 EDMA0_TCD30_CLK, /* name */ 885 1U, /* enable */ 886 }, 887 #endif 888 889 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 42U 890 { 891 EDMA0_TCD31_CLK, /* name */ 892 1U, /* enable */ 893 }, 894 #endif 895 896 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 43U 897 { 898 EIM_CLK, /* name */ 899 1U, /* enable */ 900 }, 901 #endif 902 903 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 44U 904 { 905 EMAC0_RX_CLK, /* name */ 906 1U, /* enable */ 907 }, 908 #endif 909 910 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 45U 911 { 912 EMIOS0_CLK, /* name */ 913 1U, /* enable */ 914 }, 915 #endif 916 917 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 46U 918 { 919 EMIOS1_CLK, /* name */ 920 1U, /* enable */ 921 }, 922 #endif 923 924 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 47U 925 { 926 EMIOS2_CLK, /* name */ 927 1U, /* enable */ 928 }, 929 #endif 930 931 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 48U 932 { 933 ERM0_CLK, /* name */ 934 1U, /* enable */ 935 }, 936 #endif 937 938 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 49U 939 { 940 FLEXCAN0_CLK, /* name */ 941 1U, /* enable */ 942 }, 943 #endif 944 945 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 50U 946 { 947 FLEXCAN1_CLK, /* name */ 948 1U, /* enable */ 949 }, 950 #endif 951 952 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 51U 953 { 954 FLEXCAN2_CLK, /* name */ 955 1U, /* enable */ 956 }, 957 #endif 958 959 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 52U 960 { 961 FLEXCAN3_CLK, /* name */ 962 1U, /* enable */ 963 }, 964 #endif 965 966 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 53U 967 { 968 FLEXCAN4_CLK, /* name */ 969 1U, /* enable */ 970 }, 971 #endif 972 973 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 54U 974 { 975 FLEXCAN5_CLK, /* name */ 976 1U, /* enable */ 977 }, 978 #endif 979 980 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 55U 981 { 982 FLEXIO0_CLK, /* name */ 983 1U, /* enable */ 984 }, 985 #endif 986 987 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 56U 988 { 989 INTM_CLK, /* name */ 990 1U, /* enable */ 991 }, 992 #endif 993 994 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 57U 995 { 996 LCU0_CLK, /* name */ 997 1U, /* enable */ 998 }, 999 #endif 1000 1001 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 58U 1002 { 1003 LCU1_CLK, /* name */ 1004 1U, /* enable */ 1005 }, 1006 #endif 1007 1008 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 59U 1009 { 1010 LPI2C0_CLK, /* name */ 1011 1U, /* enable */ 1012 }, 1013 #endif 1014 1015 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 60U 1016 { 1017 LPI2C1_CLK, /* name */ 1018 1U, /* enable */ 1019 }, 1020 #endif 1021 1022 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 61U 1023 { 1024 LPSPI0_CLK, /* name */ 1025 1U, /* enable */ 1026 }, 1027 #endif 1028 1029 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 62U 1030 { 1031 LPSPI1_CLK, /* name */ 1032 1U, /* enable */ 1033 }, 1034 #endif 1035 1036 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 63U 1037 { 1038 LPSPI2_CLK, /* name */ 1039 1U, /* enable */ 1040 }, 1041 #endif 1042 1043 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 64U 1044 { 1045 LPSPI3_CLK, /* name */ 1046 1U, /* enable */ 1047 }, 1048 #endif 1049 1050 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 65U 1051 { 1052 LPSPI4_CLK, /* name */ 1053 1U, /* enable */ 1054 }, 1055 #endif 1056 1057 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 66U 1058 { 1059 LPSPI5_CLK, /* name */ 1060 1U, /* enable */ 1061 }, 1062 #endif 1063 1064 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 67U 1065 { 1066 LPUART0_CLK, /* name */ 1067 1U, /* enable */ 1068 }, 1069 #endif 1070 1071 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 68U 1072 { 1073 LPUART1_CLK, /* name */ 1074 1U, /* enable */ 1075 }, 1076 #endif 1077 1078 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 69U 1079 { 1080 LPUART2_CLK, /* name */ 1081 1U, /* enable */ 1082 }, 1083 #endif 1084 1085 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 70U 1086 { 1087 LPUART3_CLK, /* name */ 1088 1U, /* enable */ 1089 }, 1090 #endif 1091 1092 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 71U 1093 { 1094 LPUART4_CLK, /* name */ 1095 1U, /* enable */ 1096 }, 1097 #endif 1098 1099 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 72U 1100 { 1101 LPUART5_CLK, /* name */ 1102 1U, /* enable */ 1103 }, 1104 #endif 1105 1106 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 73U 1107 { 1108 LPUART6_CLK, /* name */ 1109 1U, /* enable */ 1110 }, 1111 #endif 1112 1113 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 74U 1114 { 1115 LPUART7_CLK, /* name */ 1116 1U, /* enable */ 1117 }, 1118 #endif 1119 1120 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 75U 1121 { 1122 LPUART8_CLK, /* name */ 1123 1U, /* enable */ 1124 }, 1125 #endif 1126 1127 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 76U 1128 { 1129 LPUART9_CLK, /* name */ 1130 1U, /* enable */ 1131 }, 1132 #endif 1133 1134 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 77U 1135 { 1136 LPUART10_CLK, /* name */ 1137 1U, /* enable */ 1138 }, 1139 #endif 1140 1141 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 78U 1142 { 1143 LPUART11_CLK, /* name */ 1144 1U, /* enable */ 1145 }, 1146 #endif 1147 1148 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 79U 1149 { 1150 LPUART12_CLK, /* name */ 1151 1U, /* enable */ 1152 }, 1153 #endif 1154 1155 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 80U 1156 { 1157 LPUART13_CLK, /* name */ 1158 1U, /* enable */ 1159 }, 1160 #endif 1161 1162 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 81U 1163 { 1164 LPUART14_CLK, /* name */ 1165 1U, /* enable */ 1166 }, 1167 #endif 1168 1169 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 82U 1170 { 1171 LPUART15_CLK, /* name */ 1172 1U, /* enable */ 1173 }, 1174 #endif 1175 1176 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 83U 1177 { 1178 MSCM_CLK, /* name */ 1179 1U, /* enable */ 1180 }, 1181 #endif 1182 1183 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 84U 1184 { 1185 PIT0_CLK, /* name */ 1186 1U, /* enable */ 1187 }, 1188 #endif 1189 1190 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 85U 1191 { 1192 PIT1_CLK, /* name */ 1193 1U, /* enable */ 1194 }, 1195 #endif 1196 1197 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 86U 1198 { 1199 PIT2_CLK, /* name */ 1200 1U, /* enable */ 1201 }, 1202 #endif 1203 1204 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 87U 1205 { 1206 QSPI0_RAM_CLK, /* name */ 1207 1U, /* enable */ 1208 }, 1209 #endif 1210 1211 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 88U 1212 { 1213 RTC0_CLK, /* name */ 1214 1U, /* enable */ 1215 }, 1216 #endif 1217 1218 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 89U 1219 { 1220 SAI0_CLK, /* name */ 1221 1U, /* enable */ 1222 }, 1223 #endif 1224 1225 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 90U 1226 { 1227 SAI1_CLK, /* name */ 1228 1U, /* enable */ 1229 }, 1230 #endif 1231 1232 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 91U 1233 { 1234 SEMA42_CLK, /* name */ 1235 1U, /* enable */ 1236 }, 1237 #endif 1238 1239 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 92U 1240 { 1241 SIUL2_CLK, /* name */ 1242 1U, /* enable */ 1243 }, 1244 #endif 1245 1246 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 93U 1247 { 1248 STM0_CLK, /* name */ 1249 1U, /* enable */ 1250 }, 1251 #endif 1252 1253 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 94U 1254 { 1255 STM1_CLK, /* name */ 1256 1U, /* enable */ 1257 }, 1258 #endif 1259 1260 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 95U 1261 { 1262 SWT0_CLK, /* name */ 1263 1U, /* enable */ 1264 }, 1265 #endif 1266 1267 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 96U 1268 { 1269 TEMPSENSE_CLK, /* name */ 1270 1U, /* enable */ 1271 }, 1272 #endif 1273 1274 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 97U 1275 { 1276 TRGMUX0_CLK, /* name */ 1277 1U, /* enable */ 1278 }, 1279 #endif 1280 1281 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 98U 1282 { 1283 TSENSE0_CLK, /* name */ 1284 1U, /* enable */ 1285 }, 1286 #endif 1287 1288 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 99U 1289 { 1290 WKPU0_CLK, /* name */ 1291 1U, /* enable */ 1292 }, 1293 #endif 1294 }; 1295 1296 1297 static const Clock_Ip_CmuConfigType Clock_Ip_CmuConfigurations_0[CLOCK_IP_CONFIGURED_CMUS_0_NO] = { 1298 1299 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U 1300 { 1301 FXOSC_CLK, /* Clock name associated to clock monitor. */ 1302 0U, /*Enable/disable clock monitor CMU_FC_0 */ 1303 ( /* IER for CMU_FC_0 */ 1304 CMU_FC_IER_FLLIE(0U) | 1305 CMU_FC_IER_FHHIE(0U) | 1306 CMU_FC_IER_FLLAIE(0U) | 1307 CMU_FC_IER_FHHAIE(0U) 1308 ), 1309 16000000U, 1310 { 1311 0U, /* Start index in register values array */ 1312 0U, /* End index in register values array */ 1313 }, 1314 }, 1315 #endif 1316 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U 1317 { 1318 CORE_CLK, /* Clock name associated to clock monitor. */ 1319 0U, /*Enable/disable clock monitor CMU_FC_3 */ 1320 ( /* IER for CMU_FC_3 */ 1321 CMU_FC_IER_FLLIE(0U) | 1322 CMU_FC_IER_FHHIE(0U) | 1323 CMU_FC_IER_FLLAIE(0U) | 1324 CMU_FC_IER_FHHAIE(0U) 1325 ), 1326 160000000U, 1327 { 1328 0U, /* Start index in register values array */ 1329 0U, /* End index in register values array */ 1330 }, 1331 }, 1332 #endif 1333 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U 1334 { 1335 AIPS_PLAT_CLK, /* Clock name associated to clock monitor. */ 1336 0U, /*Enable/disable clock monitor CMU_FC_4 */ 1337 ( /* IER for CMU_FC_4 */ 1338 CMU_FC_IER_FLLIE(0U) | 1339 CMU_FC_IER_FHHIE(0U) | 1340 CMU_FC_IER_FLLAIE(0U) | 1341 CMU_FC_IER_FHHAIE(0U) 1342 ), 1343 80000000U, 1344 { 1345 0U, /* Start index in register values array */ 1346 0U, /* End index in register values array */ 1347 }, 1348 }, 1349 #endif 1350 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U 1351 { 1352 HSE_CLK, /* Clock name associated to clock monitor. */ 1353 0U, /*Enable/disable clock monitor CMU_FC_5 */ 1354 ( /* IER for CMU_FC_5 */ 1355 CMU_FC_IER_FLLIE(0U) | 1356 CMU_FC_IER_FHHIE(0U) | 1357 CMU_FC_IER_FLLAIE(0U) | 1358 CMU_FC_IER_FHHAIE(0U) 1359 ), 1360 80000000U, 1361 { 1362 0U, /* Start index in register values array */ 1363 0U, /* End index in register values array */ 1364 }, 1365 }, 1366 #endif 1367 }; 1368 1369 1370 static const Clock_Ip_ConfiguredFrequencyType Clock_Ip_ConfiguredFrequencyConfigurations_0[CLOCK_IP_CONFIGURED_FREQUENCIES_0_NO] = { 1371 1372 { 1373 CLOCK_IS_OFF, 1374 0U, 1375 }, 1376 #if CLOCK_IP_CONFIGURED_FREQUENCIES_0_NO > 1U 1377 { 1378 FIRC_CLK, 1379 48000000U, 1380 }, 1381 #endif 1382 #if CLOCK_IP_CONFIGURED_FREQUENCIES_0_NO > 2U 1383 { 1384 FXOSC_CLK, 1385 16000000U, 1386 }, 1387 #endif 1388 #if CLOCK_IP_CONFIGURED_FREQUENCIES_0_NO > 3U 1389 { 1390 CORE_CLK, 1391 160000000U, 1392 }, 1393 #endif 1394 #if CLOCK_IP_CONFIGURED_FREQUENCIES_0_NO > 4U 1395 { 1396 AIPS_PLAT_CLK, 1397 80000000U, 1398 }, 1399 #endif 1400 #if CLOCK_IP_CONFIGURED_FREQUENCIES_0_NO > 5U 1401 { 1402 AIPS_SLOW_CLK, 1403 40000000U, 1404 }, 1405 #endif 1406 }; 1407 1408 static const Clock_Ip_SelectorConfigType Clock_Ip_SelectorConfigurations_1[CLOCK_IP_CONFIGURED_SELECTORS_1_NO] = { 1409 1410 #if CLOCK_IP_CONFIGURED_SELECTORS_1_NO > 0U 1411 { 1412 EMAC_RX_CLK, /* Clock name associated to selector */ 1413 EMAC_MII_RMII_TX_CLK, /* Name of the selected input source */ 1414 }, 1415 #endif 1416 1417 #if CLOCK_IP_CONFIGURED_SELECTORS_1_NO > 1U 1418 { 1419 EMAC_TS_CLK, /* Clock name associated to selector */ 1420 FIRC_CLK, /* Name of the selected input source */ 1421 }, 1422 #endif 1423 1424 #if CLOCK_IP_CONFIGURED_SELECTORS_1_NO > 2U 1425 { 1426 EMAC_TX_CLK, /* Clock name associated to selector */ 1427 EMAC_MII_RMII_TX_CLK, /* Name of the selected input source */ 1428 }, 1429 #endif 1430 }; 1431 1432 1433 static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_1[CLOCK_IP_CONFIGURED_DIVIDERS_1_NO] = { 1434 1435 #if CLOCK_IP_CONFIGURED_DIVIDERS_1_NO > 0U 1436 { 1437 EMAC_RX_CLK, /* name */ 1438 2U, /* value */ 1439 { 1440 0U, 1441 } 1442 }, 1443 #endif 1444 1445 #if CLOCK_IP_CONFIGURED_DIVIDERS_1_NO > 1U 1446 { 1447 EMAC_TS_CLK, /* name */ 1448 1U, /* value */ 1449 { 1450 0U, 1451 } 1452 }, 1453 #endif 1454 1455 #if CLOCK_IP_CONFIGURED_DIVIDERS_1_NO > 2U 1456 { 1457 EMAC_TX_CLK, /* name */ 1458 2U, /* value */ 1459 { 1460 0U, 1461 } 1462 }, 1463 #endif 1464 }; 1465 1466 1467 static const Clock_Ip_ExtClkConfigType Clock_Ip_ExtClkConfigurations_1[CLOCK_IP_CONFIGURED_EXT_CLKS_1_NO] = { 1468 1469 #if CLOCK_IP_CONFIGURED_EXT_CLKS_1_NO > 0U 1470 { 1471 EMAC_MII_RX_CLK, /* name */ 1472 0U, /* value */ 1473 }, 1474 #endif 1475 1476 #if CLOCK_IP_CONFIGURED_EXT_CLKS_1_NO > 1U 1477 { 1478 EMAC_MII_RMII_TX_CLK, /* name */ 1479 50000000U, /* value */ 1480 }, 1481 #endif 1482 }; 1483 1484 1485 static const Clock_Ip_GateConfigType Clock_Ip_GatesConfigurations_1[CLOCK_IP_CONFIGURED_GATES_1_NO] = { 1486 1487 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 0U 1488 { 1489 ADC0_CLK, /* name */ 1490 1U, /* enable */ 1491 }, 1492 #endif 1493 1494 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 1U 1495 { 1496 ADC1_CLK, /* name */ 1497 1U, /* enable */ 1498 }, 1499 #endif 1500 1501 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 2U 1502 { 1503 ADC2_CLK, /* name */ 1504 1U, /* enable */ 1505 }, 1506 #endif 1507 1508 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 3U 1509 { 1510 BCTU0_CLK, /* name */ 1511 1U, /* enable */ 1512 }, 1513 #endif 1514 1515 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 4U 1516 { 1517 CMP0_CLK, /* name */ 1518 1U, /* enable */ 1519 }, 1520 #endif 1521 1522 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 5U 1523 { 1524 CMP1_CLK, /* name */ 1525 1U, /* enable */ 1526 }, 1527 #endif 1528 1529 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 6U 1530 { 1531 CMP2_CLK, /* name */ 1532 1U, /* enable */ 1533 }, 1534 #endif 1535 1536 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 7U 1537 { 1538 CRC0_CLK, /* name */ 1539 1U, /* enable */ 1540 }, 1541 #endif 1542 1543 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 8U 1544 { 1545 DMAMUX0_CLK, /* name */ 1546 1U, /* enable */ 1547 }, 1548 #endif 1549 1550 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 9U 1551 { 1552 DMAMUX1_CLK, /* name */ 1553 1U, /* enable */ 1554 }, 1555 #endif 1556 1557 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 10U 1558 { 1559 EDMA0_CLK, /* name */ 1560 1U, /* enable */ 1561 }, 1562 #endif 1563 1564 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 11U 1565 { 1566 EDMA0_TCD0_CLK, /* name */ 1567 1U, /* enable */ 1568 }, 1569 #endif 1570 1571 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 12U 1572 { 1573 EDMA0_TCD1_CLK, /* name */ 1574 1U, /* enable */ 1575 }, 1576 #endif 1577 1578 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 13U 1579 { 1580 EDMA0_TCD2_CLK, /* name */ 1581 1U, /* enable */ 1582 }, 1583 #endif 1584 1585 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 14U 1586 { 1587 EDMA0_TCD3_CLK, /* name */ 1588 1U, /* enable */ 1589 }, 1590 #endif 1591 1592 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 15U 1593 { 1594 EDMA0_TCD4_CLK, /* name */ 1595 1U, /* enable */ 1596 }, 1597 #endif 1598 1599 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 16U 1600 { 1601 EDMA0_TCD5_CLK, /* name */ 1602 1U, /* enable */ 1603 }, 1604 #endif 1605 1606 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 17U 1607 { 1608 EDMA0_TCD6_CLK, /* name */ 1609 1U, /* enable */ 1610 }, 1611 #endif 1612 1613 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 18U 1614 { 1615 EDMA0_TCD7_CLK, /* name */ 1616 1U, /* enable */ 1617 }, 1618 #endif 1619 1620 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 19U 1621 { 1622 EDMA0_TCD8_CLK, /* name */ 1623 1U, /* enable */ 1624 }, 1625 #endif 1626 1627 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 20U 1628 { 1629 EDMA0_TCD9_CLK, /* name */ 1630 1U, /* enable */ 1631 }, 1632 #endif 1633 1634 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 21U 1635 { 1636 EDMA0_TCD10_CLK, /* name */ 1637 1U, /* enable */ 1638 }, 1639 #endif 1640 1641 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 22U 1642 { 1643 EDMA0_TCD11_CLK, /* name */ 1644 1U, /* enable */ 1645 }, 1646 #endif 1647 1648 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 23U 1649 { 1650 EDMA0_TCD12_CLK, /* name */ 1651 1U, /* enable */ 1652 }, 1653 #endif 1654 1655 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 24U 1656 { 1657 EDMA0_TCD13_CLK, /* name */ 1658 1U, /* enable */ 1659 }, 1660 #endif 1661 1662 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 25U 1663 { 1664 EDMA0_TCD14_CLK, /* name */ 1665 1U, /* enable */ 1666 }, 1667 #endif 1668 1669 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 26U 1670 { 1671 EDMA0_TCD15_CLK, /* name */ 1672 1U, /* enable */ 1673 }, 1674 #endif 1675 1676 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 27U 1677 { 1678 EDMA0_TCD16_CLK, /* name */ 1679 1U, /* enable */ 1680 }, 1681 #endif 1682 1683 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 28U 1684 { 1685 EDMA0_TCD17_CLK, /* name */ 1686 1U, /* enable */ 1687 }, 1688 #endif 1689 1690 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 29U 1691 { 1692 EDMA0_TCD18_CLK, /* name */ 1693 1U, /* enable */ 1694 }, 1695 #endif 1696 1697 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 30U 1698 { 1699 EDMA0_TCD19_CLK, /* name */ 1700 1U, /* enable */ 1701 }, 1702 #endif 1703 1704 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 31U 1705 { 1706 EDMA0_TCD20_CLK, /* name */ 1707 1U, /* enable */ 1708 }, 1709 #endif 1710 1711 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 32U 1712 { 1713 EDMA0_TCD21_CLK, /* name */ 1714 1U, /* enable */ 1715 }, 1716 #endif 1717 1718 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 33U 1719 { 1720 EDMA0_TCD22_CLK, /* name */ 1721 1U, /* enable */ 1722 }, 1723 #endif 1724 1725 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 34U 1726 { 1727 EDMA0_TCD23_CLK, /* name */ 1728 1U, /* enable */ 1729 }, 1730 #endif 1731 1732 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 35U 1733 { 1734 EDMA0_TCD24_CLK, /* name */ 1735 1U, /* enable */ 1736 }, 1737 #endif 1738 1739 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 36U 1740 { 1741 EDMA0_TCD25_CLK, /* name */ 1742 1U, /* enable */ 1743 }, 1744 #endif 1745 1746 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 37U 1747 { 1748 EDMA0_TCD26_CLK, /* name */ 1749 1U, /* enable */ 1750 }, 1751 #endif 1752 1753 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 38U 1754 { 1755 EDMA0_TCD27_CLK, /* name */ 1756 1U, /* enable */ 1757 }, 1758 #endif 1759 1760 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 39U 1761 { 1762 EDMA0_TCD28_CLK, /* name */ 1763 1U, /* enable */ 1764 }, 1765 #endif 1766 1767 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 40U 1768 { 1769 EDMA0_TCD29_CLK, /* name */ 1770 1U, /* enable */ 1771 }, 1772 #endif 1773 1774 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 41U 1775 { 1776 EDMA0_TCD30_CLK, /* name */ 1777 1U, /* enable */ 1778 }, 1779 #endif 1780 1781 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 42U 1782 { 1783 EDMA0_TCD31_CLK, /* name */ 1784 1U, /* enable */ 1785 }, 1786 #endif 1787 1788 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 43U 1789 { 1790 EIM_CLK, /* name */ 1791 1U, /* enable */ 1792 }, 1793 #endif 1794 1795 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 44U 1796 { 1797 EMAC0_RX_CLK, /* name */ 1798 1U, /* enable */ 1799 }, 1800 #endif 1801 1802 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 45U 1803 { 1804 EMIOS0_CLK, /* name */ 1805 1U, /* enable */ 1806 }, 1807 #endif 1808 1809 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 46U 1810 { 1811 EMIOS1_CLK, /* name */ 1812 1U, /* enable */ 1813 }, 1814 #endif 1815 1816 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 47U 1817 { 1818 EMIOS2_CLK, /* name */ 1819 1U, /* enable */ 1820 }, 1821 #endif 1822 1823 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 48U 1824 { 1825 ERM0_CLK, /* name */ 1826 1U, /* enable */ 1827 }, 1828 #endif 1829 1830 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 49U 1831 { 1832 FLEXCAN0_CLK, /* name */ 1833 1U, /* enable */ 1834 }, 1835 #endif 1836 1837 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 50U 1838 { 1839 FLEXCAN1_CLK, /* name */ 1840 1U, /* enable */ 1841 }, 1842 #endif 1843 1844 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 51U 1845 { 1846 FLEXCAN2_CLK, /* name */ 1847 1U, /* enable */ 1848 }, 1849 #endif 1850 1851 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 52U 1852 { 1853 FLEXCAN3_CLK, /* name */ 1854 1U, /* enable */ 1855 }, 1856 #endif 1857 1858 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 53U 1859 { 1860 FLEXCAN4_CLK, /* name */ 1861 1U, /* enable */ 1862 }, 1863 #endif 1864 1865 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 54U 1866 { 1867 FLEXCAN5_CLK, /* name */ 1868 1U, /* enable */ 1869 }, 1870 #endif 1871 1872 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 55U 1873 { 1874 FLEXIO0_CLK, /* name */ 1875 1U, /* enable */ 1876 }, 1877 #endif 1878 1879 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 56U 1880 { 1881 INTM_CLK, /* name */ 1882 1U, /* enable */ 1883 }, 1884 #endif 1885 1886 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 57U 1887 { 1888 LCU0_CLK, /* name */ 1889 1U, /* enable */ 1890 }, 1891 #endif 1892 1893 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 58U 1894 { 1895 LCU1_CLK, /* name */ 1896 1U, /* enable */ 1897 }, 1898 #endif 1899 1900 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 59U 1901 { 1902 LPI2C0_CLK, /* name */ 1903 1U, /* enable */ 1904 }, 1905 #endif 1906 1907 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 60U 1908 { 1909 LPI2C1_CLK, /* name */ 1910 1U, /* enable */ 1911 }, 1912 #endif 1913 1914 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 61U 1915 { 1916 LPSPI0_CLK, /* name */ 1917 1U, /* enable */ 1918 }, 1919 #endif 1920 1921 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 62U 1922 { 1923 LPSPI1_CLK, /* name */ 1924 1U, /* enable */ 1925 }, 1926 #endif 1927 1928 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 63U 1929 { 1930 LPSPI2_CLK, /* name */ 1931 1U, /* enable */ 1932 }, 1933 #endif 1934 1935 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 64U 1936 { 1937 LPSPI3_CLK, /* name */ 1938 1U, /* enable */ 1939 }, 1940 #endif 1941 1942 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 65U 1943 { 1944 LPSPI4_CLK, /* name */ 1945 1U, /* enable */ 1946 }, 1947 #endif 1948 1949 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 66U 1950 { 1951 LPSPI5_CLK, /* name */ 1952 1U, /* enable */ 1953 }, 1954 #endif 1955 1956 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 67U 1957 { 1958 LPUART0_CLK, /* name */ 1959 1U, /* enable */ 1960 }, 1961 #endif 1962 1963 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 68U 1964 { 1965 LPUART1_CLK, /* name */ 1966 1U, /* enable */ 1967 }, 1968 #endif 1969 1970 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 69U 1971 { 1972 LPUART2_CLK, /* name */ 1973 1U, /* enable */ 1974 }, 1975 #endif 1976 1977 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 70U 1978 { 1979 LPUART3_CLK, /* name */ 1980 1U, /* enable */ 1981 }, 1982 #endif 1983 1984 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 71U 1985 { 1986 LPUART4_CLK, /* name */ 1987 1U, /* enable */ 1988 }, 1989 #endif 1990 1991 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 72U 1992 { 1993 LPUART5_CLK, /* name */ 1994 1U, /* enable */ 1995 }, 1996 #endif 1997 1998 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 73U 1999 { 2000 LPUART6_CLK, /* name */ 2001 1U, /* enable */ 2002 }, 2003 #endif 2004 2005 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 74U 2006 { 2007 LPUART7_CLK, /* name */ 2008 1U, /* enable */ 2009 }, 2010 #endif 2011 2012 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 75U 2013 { 2014 LPUART8_CLK, /* name */ 2015 1U, /* enable */ 2016 }, 2017 #endif 2018 2019 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 76U 2020 { 2021 LPUART9_CLK, /* name */ 2022 1U, /* enable */ 2023 }, 2024 #endif 2025 2026 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 77U 2027 { 2028 LPUART10_CLK, /* name */ 2029 1U, /* enable */ 2030 }, 2031 #endif 2032 2033 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 78U 2034 { 2035 LPUART11_CLK, /* name */ 2036 1U, /* enable */ 2037 }, 2038 #endif 2039 2040 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 79U 2041 { 2042 LPUART12_CLK, /* name */ 2043 1U, /* enable */ 2044 }, 2045 #endif 2046 2047 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 80U 2048 { 2049 LPUART13_CLK, /* name */ 2050 1U, /* enable */ 2051 }, 2052 #endif 2053 2054 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 81U 2055 { 2056 LPUART14_CLK, /* name */ 2057 1U, /* enable */ 2058 }, 2059 #endif 2060 2061 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 82U 2062 { 2063 LPUART15_CLK, /* name */ 2064 1U, /* enable */ 2065 }, 2066 #endif 2067 2068 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 83U 2069 { 2070 MSCM_CLK, /* name */ 2071 1U, /* enable */ 2072 }, 2073 #endif 2074 2075 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 84U 2076 { 2077 PIT0_CLK, /* name */ 2078 1U, /* enable */ 2079 }, 2080 #endif 2081 2082 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 85U 2083 { 2084 PIT1_CLK, /* name */ 2085 1U, /* enable */ 2086 }, 2087 #endif 2088 2089 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 86U 2090 { 2091 PIT2_CLK, /* name */ 2092 1U, /* enable */ 2093 }, 2094 #endif 2095 2096 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 87U 2097 { 2098 QSPI0_RAM_CLK, /* name */ 2099 1U, /* enable */ 2100 }, 2101 #endif 2102 2103 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 88U 2104 { 2105 RTC0_CLK, /* name */ 2106 1U, /* enable */ 2107 }, 2108 #endif 2109 2110 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 89U 2111 { 2112 SAI0_CLK, /* name */ 2113 1U, /* enable */ 2114 }, 2115 #endif 2116 2117 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 90U 2118 { 2119 SAI1_CLK, /* name */ 2120 1U, /* enable */ 2121 }, 2122 #endif 2123 2124 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 91U 2125 { 2126 SEMA42_CLK, /* name */ 2127 1U, /* enable */ 2128 }, 2129 #endif 2130 2131 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 92U 2132 { 2133 SIUL2_CLK, /* name */ 2134 1U, /* enable */ 2135 }, 2136 #endif 2137 2138 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 93U 2139 { 2140 STM0_CLK, /* name */ 2141 1U, /* enable */ 2142 }, 2143 #endif 2144 2145 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 94U 2146 { 2147 STM1_CLK, /* name */ 2148 1U, /* enable */ 2149 }, 2150 #endif 2151 2152 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 95U 2153 { 2154 SWT0_CLK, /* name */ 2155 1U, /* enable */ 2156 }, 2157 #endif 2158 2159 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 96U 2160 { 2161 TEMPSENSE_CLK, /* name */ 2162 1U, /* enable */ 2163 }, 2164 #endif 2165 2166 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 97U 2167 { 2168 TRGMUX0_CLK, /* name */ 2169 1U, /* enable */ 2170 }, 2171 #endif 2172 2173 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 98U 2174 { 2175 TSENSE0_CLK, /* name */ 2176 1U, /* enable */ 2177 }, 2178 #endif 2179 2180 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 99U 2181 { 2182 WKPU0_CLK, /* name */ 2183 1U, /* enable */ 2184 }, 2185 #endif 2186 }; 2187 2188 2189 static const Clock_Ip_CmuConfigType Clock_Ip_CmuConfigurations_1[CLOCK_IP_CONFIGURED_CMUS_1_NO] = { 2190 2191 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U 2192 { 2193 FXOSC_CLK, /* Clock name associated to clock monitor. */ 2194 0U, /*Enable/disable clock monitor CMU_FC_0 */ 2195 ( /* IER for CMU_FC_0 */ 2196 CMU_FC_IER_FLLIE(0U) | 2197 CMU_FC_IER_FHHIE(0U) | 2198 CMU_FC_IER_FLLAIE(0U) | 2199 CMU_FC_IER_FHHAIE(0U) 2200 ), 2201 16000000U, 2202 { 2203 0U, /* Start index in register values array */ 2204 0U, /* End index in register values array */ 2205 }, 2206 }, 2207 #endif 2208 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U 2209 { 2210 CORE_CLK, /* Clock name associated to clock monitor. */ 2211 0U, /*Enable/disable clock monitor CMU_FC_3 */ 2212 ( /* IER for CMU_FC_3 */ 2213 CMU_FC_IER_FLLIE(0U) | 2214 CMU_FC_IER_FHHIE(0U) | 2215 CMU_FC_IER_FLLAIE(0U) | 2216 CMU_FC_IER_FHHAIE(0U) 2217 ), 2218 160000000U, 2219 { 2220 0U, /* Start index in register values array */ 2221 0U, /* End index in register values array */ 2222 }, 2223 }, 2224 #endif 2225 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U 2226 { 2227 AIPS_PLAT_CLK, /* Clock name associated to clock monitor. */ 2228 0U, /*Enable/disable clock monitor CMU_FC_4 */ 2229 ( /* IER for CMU_FC_4 */ 2230 CMU_FC_IER_FLLIE(0U) | 2231 CMU_FC_IER_FHHIE(0U) | 2232 CMU_FC_IER_FLLAIE(0U) | 2233 CMU_FC_IER_FHHAIE(0U) 2234 ), 2235 80000000U, 2236 { 2237 0U, /* Start index in register values array */ 2238 0U, /* End index in register values array */ 2239 }, 2240 }, 2241 #endif 2242 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U 2243 { 2244 HSE_CLK, /* Clock name associated to clock monitor. */ 2245 0U, /*Enable/disable clock monitor CMU_FC_5 */ 2246 ( /* IER for CMU_FC_5 */ 2247 CMU_FC_IER_FLLIE(0U) | 2248 CMU_FC_IER_FHHIE(0U) | 2249 CMU_FC_IER_FLLAIE(0U) | 2250 CMU_FC_IER_FHHAIE(0U) 2251 ), 2252 80000000U, 2253 { 2254 0U, /* Start index in register values array */ 2255 0U, /* End index in register values array */ 2256 }, 2257 }, 2258 #endif 2259 }; 2260 2261 2262 static const Clock_Ip_ConfiguredFrequencyType Clock_Ip_ConfiguredFrequencyConfigurations_1[CLOCK_IP_CONFIGURED_FREQUENCIES_1_NO] = { 2263 2264 { 2265 CLOCK_IS_OFF, 2266 0U, 2267 }, 2268 #if CLOCK_IP_CONFIGURED_FREQUENCIES_1_NO > 1U 2269 { 2270 FIRC_CLK, 2271 48000000U, 2272 }, 2273 #endif 2274 #if CLOCK_IP_CONFIGURED_FREQUENCIES_1_NO > 2U 2275 { 2276 FXOSC_CLK, 2277 16000000U, 2278 }, 2279 #endif 2280 #if CLOCK_IP_CONFIGURED_FREQUENCIES_1_NO > 3U 2281 { 2282 CORE_CLK, 2283 160000000U, 2284 }, 2285 #endif 2286 #if CLOCK_IP_CONFIGURED_FREQUENCIES_1_NO > 4U 2287 { 2288 AIPS_PLAT_CLK, 2289 80000000U, 2290 }, 2291 #endif 2292 #if CLOCK_IP_CONFIGURED_FREQUENCIES_1_NO > 5U 2293 { 2294 AIPS_SLOW_CLK, 2295 40000000U, 2296 }, 2297 #endif 2298 }; 2299 2300 2301 /* ************************************************************************* 2302 * Configuration structure for Clock Configuration 2303 * ************************************************************************* */ 2304 const Clock_Ip_ClockConfigType Clock_Ip_aClockConfig[2U] = { 2305 2306 /*! @brief User Configuration structure clock_Cfg_0 */ 2307 2308 { 2309 0U, /* clkConfigId */ 2310 (NULL_PTR), /* Register data if register value optimization is enabled */ 2311 2312 3U, /* ircoscsCount */ 2313 2U, /* xoscsCount */ 2314 1U, /* pllsCount */ 2315 13U, /* selectorsCount */ 2316 21U, /* dividersCount */ 2317 1U, /* dividerTriggersCount */ 2318 0U, /* fracDivsCount */ 2319 2U, /* extClksCount */ 2320 100U, /* gatesCount */ 2321 0U, /* pcfsCount */ 2322 4U, /* cmusCount */ 2323 6U, /* configureFrequenciesCount */ 2324 2325 (&Clock_Ip_IrcoscConfigurations_0), /* Ircosc configurations */ 2326 (&Clock_Ip_XoscConfigurations_0), /* Xosc configurations */ 2327 (&Clock_Ip_PllConfigurations_0), /* Pll configurations */ 2328 (&Clock_Ip_SelectorConfigurations_0), /* Selectors configurations */ 2329 (&Clock_Ip_DividerConfigurations_0), /* dividers configurations */ 2330 (&Clock_Ip_DividerTriggerConfigurations_0), /* dividerTriggers configurations */ 2331 (NULL_PTR), /* fracDivs configurations */ 2332 (&Clock_Ip_ExtClkConfigurations_0), /* extClks configurations */ 2333 (&Clock_Ip_GatesConfigurations_0), /* gates configurations */ 2334 (NULL_PTR), /* pcfs configurations */ 2335 (&Clock_Ip_CmuConfigurations_0), /* cmus configurations */ 2336 (&Clock_Ip_ConfiguredFrequencyConfigurations_0), /* configureFrequencies configurations */ 2337 }, 2338 2339 /*! @brief User Configuration structure clock_Cfg_1 */ 2340 2341 { 2342 1U, /* clkConfigId */ 2343 (NULL_PTR), /* Register data if register value optimization is enabled */ 2344 2345 0U, /* ircoscsCount */ 2346 0U, /* xoscsCount */ 2347 0U, /* pllsCount */ 2348 3U, /* selectorsCount */ 2349 3U, /* dividersCount */ 2350 0U, /* dividerTriggersCount */ 2351 0U, /* fracDivsCount */ 2352 2U, /* extClksCount */ 2353 100U, /* gatesCount */ 2354 0U, /* pcfsCount */ 2355 4U, /* cmusCount */ 2356 6U, /* configureFrequenciesCount */ 2357 2358 (NULL_PTR), /* Ircosc configurations */ 2359 (NULL_PTR), /* Xosc configurations */ 2360 (NULL_PTR), /* Pll configurations */ 2361 (&Clock_Ip_SelectorConfigurations_1), /* Selectors configurations */ 2362 (&Clock_Ip_DividerConfigurations_1), /* dividers configurations */ 2363 (NULL_PTR), /* dividerTriggers configurations */ 2364 (NULL_PTR), /* fracDivs configurations */ 2365 (&Clock_Ip_ExtClkConfigurations_1), /* extClks configurations */ 2366 (&Clock_Ip_GatesConfigurations_1), /* gates configurations */ 2367 (NULL_PTR), /* pcfs configurations */ 2368 (&Clock_Ip_CmuConfigurations_1), /* cmus configurations */ 2369 (&Clock_Ip_ConfiguredFrequencyConfigurations_1), /* configureFrequencies configurations */ 2370 }, 2371 }; 2372 2373 2374 #define MCU_STOP_SEC_CONFIG_DATA_UNSPECIFIED 2375 #include "Mcu_MemMap.h" 2376 2377 2378 /*================================================================================================== 2379 LOCAL FUNCTION PROTOTYPES 2380 ==================================================================================================*/ 2381 2382 /*================================================================================================== 2383 LOCAL FUNCTIONS 2384 ==================================================================================================*/ 2385 2386 /*================================================================================================== 2387 GLOBAL FUNCTIONS 2388 ==================================================================================================*/ 2389 2390 #ifdef __cplusplus 2391 } 2392 #endif 2393 2394 /** @} */ 2395
