1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /** 8 * @file Clock_Ip_Cfg.c 9 * @version 2.0.0 10 * 11 * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. 12 * @details Code template for Post-Build(PB) configuration file generation. 13 * 14 * @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver 15 * @{ 16 */ 17 18 19 #ifdef __cplusplus 20 extern "C"{ 21 #endif 22 23 24 /*================================================================================================== 25 INCLUDE FILES 26 1) system and project includes 27 2) needed interfaces from external units 28 3) internal and external interfaces from this unit 29 ==================================================================================================*/ 30 #include "StandardTypes.h" 31 #include "Clock_Ip_Private.h" 32 33 /*================================================================================================== 34 * SOURCE FILE VERSION INFORMATION 35 ==================================================================================================*/ 36 #define CLOCK_IP_CFG_VENDOR_ID_C 43 37 #define CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C 4 38 #define CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C 7 39 #define CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C 0 40 #define CLOCK_IP_CFG_SW_MAJOR_VERSION_C 2 41 #define CLOCK_IP_CFG_SW_MINOR_VERSION_C 0 42 #define CLOCK_IP_CFG_SW_PATCH_VERSION_C 0 43 44 /*================================================================================================== 45 * FILE VERSION CHECKS 46 ==================================================================================================*/ 47 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 48 /* Check if source file and StandardTypes.h file are of the same Autosar version */ 49 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != STD_AR_RELEASE_MAJOR_VERSION) || \ 50 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != STD_AR_RELEASE_MINOR_VERSION) \ 51 ) 52 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and StandardTypes.h are different" 53 #endif 54 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */ 55 /* Check if source file and Clock_Ip_Private.h file are of the same vendor */ 56 #if (CLOCK_IP_CFG_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID) 57 #error "Clock_Ip_Cfg.c and Clock_Ip_Private.h have different vendor ids" 58 #endif 59 60 /* Check if source file and Clock_Ip_Private.h file are of the same Autosar version */ 61 #if ((CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \ 62 (CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \ 63 (CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \ 64 ) 65 #error "AutoSar Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Private.h are different" 66 #endif 67 68 /* Check if source file and Clock_Ip_Private.h file are of the same Software version */ 69 #if ((CLOCK_IP_CFG_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \ 70 (CLOCK_IP_CFG_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \ 71 (CLOCK_IP_CFG_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \ 72 ) 73 #error "Software Version Numbers of Clock_Ip_Cfg.c and Clock_Ip_Private.h are different" 74 #endif 75 76 /*================================================================================================== 77 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) 78 ==================================================================================================*/ 79 80 /*================================================================================================== 81 LOCAL MACROS 82 ==================================================================================================*/ 83 84 /*================================================================================================== 85 LOCAL CONSTANTS 86 ==================================================================================================*/ 87 88 /*================================================================================================== 89 LOCAL VARIABLES 90 ==================================================================================================*/ 91 92 /*================================================================================================== 93 GLOBAL CONSTANTS 94 ==================================================================================================*/ 95 96 /*================================================================================================== 97 GLOBAL VARIABLES 98 ==================================================================================================*/ 99 100 101 #define MCU_START_SEC_CONFIG_DATA_UNSPECIFIED 102 #include "Mcu_MemMap.h" 103 104 105 /* ************************************************************************* 106 * Configuration structure for Clock Configuration 107 * ************************************************************************* */ 108 const Clock_Ip_ClockConfigType Clock_Ip_aClockConfig[1U] = { 109 110 { 111 0U, /* clkConfigId */ 112 113 (NULL_PTR), /* Register data if register value optimization is enabled */ 114 2U, /* ircoscsCount */ 115 1U, /* xoscsCount */ 116 1U, /* pllsCount */ 117 32U, /* selectorsCount */ 118 20U, /* dividersCount */ 119 0U, /* dividerTriggersCount */ 120 0U, /* fracDivsCount */ 121 4U, /* extClksCount */ 122 43U, /* gatesCount */ 123 0U, /* pcfsCount */ 124 0U, /* cmusCount */ 125 1U, /* configureFrequenciesCount */ 126 127 128 /* IRCOSC initialization. */ 129 { 130 131 #if CLOCK_IP_IRCOSCS_NO > 0U 132 { 133 SIRC_CLK, /* name */ 134 1U, /* Enabled ircosc */ 135 0U, /* Enabled regulator */ 136 1U, /* Ircosc range */ 137 1U, /* Ircosc enable in VLP mode */ 138 0U, /* Ircosc disable in STOP mode */ 139 }, 140 #endif 141 142 #if CLOCK_IP_IRCOSCS_NO > 1U 143 { 144 FIRC_CLK, /* name */ 145 1U, /* Enabled ircosc */ 146 0U, /* Enabled regulator */ 147 0U, /* Ircosc range */ 148 0U, /* Ircosc disable in VLP mode */ 149 0U, /* Ircosc disable in STOP mode */ 150 }, 151 #endif 152 }, 153 154 /* XOSC initialization. */ 155 156 { 157 158 #if CLOCK_IP_XOSCS_NO > 0U 159 { 160 SOSC_CLK, /* Clock name associated to xosc */ 161 8000000U, /* External oscillator frequency */ 162 1U, /* Enable xosc */ 163 0U, /* Startup stabilization time */ 164 0U, /* XOSC bypass option */ 165 0U, /* Comparator is not enabled */ 166 0U, /* Crystal overdrive protection */ 167 0U, /* High gain value */ 168 CLOCK_IP_HAS_MONITOR_DISABLE, /* Monitor type */ 169 0U, /* Automatic level controller */ 170 }, 171 #endif 172 }, 173 174 175 /* PLL initialization. */ 176 { 177 178 #if CLOCK_IP_PLLS_NO > 0U 179 { 180 SPLL_CLK, /* name */ 181 1U, /* enable */ 182 SOSC_CLK, /* inputReference */ 183 0U, /* Bypass */ 184 1U, /* predivider */ 185 0U, /* multiplier */ 186 0U, /* postdivider */ 187 0U, /* numeratorFracLoopDiv */ 188 40U, /* mulFactorDiv */ 189 0U, /* ModulationBypass */ 190 0U, /* Modulation type: Spread spectrum modulation bypassed */ 191 0U, /* modulationPeriod */ 192 1U, /* incrementStep */ 193 0U, /* sigmaDelta */ 194 0U, /* ditherControl */ 195 0U, /* ditherControlValue */ 196 CLOCK_IP_HAS_MONITOR_DISABLE, /* Monitor type */ 197 { /* Dividers */ 198 0U, 199 0U, 200 0U, 201 }, 202 }, 203 #endif 204 }, 205 206 207 208 /* SELECTOR initialization. */ 209 { 210 211 #if CLOCK_IP_SELECTORS_NO > 0U 212 { 213 SCS_RUN_CLK, /* Clock name associated to selector */ 214 SPLL_CLK, /* Name of the selected input source */ 215 }, 216 #endif 217 218 #if CLOCK_IP_SELECTORS_NO > 1U 219 { 220 SCS_VLPR_CLK, /* Clock name associated to selector */ 221 SIRC_CLK, /* Name of the selected input source */ 222 }, 223 #endif 224 225 #if CLOCK_IP_SELECTORS_NO > 2U 226 { 227 SCS_HSRUN_CLK, /* Clock name associated to selector */ 228 FIRC_CLK, /* Name of the selected input source */ 229 }, 230 #endif 231 232 #if CLOCK_IP_SELECTORS_NO > 3U 233 { 234 SCG_CLKOUT_CLK, /* Clock name associated to selector */ 235 SPLL_CLK, /* Name of the selected input source */ 236 }, 237 #endif 238 239 #if CLOCK_IP_SELECTORS_NO > 4U 240 { 241 RTC_CLK, /* Clock name associated to selector */ 242 LPO_32K_CLK, /* Name of the selected input source */ 243 }, 244 #endif 245 246 #if CLOCK_IP_SELECTORS_NO > 5U 247 { 248 LPO_CLK, /* Clock name associated to selector */ 249 LPO_128K_CLK, /* Name of the selected input source */ 250 }, 251 #endif 252 253 #if CLOCK_IP_SELECTORS_NO > 6U 254 { 255 TRACE_CLK, /* Clock name associated to selector */ 256 CORE_CLK, /* Name of the selected input source */ 257 }, 258 #endif 259 260 #if CLOCK_IP_SELECTORS_NO > 7U 261 { 262 CLKOUT0_CLK, /* Clock name associated to selector */ 263 HCLK, /* Name of the selected input source */ 264 }, 265 #endif 266 267 #if CLOCK_IP_SELECTORS_NO > 8U 268 { 269 FTM0_EXT_CLK, /* Clock name associated to selector */ 270 TCLK0_REF_CLK, /* Name of the selected input source */ 271 }, 272 #endif 273 274 #if CLOCK_IP_SELECTORS_NO > 9U 275 { 276 FTM1_EXT_CLK, /* Clock name associated to selector */ 277 TCLK0_REF_CLK, /* Name of the selected input source */ 278 }, 279 #endif 280 281 #if CLOCK_IP_SELECTORS_NO > 10U 282 { 283 FTM2_EXT_CLK, /* Clock name associated to selector */ 284 TCLK0_REF_CLK, /* Name of the selected input source */ 285 }, 286 #endif 287 288 #if CLOCK_IP_SELECTORS_NO > 11U 289 { 290 FTM3_EXT_CLK, /* Clock name associated to selector */ 291 TCLK0_REF_CLK, /* Name of the selected input source */ 292 }, 293 #endif 294 295 #if CLOCK_IP_SELECTORS_NO > 12U 296 { 297 FTM4_EXT_CLK, /* Clock name associated to selector */ 298 TCLK0_REF_CLK, /* Name of the selected input source */ 299 }, 300 #endif 301 302 #if CLOCK_IP_SELECTORS_NO > 13U 303 { 304 FTM5_EXT_CLK, /* Clock name associated to selector */ 305 TCLK0_REF_CLK, /* Name of the selected input source */ 306 }, 307 #endif 308 309 #if CLOCK_IP_SELECTORS_NO > 14U 310 { 311 FTM0_CLK, /* Clock name associated to selector */ 312 SPLLDIV1_CLK, /* Name of the selected input source */ 313 }, 314 #endif 315 316 #if CLOCK_IP_SELECTORS_NO > 15U 317 { 318 FTM1_CLK, /* Clock name associated to selector */ 319 SPLLDIV1_CLK, /* Name of the selected input source */ 320 }, 321 #endif 322 323 #if CLOCK_IP_SELECTORS_NO > 16U 324 { 325 FTM2_CLK, /* Clock name associated to selector */ 326 SPLLDIV1_CLK, /* Name of the selected input source */ 327 }, 328 #endif 329 330 #if CLOCK_IP_SELECTORS_NO > 17U 331 { 332 FTM3_CLK, /* Clock name associated to selector */ 333 SPLLDIV1_CLK, /* Name of the selected input source */ 334 }, 335 #endif 336 337 #if CLOCK_IP_SELECTORS_NO > 18U 338 { 339 FTM4_CLK, /* Clock name associated to selector */ 340 SPLLDIV1_CLK, /* Name of the selected input source */ 341 }, 342 #endif 343 344 #if CLOCK_IP_SELECTORS_NO > 19U 345 { 346 FTM5_CLK, /* Clock name associated to selector */ 347 SPLLDIV1_CLK, /* Name of the selected input source */ 348 }, 349 #endif 350 351 #if CLOCK_IP_SELECTORS_NO > 20U 352 { 353 ADC1_CLK, /* Clock name associated to selector */ 354 SPLLDIV2_CLK, /* Name of the selected input source */ 355 }, 356 #endif 357 358 #if CLOCK_IP_SELECTORS_NO > 21U 359 { 360 LPSPI0_CLK, /* Clock name associated to selector */ 361 SPLLDIV2_CLK, /* Name of the selected input source */ 362 }, 363 #endif 364 365 #if CLOCK_IP_SELECTORS_NO > 22U 366 { 367 LPSPI1_CLK, /* Clock name associated to selector */ 368 SPLLDIV2_CLK, /* Name of the selected input source */ 369 }, 370 #endif 371 372 #if CLOCK_IP_SELECTORS_NO > 23U 373 { 374 LPSPI2_CLK, /* Clock name associated to selector */ 375 SPLLDIV2_CLK, /* Name of the selected input source */ 376 }, 377 #endif 378 379 #if CLOCK_IP_SELECTORS_NO > 24U 380 { 381 LPIT0_CLK, /* Clock name associated to selector */ 382 SPLLDIV2_CLK, /* Name of the selected input source */ 383 }, 384 #endif 385 386 #if CLOCK_IP_SELECTORS_NO > 25U 387 { 388 ADC0_CLK, /* Clock name associated to selector */ 389 SPLLDIV2_CLK, /* Name of the selected input source */ 390 }, 391 #endif 392 393 #if CLOCK_IP_SELECTORS_NO > 26U 394 { 395 FlexIO_CLK, /* Clock name associated to selector */ 396 SPLLDIV2_CLK, /* Name of the selected input source */ 397 }, 398 #endif 399 400 #if CLOCK_IP_SELECTORS_NO > 27U 401 { 402 LPI2C0_CLK, /* Clock name associated to selector */ 403 SPLLDIV2_CLK, /* Name of the selected input source */ 404 }, 405 #endif 406 407 #if CLOCK_IP_SELECTORS_NO > 28U 408 { 409 LPUART0_CLK, /* Clock name associated to selector */ 410 SPLLDIV2_CLK, /* Name of the selected input source */ 411 }, 412 #endif 413 414 #if CLOCK_IP_SELECTORS_NO > 29U 415 { 416 LPUART1_CLK, /* Clock name associated to selector */ 417 SPLLDIV2_CLK, /* Name of the selected input source */ 418 }, 419 #endif 420 421 #if CLOCK_IP_SELECTORS_NO > 30U 422 { 423 LPUART2_CLK, /* Clock name associated to selector */ 424 SPLLDIV2_CLK, /* Name of the selected input source */ 425 }, 426 #endif 427 428 #if CLOCK_IP_SELECTORS_NO > 31U 429 { 430 LPTMR0_CLK, /* Clock name associated to selector */ 431 SPLLDIV2_CLK, /* Name of the selected input source */ 432 }, 433 #endif 434 }, 435 436 437 /* DIVIDER initialization. */ 438 439 { 440 441 #if CLOCK_IP_DIVIDERS_NO > 0U 442 { 443 SIRCDIV1_CLK, /* name */ 444 1U, /* value */ 445 { 446 0U, 447 } 448 }, 449 #endif 450 451 #if CLOCK_IP_DIVIDERS_NO > 1U 452 { 453 SIRCDIV2_CLK, /* name */ 454 1U, /* value */ 455 { 456 0U, 457 } 458 }, 459 #endif 460 461 #if CLOCK_IP_DIVIDERS_NO > 2U 462 { 463 FIRCDIV1_CLK, /* name */ 464 1U, /* value */ 465 { 466 0U, 467 } 468 }, 469 #endif 470 471 #if CLOCK_IP_DIVIDERS_NO > 3U 472 { 473 FIRCDIV2_CLK, /* name */ 474 1U, /* value */ 475 { 476 0U, 477 } 478 }, 479 #endif 480 481 #if CLOCK_IP_DIVIDERS_NO > 4U 482 { 483 SOSCDIV1_CLK, /* name */ 484 1U, /* value */ 485 { 486 0U, 487 } 488 }, 489 #endif 490 491 #if CLOCK_IP_DIVIDERS_NO > 5U 492 { 493 SOSCDIV2_CLK, /* name */ 494 1U, /* value */ 495 { 496 0U, 497 } 498 }, 499 #endif 500 501 #if CLOCK_IP_DIVIDERS_NO > 6U 502 { 503 SPLLDIV1_CLK, /* name */ 504 2U, /* value */ 505 { 506 0U, 507 } 508 }, 509 #endif 510 511 #if CLOCK_IP_DIVIDERS_NO > 7U 512 { 513 SPLLDIV2_CLK, /* name */ 514 4U, /* value */ 515 { 516 0U, 517 } 518 }, 519 #endif 520 521 #if CLOCK_IP_DIVIDERS_NO > 8U 522 { 523 CORE_RUN_CLK, /* name */ 524 2U, /* value */ 525 { 526 0U, 527 } 528 }, 529 #endif 530 531 #if CLOCK_IP_DIVIDERS_NO > 9U 532 { 533 CORE_VLPR_CLK, /* name */ 534 8U, /* value */ 535 { 536 0U, 537 } 538 }, 539 #endif 540 541 #if CLOCK_IP_DIVIDERS_NO > 10U 542 { 543 CORE_HSRUN_CLK, /* name */ 544 1U, /* value */ 545 { 546 0U, 547 } 548 }, 549 #endif 550 551 #if CLOCK_IP_DIVIDERS_NO > 11U 552 { 553 BUS_RUN_CLK, /* name */ 554 2U, /* value */ 555 { 556 0U, 557 } 558 }, 559 #endif 560 561 #if CLOCK_IP_DIVIDERS_NO > 12U 562 { 563 BUS_VLPR_CLK, /* name */ 564 1U, /* value */ 565 { 566 0U, 567 } 568 }, 569 #endif 570 571 #if CLOCK_IP_DIVIDERS_NO > 13U 572 { 573 BUS_HSRUN_CLK, /* name */ 574 1U, /* value */ 575 { 576 0U, 577 } 578 }, 579 #endif 580 581 #if CLOCK_IP_DIVIDERS_NO > 14U 582 { 583 SLOW_RUN_CLK, /* name */ 584 3U, /* value */ 585 { 586 0U, 587 } 588 }, 589 #endif 590 591 #if CLOCK_IP_DIVIDERS_NO > 15U 592 { 593 SLOW_VLPR_CLK, /* name */ 594 4U, /* value */ 595 { 596 0U, 597 } 598 }, 599 #endif 600 601 #if CLOCK_IP_DIVIDERS_NO > 16U 602 { 603 SLOW_HSRUN_CLK, /* name */ 604 2U, /* value */ 605 { 606 0U, 607 } 608 }, 609 #endif 610 611 #if CLOCK_IP_DIVIDERS_NO > 17U 612 { 613 CLKOUT0_CLK, /* name */ 614 5U, /* value */ 615 { 616 0U, 617 } 618 }, 619 #endif 620 621 #if CLOCK_IP_DIVIDERS_NO > 18U 622 { 623 LPTMR0_CLK, /* name */ 624 1U, /* value */ 625 { 626 1U, 627 } 628 }, 629 #endif 630 631 #if CLOCK_IP_DIVIDERS_NO > 19U 632 { 633 TRACE_CLK, /* name */ 634 1U, /* value */ 635 { 636 1U, 637 } 638 }, 639 #endif 640 }, 641 642 /* TRIGGER DIVIDER Initialization. */ 643 { 644 { 645 RESERVED_CLK, /* divider name */ 646 IMMEDIATE_DIVIDER_UPDATE, /* trigger value */ 647 RESERVED_CLK, /* input source name */ 648 }, 649 }, 650 651 652 653 /* FRACTIONAL DIVIDER initialization. */ 654 { 655 { 656 RESERVED_CLK, 657 0U, 658 { 659 0U, 660 0U, 661 }, 662 }, 663 }, 664 665 666 667 /* EXTERNAL CLOCKS initialization. */ 668 { 669 670 #if CLOCK_IP_EXT_CLKS_NO > 0U 671 { 672 TCLK0_REF_CLK, /* name */ 673 0U, /* value */ 674 }, 675 #endif 676 677 #if CLOCK_IP_EXT_CLKS_NO > 1U 678 { 679 TCLK1_REF_CLK, /* name */ 680 0U, /* value */ 681 }, 682 #endif 683 684 #if CLOCK_IP_EXT_CLKS_NO > 2U 685 { 686 TCLK2_REF_CLK, /* name */ 687 0U, /* value */ 688 }, 689 #endif 690 691 #if CLOCK_IP_EXT_CLKS_NO > 3U 692 { 693 RTC_CLKIN, /* name */ 694 32768U, /* value */ 695 }, 696 #endif 697 }, 698 699 700 701 /* CLOCK GATES initialization. */ 702 { 703 704 #if CLOCK_IP_GATES_NO > 0U 705 { 706 LPO_32K_CLK, /* name */ 707 1U, /* enable */ 708 }, 709 #endif 710 711 #if CLOCK_IP_GATES_NO > 1U 712 { 713 LPO_1K_CLK, /* name */ 714 1U, /* enable */ 715 }, 716 #endif 717 718 #if CLOCK_IP_GATES_NO > 2U 719 { 720 ADC0_CLK, /* name */ 721 1U, /* enable */ 722 }, 723 #endif 724 725 #if CLOCK_IP_GATES_NO > 3U 726 { 727 ADC1_CLK, /* name */ 728 1U, /* enable */ 729 }, 730 #endif 731 732 #if CLOCK_IP_GATES_NO > 4U 733 { 734 CLKOUT0_CLK, /* name */ 735 1U, /* enable */ 736 }, 737 #endif 738 739 #if CLOCK_IP_GATES_NO > 5U 740 { 741 CMP0_CLK, /* name */ 742 1U, /* enable */ 743 }, 744 #endif 745 746 #if CLOCK_IP_GATES_NO > 6U 747 { 748 CRC0_CLK, /* name */ 749 1U, /* enable */ 750 }, 751 #endif 752 753 #if CLOCK_IP_GATES_NO > 7U 754 { 755 DMA0_CLK, /* name */ 756 1U, /* enable */ 757 }, 758 #endif 759 760 #if CLOCK_IP_GATES_NO > 8U 761 { 762 DMAMUX0_CLK, /* name */ 763 1U, /* enable */ 764 }, 765 #endif 766 767 #if CLOCK_IP_GATES_NO > 9U 768 { 769 EIM0_CLK, /* name */ 770 1U, /* enable */ 771 }, 772 #endif 773 774 #if CLOCK_IP_GATES_NO > 10U 775 { 776 ERM0_CLK, /* name */ 777 1U, /* enable */ 778 }, 779 #endif 780 781 #if CLOCK_IP_GATES_NO > 11U 782 { 783 EWM0_CLK, /* name */ 784 1U, /* enable */ 785 }, 786 #endif 787 788 #if CLOCK_IP_GATES_NO > 12U 789 { 790 FLEXCAN0_CLK, /* name */ 791 1U, /* enable */ 792 }, 793 #endif 794 795 #if CLOCK_IP_GATES_NO > 13U 796 { 797 FLEXCAN1_CLK, /* name */ 798 1U, /* enable */ 799 }, 800 #endif 801 802 #if CLOCK_IP_GATES_NO > 14U 803 { 804 FLEXCAN2_CLK, /* name */ 805 1U, /* enable */ 806 }, 807 #endif 808 809 #if CLOCK_IP_GATES_NO > 15U 810 { 811 FlexIO_CLK, /* name */ 812 1U, /* enable */ 813 }, 814 #endif 815 816 #if CLOCK_IP_GATES_NO > 16U 817 { 818 FTFC_CLK, /* name */ 819 1U, /* enable */ 820 }, 821 #endif 822 823 #if CLOCK_IP_GATES_NO > 17U 824 { 825 FTM0_CLK, /* name */ 826 1U, /* enable */ 827 }, 828 #endif 829 830 #if CLOCK_IP_GATES_NO > 18U 831 { 832 FTM1_CLK, /* name */ 833 1U, /* enable */ 834 }, 835 #endif 836 837 #if CLOCK_IP_GATES_NO > 19U 838 { 839 FTM2_CLK, /* name */ 840 1U, /* enable */ 841 }, 842 #endif 843 844 #if CLOCK_IP_GATES_NO > 20U 845 { 846 FTM3_CLK, /* name */ 847 1U, /* enable */ 848 }, 849 #endif 850 851 #if CLOCK_IP_GATES_NO > 21U 852 { 853 FTM4_CLK, /* name */ 854 1U, /* enable */ 855 }, 856 #endif 857 858 #if CLOCK_IP_GATES_NO > 22U 859 { 860 FTM5_CLK, /* name */ 861 1U, /* enable */ 862 }, 863 #endif 864 865 #if CLOCK_IP_GATES_NO > 23U 866 { 867 LPI2C0_CLK, /* name */ 868 1U, /* enable */ 869 }, 870 #endif 871 872 #if CLOCK_IP_GATES_NO > 24U 873 { 874 LPIT0_CLK, /* name */ 875 1U, /* enable */ 876 }, 877 #endif 878 879 #if CLOCK_IP_GATES_NO > 25U 880 { 881 LPSPI0_CLK, /* name */ 882 1U, /* enable */ 883 }, 884 #endif 885 886 #if CLOCK_IP_GATES_NO > 26U 887 { 888 LPSPI1_CLK, /* name */ 889 1U, /* enable */ 890 }, 891 #endif 892 893 #if CLOCK_IP_GATES_NO > 27U 894 { 895 LPSPI2_CLK, /* name */ 896 1U, /* enable */ 897 }, 898 #endif 899 900 #if CLOCK_IP_GATES_NO > 28U 901 { 902 LPTMR0_CLK, /* name */ 903 1U, /* enable */ 904 }, 905 #endif 906 907 #if CLOCK_IP_GATES_NO > 29U 908 { 909 LPUART0_CLK, /* name */ 910 1U, /* enable */ 911 }, 912 #endif 913 914 #if CLOCK_IP_GATES_NO > 30U 915 { 916 LPUART1_CLK, /* name */ 917 1U, /* enable */ 918 }, 919 #endif 920 921 #if CLOCK_IP_GATES_NO > 31U 922 { 923 LPUART2_CLK, /* name */ 924 1U, /* enable */ 925 }, 926 #endif 927 928 #if CLOCK_IP_GATES_NO > 32U 929 { 930 MPU0_CLK, /* name */ 931 1U, /* enable */ 932 }, 933 #endif 934 935 #if CLOCK_IP_GATES_NO > 33U 936 { 937 MSCM0_CLK, /* name */ 938 1U, /* enable */ 939 }, 940 #endif 941 942 #if CLOCK_IP_GATES_NO > 34U 943 { 944 PDB0_CLK, /* name */ 945 1U, /* enable */ 946 }, 947 #endif 948 949 #if CLOCK_IP_GATES_NO > 35U 950 { 951 PDB1_CLK, /* name */ 952 1U, /* enable */ 953 }, 954 #endif 955 956 #if CLOCK_IP_GATES_NO > 36U 957 { 958 PORTA_CLK, /* name */ 959 1U, /* enable */ 960 }, 961 #endif 962 963 #if CLOCK_IP_GATES_NO > 37U 964 { 965 PORTB_CLK, /* name */ 966 1U, /* enable */ 967 }, 968 #endif 969 970 #if CLOCK_IP_GATES_NO > 38U 971 { 972 PORTC_CLK, /* name */ 973 1U, /* enable */ 974 }, 975 #endif 976 977 #if CLOCK_IP_GATES_NO > 39U 978 { 979 PORTD_CLK, /* name */ 980 1U, /* enable */ 981 }, 982 #endif 983 984 #if CLOCK_IP_GATES_NO > 40U 985 { 986 PORTE_CLK, /* name */ 987 1U, /* enable */ 988 }, 989 #endif 990 991 #if CLOCK_IP_GATES_NO > 41U 992 { 993 RTC0_CLK, /* name */ 994 1U, /* enable */ 995 }, 996 #endif 997 998 #if CLOCK_IP_GATES_NO > 42U 999 { 1000 TRACE_CLK, /* name */ 1001 1U, /* enable */ 1002 }, 1003 #endif 1004 }, 1005 1006 1007 /* PCFS initialization. */ 1008 { 1009 { 1010 RESERVED_CLK, 1011 0U, 1012 0U, 1013 RESERVED_CLK, 1014 0U, 1015 }, 1016 }, 1017 1018 1019 /* Clock monitor */ 1020 { 1021 { 1022 RESERVED_CLK, 1023 0U, 1024 0U, 1025 0U, 1026 { 1027 0U, /* Start index in register values array */ 1028 0U, /* End index in register values array */ 1029 }, 1030 }, 1031 }, 1032 1033 1034 /* Specific peripheral initialization. */ 1035 { 1036 0U, 1037 { 1038 { 1039 RESERVED_VALUE, 1040 0U, 1041 }, 1042 }, 1043 }, 1044 /* Configured frequency values. */ 1045 { 1046 { 1047 CLOCK_IS_OFF, 1048 0U, 1049 }, 1050 }, 1051 }, 1052 }; 1053 1054 1055 #define MCU_STOP_SEC_CONFIG_DATA_UNSPECIFIED 1056 #include "Mcu_MemMap.h" 1057 1058 1059 /*================================================================================================== 1060 LOCAL FUNCTION PROTOTYPES 1061 ==================================================================================================*/ 1062 1063 /*================================================================================================== 1064 LOCAL FUNCTIONS 1065 ==================================================================================================*/ 1066 1067 /*================================================================================================== 1068 GLOBAL FUNCTIONS 1069 ==================================================================================================*/ 1070 1071 #ifdef __cplusplus 1072 } 1073 #endif 1074 1075 /** @} */ 1076
