1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef QSPI_IP_COMMON_H 8 #define QSPI_IP_COMMON_H 9 10 /** 11 * @file Qspi_Ip_Common.h 12 * 13 * @addtogroup IPV_QSPI 14 * @{ 15 */ 16 17 18 #ifdef __cplusplus 19 extern "C"{ 20 #endif 21 22 /*================================================================================================== 23 * SOURCE FILE VERSION INFORMATION 24 ==================================================================================================*/ 25 #define QSPI_IP_COMMON_VENDOR_ID_H 43 26 #define QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H 4 27 #define QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H 7 28 #define QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H 0 29 #define QSPI_IP_COMMON_SW_MAJOR_VERSION_H 2 30 #define QSPI_IP_COMMON_SW_MINOR_VERSION_H 0 31 #define QSPI_IP_COMMON_SW_PATCH_VERSION_H 0 32 33 /*================================================================================================== 34 * FILE VERSION CHECKS 35 ==================================================================================================*/ 36 37 #if (QSPI_IP_MEM_INSTANCE_COUNT > 0) 38 39 /******************************************************************************* 40 * Enumerations. 41 ******************************************************************************/ 42 43 44 /******************************************************************************* 45 * Definitions 46 ******************************************************************************/ 47 48 /*! 49 * @brief Driver configuration structure 50 * 51 * This structure is used to provide configuration parameters for the external flash driver 52 * at initialization time. 53 */ 54 typedef struct 55 { 56 const Qspi_Ip_MemoryConfigType *configuration; /*!< Serial flash device configuration */ 57 const Qspi_Ip_MemoryConnectionType *connection; /*!< Connection to a QSPI device */ 58 uint32 baseAddress; /*!< Base address of serial flash device */ 59 Qspi_Ip_LastCommandType lastCommand; /*!< Last command sent to the flash device */ 60 uint16 activeReadLut; /*!< LUT number for currently active read mode */ 61 } Qspi_Ip_StateType; 62 63 64 /******************************************************************************* 65 * External variable declarations. 66 ******************************************************************************/ 67 68 /* Physical LUT seq to use for all flash commands */ 69 #define QSPI_IP_COMMAND_LUT 0U 70 /* Physical LUT seq to use for AHB reads */ 71 #define QSPI_IP_AHB_LUT 1U 72 73 #define MEM_43_EXFLS_START_SEC_CONST_UNSPECIFIED 74 #include "Mem_43_EXFLS_MemMap.h" 75 76 /* Table of AHB addresses for QuadSPI instances. */ 77 extern const uint32 Qspi_Ip_AhbAddress[QuadSPI_INSTANCE_COUNT]; 78 79 #define MEM_43_EXFLS_STOP_SEC_CONST_UNSPECIFIED 80 #include "Mem_43_EXFLS_MemMap.h" 81 82 83 /*When multicore type3 is enabled on MemAcc, global variables must be allocated to share memory section */ 84 #if( QSPI_IP_MULTICORE_ENABLED == STD_ON) 85 #define MEM_43_EXFLS_START_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE 86 #else 87 #define MEM_43_EXFLS_START_SEC_VAR_CLEARED_UNSPECIFIED 88 #endif 89 #include "Mem_43_EXFLS_MemMap.h" 90 91 /* Pointer to runtime state structures */ 92 extern Qspi_Ip_StateType Qspi_Ip_MemoryStateStructure[]; 93 94 #if( QSPI_IP_MULTICORE_ENABLED == STD_ON) 95 #define MEM_43_EXFLS_STOP_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE 96 #else 97 #define MEM_43_EXFLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED 98 #endif 99 #include "Mem_43_EXFLS_MemMap.h" 100 101 /******************************************************************************* 102 * API 103 ******************************************************************************/ 104 105 #endif /* QSPI_IP_MEM_INSTANCE_COUNT */ 106 107 108 #ifdef __cplusplus 109 } 110 #endif 111 112 /** @} */ 113 114 #endif /* QSPI_IP_COMMON_H */ 115 116