1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Emios_Mcl_Ip_Irq.c
9 *
10 * @brief AUTOSAR Mcl EMIOS interrupt common part.
11 *
12 * @addtogroup
13 * @{
14 */
15
16 #ifdef __cplusplus
17 extern "C"{
18 #endif
19
20 /*==================================================================================================
21 * INCLUDE FILES
22 * 1) system and project includes
23 * 2) needed interfaces from external units
24 * 3) internal and external interfaces from this unit
25 ==================================================================================================*/
26 #include "Emios_Mcl_Ip_Irq.h"
27
28 /*==================================================================================================
29 * SOURCE FILE VERSION INFORMATION
30 ==================================================================================================*/
31 #define EMIOS_MCL_IP_IRQ_VENDOR_ID_C 43
32 #define EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4
33 #define EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7
34 #define EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0
35 #define EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION_C 2
36 #define EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION_C 0
37 #define EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION_C 0
38 /*==================================================================================================
39 * FILE VERSION CHECKS
40 ==================================================================================================*/
41 #if (EMIOS_MCL_IP_IRQ_VENDOR_ID_C != EMIOS_MCL_IP_IRQ_VENDOR_ID)
42 #error "Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h have different vendor ids"
43 #endif
44
45 /* Check if source file and Emios_Mcl_Ip_Irq.h file are of the same Autosar version */
46 #if ((EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
47 (EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
48 (EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION))
49 #error "AutoSar Version Numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different"
50 #endif
51
52 /* Check if source file and Emios_Mcl_Ip_Irq.h file are of the same Software version */
53 #if ((EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION) || \
54 (EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION) || \
55 (EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION_C != EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION))
56 #error "Software Version Numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different"
57 #endif
58
59 /*==================================================================================================
60 * FILE VERSION CHECKS
61 ==================================================================================================*/
62
63 /* Check if Emios_Mcl_Ip_Irq.c file and Emios_Mcl_Ip_Irq header file are of the same vendor. */
64 #if (EMIOS_MCL_IP_IRQ_VENDOR_ID_C != EMIOS_MCL_IP_IRQ_VENDOR_ID)
65 #error "Vendor IDs of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different."
66 #endif
67
68 /* Check if Emios_Mcl_Ip_Irq.c file and Emios_Mcl_Ip_Irq header file are of the same AUTOSAR version. */
69 #if ((EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
70 (EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
71 (EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION))
72 #error "AUTOSAR version numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different."
73 #endif
74
75 /* Check if Emios_Mcl_Ip_Irq.c file and Emios_Mcl_Ip_Irq header file are of the same software version */
76 #if ((EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION) || \
77 (EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION) || \
78 (EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION_C != EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION))
79 #error "Software version numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different."
80 #endif
81
82 /*==================================================================================================
83 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
84 ==================================================================================================*/
85
86 /*==================================================================================================
87 * LOCAL MACROS
88 ==================================================================================================*/
89 #if (\
90 (defined GPT_EMIOS_0_CH_0_ISR_USED) ||\
91 (defined GPT_EMIOS_0_CH_1_ISR_USED) ||\
92 (defined GPT_EMIOS_0_CH_2_ISR_USED) ||\
93 (defined GPT_EMIOS_0_CH_3_ISR_USED) ||\
94 (defined GPT_EMIOS_0_CH_4_ISR_USED) ||\
95 (defined GPT_EMIOS_0_CH_5_ISR_USED) ||\
96 (defined GPT_EMIOS_0_CH_6_ISR_USED) ||\
97 (defined GPT_EMIOS_0_CH_7_ISR_USED) ||\
98 (defined GPT_EMIOS_0_CH_8_ISR_USED) ||\
99 (defined GPT_EMIOS_0_CH_9_ISR_USED) ||\
100 (defined GPT_EMIOS_0_CH_10_ISR_USED) ||\
101 (defined GPT_EMIOS_0_CH_11_ISR_USED) ||\
102 (defined GPT_EMIOS_0_CH_12_ISR_USED) ||\
103 (defined GPT_EMIOS_0_CH_13_ISR_USED) ||\
104 (defined GPT_EMIOS_0_CH_14_ISR_USED) ||\
105 (defined GPT_EMIOS_0_CH_15_ISR_USED) ||\
106 (defined GPT_EMIOS_0_CH_16_ISR_USED) ||\
107 (defined GPT_EMIOS_0_CH_17_ISR_USED) ||\
108 (defined GPT_EMIOS_0_CH_18_ISR_USED) ||\
109 (defined GPT_EMIOS_0_CH_19_ISR_USED) ||\
110 (defined GPT_EMIOS_0_CH_20_ISR_USED) ||\
111 (defined GPT_EMIOS_0_CH_21_ISR_USED) ||\
112 (defined GPT_EMIOS_0_CH_22_ISR_USED) ||\
113 (defined GPT_EMIOS_0_CH_23_ISR_USED) ||\
114 (defined GPT_EMIOS_0_CH_24_ISR_USED) ||\
115 (defined GPT_EMIOS_0_CH_25_ISR_USED) ||\
116 (defined GPT_EMIOS_0_CH_26_ISR_USED) ||\
117 (defined GPT_EMIOS_0_CH_27_ISR_USED) ||\
118 (defined GPT_EMIOS_0_CH_28_ISR_USED) ||\
119 (defined GPT_EMIOS_0_CH_29_ISR_USED) ||\
120 (defined GPT_EMIOS_0_CH_30_ISR_USED) ||\
121 (defined GPT_EMIOS_0_CH_31_ISR_USED) ||\
122 (defined GPT_EMIOS_1_CH_0_ISR_USED) ||\
123 (defined GPT_EMIOS_1_CH_1_ISR_USED) ||\
124 (defined GPT_EMIOS_1_CH_2_ISR_USED) ||\
125 (defined GPT_EMIOS_1_CH_3_ISR_USED) ||\
126 (defined GPT_EMIOS_1_CH_4_ISR_USED) ||\
127 (defined GPT_EMIOS_1_CH_5_ISR_USED) ||\
128 (defined GPT_EMIOS_1_CH_6_ISR_USED) ||\
129 (defined GPT_EMIOS_1_CH_7_ISR_USED) ||\
130 (defined GPT_EMIOS_1_CH_8_ISR_USED) ||\
131 (defined GPT_EMIOS_1_CH_9_ISR_USED) ||\
132 (defined GPT_EMIOS_1_CH_10_ISR_USED) ||\
133 (defined GPT_EMIOS_1_CH_11_ISR_USED) ||\
134 (defined GPT_EMIOS_1_CH_12_ISR_USED) ||\
135 (defined GPT_EMIOS_1_CH_13_ISR_USED) ||\
136 (defined GPT_EMIOS_1_CH_14_ISR_USED) ||\
137 (defined GPT_EMIOS_1_CH_15_ISR_USED) ||\
138 (defined GPT_EMIOS_1_CH_16_ISR_USED) ||\
139 (defined GPT_EMIOS_1_CH_17_ISR_USED) ||\
140 (defined GPT_EMIOS_1_CH_18_ISR_USED) ||\
141 (defined GPT_EMIOS_1_CH_19_ISR_USED) ||\
142 (defined GPT_EMIOS_1_CH_20_ISR_USED) ||\
143 (defined GPT_EMIOS_1_CH_21_ISR_USED) ||\
144 (defined GPT_EMIOS_1_CH_22_ISR_USED) ||\
145 (defined GPT_EMIOS_1_CH_23_ISR_USED) ||\
146 (defined GPT_EMIOS_1_CH_24_ISR_USED) ||\
147 (defined GPT_EMIOS_1_CH_25_ISR_USED) ||\
148 (defined GPT_EMIOS_1_CH_26_ISR_USED) ||\
149 (defined GPT_EMIOS_1_CH_27_ISR_USED) ||\
150 (defined GPT_EMIOS_1_CH_28_ISR_USED) ||\
151 (defined GPT_EMIOS_1_CH_29_ISR_USED) ||\
152 (defined GPT_EMIOS_1_CH_30_ISR_USED) ||\
153 (defined GPT_EMIOS_1_CH_31_ISR_USED) ||\
154 (defined GPT_EMIOS_2_CH_0_ISR_USED) ||\
155 (defined GPT_EMIOS_2_CH_1_ISR_USED) ||\
156 (defined GPT_EMIOS_2_CH_2_ISR_USED) ||\
157 (defined GPT_EMIOS_2_CH_3_ISR_USED) ||\
158 (defined GPT_EMIOS_2_CH_4_ISR_USED) ||\
159 (defined GPT_EMIOS_2_CH_5_ISR_USED) ||\
160 (defined GPT_EMIOS_2_CH_6_ISR_USED) ||\
161 (defined GPT_EMIOS_2_CH_7_ISR_USED) ||\
162 (defined GPT_EMIOS_2_CH_8_ISR_USED) ||\
163 (defined GPT_EMIOS_2_CH_9_ISR_USED) ||\
164 (defined GPT_EMIOS_2_CH_10_ISR_USED) ||\
165 (defined GPT_EMIOS_2_CH_11_ISR_USED) ||\
166 (defined GPT_EMIOS_2_CH_12_ISR_USED) ||\
167 (defined GPT_EMIOS_2_CH_13_ISR_USED) ||\
168 (defined GPT_EMIOS_2_CH_14_ISR_USED) ||\
169 (defined GPT_EMIOS_2_CH_15_ISR_USED) ||\
170 (defined GPT_EMIOS_2_CH_16_ISR_USED) ||\
171 (defined GPT_EMIOS_2_CH_17_ISR_USED) ||\
172 (defined GPT_EMIOS_2_CH_18_ISR_USED) ||\
173 (defined GPT_EMIOS_2_CH_19_ISR_USED) ||\
174 (defined GPT_EMIOS_2_CH_20_ISR_USED) ||\
175 (defined GPT_EMIOS_2_CH_21_ISR_USED) ||\
176 (defined GPT_EMIOS_2_CH_22_ISR_USED) ||\
177 (defined GPT_EMIOS_2_CH_23_ISR_USED) ||\
178 (defined GPT_EMIOS_2_CH_24_ISR_USED) ||\
179 (defined GPT_EMIOS_2_CH_25_ISR_USED) ||\
180 (defined GPT_EMIOS_2_CH_26_ISR_USED) ||\
181 (defined GPT_EMIOS_2_CH_27_ISR_USED) ||\
182 (defined GPT_EMIOS_2_CH_28_ISR_USED) ||\
183 (defined GPT_EMIOS_2_CH_29_ISR_USED) ||\
184 (defined GPT_EMIOS_2_CH_30_ISR_USED) ||\
185 (defined GPT_EMIOS_2_CH_31_ISR_USED) ||\
186 (defined ICU_EMIOS_0_CH_0_ISR_USED) ||\
187 (defined ICU_EMIOS_0_CH_1_ISR_USED) ||\
188 (defined ICU_EMIOS_0_CH_2_ISR_USED) ||\
189 (defined ICU_EMIOS_0_CH_3_ISR_USED) ||\
190 (defined ICU_EMIOS_0_CH_4_ISR_USED) ||\
191 (defined ICU_EMIOS_0_CH_5_ISR_USED) ||\
192 (defined ICU_EMIOS_0_CH_6_ISR_USED) ||\
193 (defined ICU_EMIOS_0_CH_7_ISR_USED) ||\
194 (defined ICU_EMIOS_0_CH_8_ISR_USED) ||\
195 (defined ICU_EMIOS_0_CH_9_ISR_USED) ||\
196 (defined ICU_EMIOS_0_CH_10_ISR_USED) ||\
197 (defined ICU_EMIOS_0_CH_11_ISR_USED) ||\
198 (defined ICU_EMIOS_0_CH_12_ISR_USED) ||\
199 (defined ICU_EMIOS_0_CH_13_ISR_USED) ||\
200 (defined ICU_EMIOS_0_CH_14_ISR_USED) ||\
201 (defined ICU_EMIOS_0_CH_15_ISR_USED) ||\
202 (defined ICU_EMIOS_0_CH_16_ISR_USED) ||\
203 (defined ICU_EMIOS_0_CH_17_ISR_USED) ||\
204 (defined ICU_EMIOS_0_CH_18_ISR_USED) ||\
205 (defined ICU_EMIOS_0_CH_19_ISR_USED) ||\
206 (defined ICU_EMIOS_0_CH_20_ISR_USED) ||\
207 (defined ICU_EMIOS_0_CH_21_ISR_USED) ||\
208 (defined ICU_EMIOS_0_CH_22_ISR_USED) ||\
209 (defined ICU_EMIOS_0_CH_23_ISR_USED) ||\
210 (defined ICU_EMIOS_0_CH_24_ISR_USED) ||\
211 (defined ICU_EMIOS_0_CH_25_ISR_USED) ||\
212 (defined ICU_EMIOS_0_CH_26_ISR_USED) ||\
213 (defined ICU_EMIOS_0_CH_27_ISR_USED) ||\
214 (defined ICU_EMIOS_0_CH_28_ISR_USED) ||\
215 (defined ICU_EMIOS_0_CH_29_ISR_USED) ||\
216 (defined ICU_EMIOS_0_CH_30_ISR_USED) ||\
217 (defined ICU_EMIOS_0_CH_31_ISR_USED) ||\
218 (defined ICU_EMIOS_1_CH_0_ISR_USED) ||\
219 (defined ICU_EMIOS_1_CH_1_ISR_USED) ||\
220 (defined ICU_EMIOS_1_CH_2_ISR_USED) ||\
221 (defined ICU_EMIOS_1_CH_3_ISR_USED) ||\
222 (defined ICU_EMIOS_1_CH_4_ISR_USED) ||\
223 (defined ICU_EMIOS_1_CH_5_ISR_USED) ||\
224 (defined ICU_EMIOS_1_CH_6_ISR_USED) ||\
225 (defined ICU_EMIOS_1_CH_7_ISR_USED) ||\
226 (defined ICU_EMIOS_1_CH_8_ISR_USED) ||\
227 (defined ICU_EMIOS_1_CH_9_ISR_USED) ||\
228 (defined ICU_EMIOS_1_CH_10_ISR_USED) ||\
229 (defined ICU_EMIOS_1_CH_11_ISR_USED) ||\
230 (defined ICU_EMIOS_1_CH_12_ISR_USED) ||\
231 (defined ICU_EMIOS_1_CH_13_ISR_USED) ||\
232 (defined ICU_EMIOS_1_CH_14_ISR_USED) ||\
233 (defined ICU_EMIOS_1_CH_15_ISR_USED) ||\
234 (defined ICU_EMIOS_1_CH_16_ISR_USED) ||\
235 (defined ICU_EMIOS_1_CH_17_ISR_USED) ||\
236 (defined ICU_EMIOS_1_CH_18_ISR_USED) ||\
237 (defined ICU_EMIOS_1_CH_19_ISR_USED) ||\
238 (defined ICU_EMIOS_1_CH_20_ISR_USED) ||\
239 (defined ICU_EMIOS_1_CH_21_ISR_USED) ||\
240 (defined ICU_EMIOS_1_CH_22_ISR_USED) ||\
241 (defined ICU_EMIOS_1_CH_23_ISR_USED) ||\
242 (defined ICU_EMIOS_1_CH_24_ISR_USED) ||\
243 (defined ICU_EMIOS_1_CH_25_ISR_USED) ||\
244 (defined ICU_EMIOS_1_CH_26_ISR_USED) ||\
245 (defined ICU_EMIOS_1_CH_27_ISR_USED) ||\
246 (defined ICU_EMIOS_1_CH_28_ISR_USED) ||\
247 (defined ICU_EMIOS_1_CH_29_ISR_USED) ||\
248 (defined ICU_EMIOS_1_CH_30_ISR_USED) ||\
249 (defined ICU_EMIOS_1_CH_31_ISR_USED) ||\
250 (defined ICU_EMIOS_2_CH_0_ISR_USED) ||\
251 (defined ICU_EMIOS_2_CH_1_ISR_USED) ||\
252 (defined ICU_EMIOS_2_CH_2_ISR_USED) ||\
253 (defined ICU_EMIOS_2_CH_3_ISR_USED) ||\
254 (defined ICU_EMIOS_2_CH_4_ISR_USED) ||\
255 (defined ICU_EMIOS_2_CH_5_ISR_USED) ||\
256 (defined ICU_EMIOS_2_CH_6_ISR_USED) ||\
257 (defined ICU_EMIOS_2_CH_7_ISR_USED) ||\
258 (defined ICU_EMIOS_2_CH_8_ISR_USED) ||\
259 (defined ICU_EMIOS_2_CH_9_ISR_USED) ||\
260 (defined ICU_EMIOS_2_CH_10_ISR_USED) ||\
261 (defined ICU_EMIOS_2_CH_11_ISR_USED) ||\
262 (defined ICU_EMIOS_2_CH_12_ISR_USED) ||\
263 (defined ICU_EMIOS_2_CH_13_ISR_USED) ||\
264 (defined ICU_EMIOS_2_CH_14_ISR_USED) ||\
265 (defined ICU_EMIOS_2_CH_15_ISR_USED) ||\
266 (defined ICU_EMIOS_2_CH_16_ISR_USED) ||\
267 (defined ICU_EMIOS_2_CH_17_ISR_USED) ||\
268 (defined ICU_EMIOS_2_CH_18_ISR_USED) ||\
269 (defined ICU_EMIOS_2_CH_19_ISR_USED) ||\
270 (defined ICU_EMIOS_2_CH_20_ISR_USED) ||\
271 (defined ICU_EMIOS_2_CH_21_ISR_USED) ||\
272 (defined ICU_EMIOS_2_CH_22_ISR_USED) ||\
273 (defined ICU_EMIOS_2_CH_23_ISR_USED) ||\
274 (defined ICU_EMIOS_2_CH_24_ISR_USED) ||\
275 (defined ICU_EMIOS_2_CH_25_ISR_USED) ||\
276 (defined ICU_EMIOS_2_CH_26_ISR_USED) ||\
277 (defined ICU_EMIOS_2_CH_27_ISR_USED) ||\
278 (defined ICU_EMIOS_2_CH_28_ISR_USED) ||\
279 (defined ICU_EMIOS_2_CH_29_ISR_USED) ||\
280 (defined ICU_EMIOS_2_CH_30_ISR_USED) ||\
281 (defined ICU_EMIOS_2_CH_31_ISR_USED) ||\
282 (defined OCU_EMIOS_0_CH_0_ISR_USED) ||\
283 (defined OCU_EMIOS_0_CH_1_ISR_USED) ||\
284 (defined OCU_EMIOS_0_CH_2_ISR_USED) ||\
285 (defined OCU_EMIOS_0_CH_3_ISR_USED) ||\
286 (defined OCU_EMIOS_0_CH_4_ISR_USED) ||\
287 (defined OCU_EMIOS_0_CH_5_ISR_USED) ||\
288 (defined OCU_EMIOS_0_CH_6_ISR_USED) ||\
289 (defined OCU_EMIOS_0_CH_7_ISR_USED) ||\
290 (defined OCU_EMIOS_0_CH_8_ISR_USED) ||\
291 (defined OCU_EMIOS_0_CH_9_ISR_USED) ||\
292 (defined OCU_EMIOS_0_CH_10_ISR_USED) ||\
293 (defined OCU_EMIOS_0_CH_11_ISR_USED) ||\
294 (defined OCU_EMIOS_0_CH_12_ISR_USED) ||\
295 (defined OCU_EMIOS_0_CH_13_ISR_USED) ||\
296 (defined OCU_EMIOS_0_CH_14_ISR_USED) ||\
297 (defined OCU_EMIOS_0_CH_15_ISR_USED) ||\
298 (defined OCU_EMIOS_0_CH_16_ISR_USED) ||\
299 (defined OCU_EMIOS_0_CH_17_ISR_USED) ||\
300 (defined OCU_EMIOS_0_CH_18_ISR_USED) ||\
301 (defined OCU_EMIOS_0_CH_19_ISR_USED) ||\
302 (defined OCU_EMIOS_0_CH_20_ISR_USED) ||\
303 (defined OCU_EMIOS_0_CH_21_ISR_USED) ||\
304 (defined OCU_EMIOS_0_CH_22_ISR_USED) ||\
305 (defined OCU_EMIOS_0_CH_23_ISR_USED) ||\
306 (defined OCU_EMIOS_0_CH_24_ISR_USED) ||\
307 (defined OCU_EMIOS_0_CH_25_ISR_USED) ||\
308 (defined OCU_EMIOS_0_CH_26_ISR_USED) ||\
309 (defined OCU_EMIOS_0_CH_27_ISR_USED) ||\
310 (defined OCU_EMIOS_0_CH_28_ISR_USED) ||\
311 (defined OCU_EMIOS_0_CH_29_ISR_USED) ||\
312 (defined OCU_EMIOS_0_CH_30_ISR_USED) ||\
313 (defined OCU_EMIOS_0_CH_31_ISR_USED) ||\
314 (defined OCU_EMIOS_1_CH_0_ISR_USED) ||\
315 (defined OCU_EMIOS_1_CH_1_ISR_USED) ||\
316 (defined OCU_EMIOS_1_CH_2_ISR_USED) ||\
317 (defined OCU_EMIOS_1_CH_3_ISR_USED) ||\
318 (defined OCU_EMIOS_1_CH_4_ISR_USED) ||\
319 (defined OCU_EMIOS_1_CH_5_ISR_USED) ||\
320 (defined OCU_EMIOS_1_CH_6_ISR_USED) ||\
321 (defined OCU_EMIOS_1_CH_7_ISR_USED) ||\
322 (defined OCU_EMIOS_1_CH_8_ISR_USED) ||\
323 (defined OCU_EMIOS_1_CH_9_ISR_USED) ||\
324 (defined OCU_EMIOS_1_CH_10_ISR_USED) ||\
325 (defined OCU_EMIOS_1_CH_11_ISR_USED) ||\
326 (defined OCU_EMIOS_1_CH_12_ISR_USED) ||\
327 (defined OCU_EMIOS_1_CH_13_ISR_USED) ||\
328 (defined OCU_EMIOS_1_CH_14_ISR_USED) ||\
329 (defined OCU_EMIOS_1_CH_15_ISR_USED) ||\
330 (defined OCU_EMIOS_1_CH_16_ISR_USED) ||\
331 (defined OCU_EMIOS_1_CH_17_ISR_USED) ||\
332 (defined OCU_EMIOS_1_CH_18_ISR_USED) ||\
333 (defined OCU_EMIOS_1_CH_19_ISR_USED) ||\
334 (defined OCU_EMIOS_1_CH_20_ISR_USED) ||\
335 (defined OCU_EMIOS_1_CH_21_ISR_USED) ||\
336 (defined OCU_EMIOS_1_CH_22_ISR_USED) ||\
337 (defined OCU_EMIOS_1_CH_23_ISR_USED) ||\
338 (defined OCU_EMIOS_1_CH_24_ISR_USED) ||\
339 (defined OCU_EMIOS_1_CH_25_ISR_USED) ||\
340 (defined OCU_EMIOS_1_CH_26_ISR_USED) ||\
341 (defined OCU_EMIOS_1_CH_27_ISR_USED) ||\
342 (defined OCU_EMIOS_1_CH_28_ISR_USED) ||\
343 (defined OCU_EMIOS_1_CH_29_ISR_USED) ||\
344 (defined OCU_EMIOS_1_CH_30_ISR_USED) ||\
345 (defined OCU_EMIOS_1_CH_31_ISR_USED) ||\
346 (defined OCU_EMIOS_2_CH_0_ISR_USED) ||\
347 (defined OCU_EMIOS_2_CH_1_ISR_USED) ||\
348 (defined OCU_EMIOS_2_CH_2_ISR_USED) ||\
349 (defined OCU_EMIOS_2_CH_3_ISR_USED) ||\
350 (defined OCU_EMIOS_2_CH_4_ISR_USED) ||\
351 (defined OCU_EMIOS_2_CH_5_ISR_USED) ||\
352 (defined OCU_EMIOS_2_CH_6_ISR_USED) ||\
353 (defined OCU_EMIOS_2_CH_7_ISR_USED) ||\
354 (defined OCU_EMIOS_2_CH_8_ISR_USED) ||\
355 (defined OCU_EMIOS_2_CH_9_ISR_USED) ||\
356 (defined OCU_EMIOS_2_CH_10_ISR_USED) ||\
357 (defined OCU_EMIOS_2_CH_11_ISR_USED) ||\
358 (defined OCU_EMIOS_2_CH_12_ISR_USED) ||\
359 (defined OCU_EMIOS_2_CH_13_ISR_USED) ||\
360 (defined OCU_EMIOS_2_CH_14_ISR_USED) ||\
361 (defined OCU_EMIOS_2_CH_15_ISR_USED) ||\
362 (defined OCU_EMIOS_2_CH_16_ISR_USED) ||\
363 (defined OCU_EMIOS_2_CH_17_ISR_USED) ||\
364 (defined OCU_EMIOS_2_CH_18_ISR_USED) ||\
365 (defined OCU_EMIOS_2_CH_19_ISR_USED) ||\
366 (defined OCU_EMIOS_2_CH_20_ISR_USED) ||\
367 (defined OCU_EMIOS_2_CH_21_ISR_USED) ||\
368 (defined OCU_EMIOS_2_CH_22_ISR_USED) ||\
369 (defined OCU_EMIOS_2_CH_23_ISR_USED) ||\
370 (defined OCU_EMIOS_2_CH_24_ISR_USED) ||\
371 (defined OCU_EMIOS_2_CH_25_ISR_USED) ||\
372 (defined OCU_EMIOS_2_CH_26_ISR_USED) ||\
373 (defined OCU_EMIOS_2_CH_27_ISR_USED) ||\
374 (defined OCU_EMIOS_2_CH_28_ISR_USED) ||\
375 (defined OCU_EMIOS_2_CH_29_ISR_USED) ||\
376 (defined OCU_EMIOS_2_CH_30_ISR_USED) ||\
377 (defined OCU_EMIOS_2_CH_31_ISR_USED) ||\
378 (defined PWM_EMIOS_0_CH_0_ISR_USED) ||\
379 (defined PWM_EMIOS_0_CH_1_ISR_USED) ||\
380 (defined PWM_EMIOS_0_CH_2_ISR_USED) ||\
381 (defined PWM_EMIOS_0_CH_3_ISR_USED) ||\
382 (defined PWM_EMIOS_0_CH_4_ISR_USED) ||\
383 (defined PWM_EMIOS_0_CH_5_ISR_USED) ||\
384 (defined PWM_EMIOS_0_CH_6_ISR_USED) ||\
385 (defined PWM_EMIOS_0_CH_7_ISR_USED) ||\
386 (defined PWM_EMIOS_0_CH_8_ISR_USED) ||\
387 (defined PWM_EMIOS_0_CH_9_ISR_USED) ||\
388 (defined PWM_EMIOS_0_CH_10_ISR_USED) ||\
389 (defined PWM_EMIOS_0_CH_11_ISR_USED) ||\
390 (defined PWM_EMIOS_0_CH_12_ISR_USED) ||\
391 (defined PWM_EMIOS_0_CH_13_ISR_USED) ||\
392 (defined PWM_EMIOS_0_CH_14_ISR_USED) ||\
393 (defined PWM_EMIOS_0_CH_15_ISR_USED) ||\
394 (defined PWM_EMIOS_0_CH_16_ISR_USED) ||\
395 (defined PWM_EMIOS_0_CH_17_ISR_USED) ||\
396 (defined PWM_EMIOS_0_CH_18_ISR_USED) ||\
397 (defined PWM_EMIOS_0_CH_19_ISR_USED) ||\
398 (defined PWM_EMIOS_0_CH_20_ISR_USED) ||\
399 (defined PWM_EMIOS_0_CH_21_ISR_USED) ||\
400 (defined PWM_EMIOS_0_CH_22_ISR_USED) ||\
401 (defined PWM_EMIOS_0_CH_23_ISR_USED) ||\
402 (defined PWM_EMIOS_0_CH_24_ISR_USED) ||\
403 (defined PWM_EMIOS_0_CH_25_ISR_USED) ||\
404 (defined PWM_EMIOS_0_CH_26_ISR_USED) ||\
405 (defined PWM_EMIOS_0_CH_27_ISR_USED) ||\
406 (defined PWM_EMIOS_0_CH_28_ISR_USED) ||\
407 (defined PWM_EMIOS_0_CH_29_ISR_USED) ||\
408 (defined PWM_EMIOS_0_CH_30_ISR_USED) ||\
409 (defined PWM_EMIOS_0_CH_31_ISR_USED) ||\
410 (defined PWM_EMIOS_1_CH_0_ISR_USED) ||\
411 (defined PWM_EMIOS_1_CH_1_ISR_USED) ||\
412 (defined PWM_EMIOS_1_CH_2_ISR_USED) ||\
413 (defined PWM_EMIOS_1_CH_3_ISR_USED) ||\
414 (defined PWM_EMIOS_1_CH_4_ISR_USED) ||\
415 (defined PWM_EMIOS_1_CH_5_ISR_USED) ||\
416 (defined PWM_EMIOS_1_CH_6_ISR_USED) ||\
417 (defined PWM_EMIOS_1_CH_7_ISR_USED) ||\
418 (defined PWM_EMIOS_1_CH_8_ISR_USED) ||\
419 (defined PWM_EMIOS_1_CH_9_ISR_USED) ||\
420 (defined PWM_EMIOS_1_CH_10_ISR_USED) ||\
421 (defined PWM_EMIOS_1_CH_11_ISR_USED) ||\
422 (defined PWM_EMIOS_1_CH_12_ISR_USED) ||\
423 (defined PWM_EMIOS_1_CH_13_ISR_USED) ||\
424 (defined PWM_EMIOS_1_CH_14_ISR_USED) ||\
425 (defined PWM_EMIOS_1_CH_15_ISR_USED) ||\
426 (defined PWM_EMIOS_1_CH_16_ISR_USED) ||\
427 (defined PWM_EMIOS_1_CH_17_ISR_USED) ||\
428 (defined PWM_EMIOS_1_CH_18_ISR_USED) ||\
429 (defined PWM_EMIOS_1_CH_19_ISR_USED) ||\
430 (defined PWM_EMIOS_1_CH_20_ISR_USED) ||\
431 (defined PWM_EMIOS_1_CH_21_ISR_USED) ||\
432 (defined PWM_EMIOS_1_CH_22_ISR_USED) ||\
433 (defined PWM_EMIOS_1_CH_23_ISR_USED) ||\
434 (defined PWM_EMIOS_1_CH_24_ISR_USED) ||\
435 (defined PWM_EMIOS_1_CH_25_ISR_USED) ||\
436 (defined PWM_EMIOS_1_CH_26_ISR_USED) ||\
437 (defined PWM_EMIOS_1_CH_27_ISR_USED) ||\
438 (defined PWM_EMIOS_1_CH_28_ISR_USED) ||\
439 (defined PWM_EMIOS_1_CH_29_ISR_USED) ||\
440 (defined PWM_EMIOS_1_CH_30_ISR_USED) ||\
441 (defined PWM_EMIOS_1_CH_31_ISR_USED) ||\
442 (defined PWM_EMIOS_2_CH_0_ISR_USED) ||\
443 (defined PWM_EMIOS_2_CH_1_ISR_USED) ||\
444 (defined PWM_EMIOS_2_CH_2_ISR_USED) ||\
445 (defined PWM_EMIOS_2_CH_3_ISR_USED) ||\
446 (defined PWM_EMIOS_2_CH_4_ISR_USED) ||\
447 (defined PWM_EMIOS_2_CH_5_ISR_USED) ||\
448 (defined PWM_EMIOS_2_CH_6_ISR_USED) ||\
449 (defined PWM_EMIOS_2_CH_7_ISR_USED) ||\
450 (defined PWM_EMIOS_2_CH_8_ISR_USED) ||\
451 (defined PWM_EMIOS_2_CH_9_ISR_USED) ||\
452 (defined PWM_EMIOS_2_CH_10_ISR_USED) ||\
453 (defined PWM_EMIOS_2_CH_11_ISR_USED) ||\
454 (defined PWM_EMIOS_2_CH_12_ISR_USED) ||\
455 (defined PWM_EMIOS_2_CH_13_ISR_USED) ||\
456 (defined PWM_EMIOS_2_CH_14_ISR_USED) ||\
457 (defined PWM_EMIOS_2_CH_15_ISR_USED) ||\
458 (defined PWM_EMIOS_2_CH_16_ISR_USED) ||\
459 (defined PWM_EMIOS_2_CH_17_ISR_USED) ||\
460 (defined PWM_EMIOS_2_CH_18_ISR_USED) ||\
461 (defined PWM_EMIOS_2_CH_19_ISR_USED) ||\
462 (defined PWM_EMIOS_2_CH_20_ISR_USED) ||\
463 (defined PWM_EMIOS_2_CH_21_ISR_USED) ||\
464 (defined PWM_EMIOS_2_CH_22_ISR_USED) ||\
465 (defined PWM_EMIOS_2_CH_23_ISR_USED) ||\
466 (defined PWM_EMIOS_2_CH_24_ISR_USED) ||\
467 (defined PWM_EMIOS_2_CH_25_ISR_USED) ||\
468 (defined PWM_EMIOS_2_CH_26_ISR_USED) ||\
469 (defined PWM_EMIOS_2_CH_27_ISR_USED) ||\
470 (defined PWM_EMIOS_2_CH_28_ISR_USED) ||\
471 (defined PWM_EMIOS_2_CH_29_ISR_USED) ||\
472 (defined PWM_EMIOS_2_CH_30_ISR_USED) ||\
473 (defined PWM_EMIOS_2_CH_31_ISR_USED)\
474 )
475
476 /*==================================================================================================
477 * LOCAL CONSTANTS
478 ==================================================================================================*/
479
480 /*==================================================================================================
481 * LOCAL VARIABLES
482 ==================================================================================================*/
483
484 /*==================================================================================================
485 * GLOBAL CONSTANTS
486 ==================================================================================================*/
487
488 /*==================================================================================================
489 * GLOBAL VARIABLES
490 ==================================================================================================*/
491 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED
492 #include "Mcl_MemMap.h"
493
494 /* Array with EMIOS bases addresses. */
495 extern eMIOS_Type* Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT];
496
497 #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED
498 #include "Mcl_MemMap.h"
499
500 #endif /* All platfrom includes. */
501
502
503 /*==================================================================================================
504 * LOCAL FUNCTION PROTOTYPES
505 ==================================================================================================*/
506
507 /*==================================================================================================
508 * LOCAL FUNCTIONS
509 ==================================================================================================*/
510 #define MCL_START_SEC_CODE
511 #include "Mcl_MemMap.h"
512
513 #if (\
514 (defined GPT_EMIOS_0_CH_0_ISR_USED) ||\
515 (defined GPT_EMIOS_0_CH_1_ISR_USED) ||\
516 (defined GPT_EMIOS_0_CH_2_ISR_USED) ||\
517 (defined GPT_EMIOS_0_CH_3_ISR_USED) ||\
518 (defined GPT_EMIOS_0_CH_4_ISR_USED) ||\
519 (defined GPT_EMIOS_0_CH_5_ISR_USED) ||\
520 (defined GPT_EMIOS_0_CH_6_ISR_USED) ||\
521 (defined GPT_EMIOS_0_CH_7_ISR_USED) ||\
522 (defined GPT_EMIOS_0_CH_16_ISR_USED) ||\
523 (defined GPT_EMIOS_0_CH_17_ISR_USED) ||\
524 (defined GPT_EMIOS_0_CH_18_ISR_USED) ||\
525 (defined GPT_EMIOS_0_CH_19_ISR_USED) ||\
526 (defined GPT_EMIOS_0_CH_20_ISR_USED) ||\
527 (defined GPT_EMIOS_0_CH_21_ISR_USED) ||\
528 (defined GPT_EMIOS_0_CH_22_ISR_USED) ||\
529 (defined GPT_EMIOS_0_CH_23_ISR_USED) ||\
530 (defined GPT_EMIOS_0_CH_24_ISR_USED) ||\
531 (defined GPT_EMIOS_0_CH_25_ISR_USED) ||\
532 (defined GPT_EMIOS_0_CH_26_ISR_USED) ||\
533 (defined GPT_EMIOS_0_CH_27_ISR_USED) ||\
534 (defined GPT_EMIOS_0_CH_28_ISR_USED) ||\
535 (defined GPT_EMIOS_0_CH_29_ISR_USED) ||\
536 (defined GPT_EMIOS_0_CH_30_ISR_USED) ||\
537 (defined GPT_EMIOS_0_CH_31_ISR_USED) ||\
538 (defined GPT_EMIOS_1_CH_0_ISR_USED) ||\
539 (defined GPT_EMIOS_1_CH_1_ISR_USED) ||\
540 (defined GPT_EMIOS_1_CH_2_ISR_USED) ||\
541 (defined GPT_EMIOS_1_CH_3_ISR_USED) ||\
542 (defined GPT_EMIOS_1_CH_4_ISR_USED) ||\
543 (defined GPT_EMIOS_1_CH_5_ISR_USED) ||\
544 (defined GPT_EMIOS_1_CH_6_ISR_USED) ||\
545 (defined GPT_EMIOS_1_CH_7_ISR_USED) ||\
546 (defined GPT_EMIOS_1_CH_16_ISR_USED) ||\
547 (defined GPT_EMIOS_1_CH_17_ISR_USED) ||\
548 (defined GPT_EMIOS_1_CH_18_ISR_USED) ||\
549 (defined GPT_EMIOS_1_CH_19_ISR_USED) ||\
550 (defined GPT_EMIOS_1_CH_20_ISR_USED) ||\
551 (defined GPT_EMIOS_1_CH_21_ISR_USED) ||\
552 (defined GPT_EMIOS_1_CH_22_ISR_USED) ||\
553 (defined GPT_EMIOS_1_CH_23_ISR_USED) ||\
554 (defined GPT_EMIOS_1_CH_24_ISR_USED) ||\
555 (defined GPT_EMIOS_1_CH_25_ISR_USED) ||\
556 (defined GPT_EMIOS_1_CH_26_ISR_USED) ||\
557 (defined GPT_EMIOS_1_CH_27_ISR_USED) ||\
558 (defined GPT_EMIOS_1_CH_28_ISR_USED) ||\
559 (defined GPT_EMIOS_1_CH_29_ISR_USED) ||\
560 (defined GPT_EMIOS_1_CH_30_ISR_USED) ||\
561 (defined GPT_EMIOS_1_CH_31_ISR_USED) ||\
562 (defined GPT_EMIOS_2_CH_0_ISR_USED) ||\
563 (defined GPT_EMIOS_2_CH_1_ISR_USED) ||\
564 (defined GPT_EMIOS_2_CH_2_ISR_USED) ||\
565 (defined GPT_EMIOS_2_CH_3_ISR_USED) ||\
566 (defined GPT_EMIOS_2_CH_4_ISR_USED) ||\
567 (defined GPT_EMIOS_2_CH_5_ISR_USED) ||\
568 (defined GPT_EMIOS_2_CH_6_ISR_USED) ||\
569 (defined GPT_EMIOS_2_CH_7_ISR_USED) ||\
570 (defined GPT_EMIOS_2_CH_8_ISR_USED) ||\
571 (defined GPT_EMIOS_2_CH_9_ISR_USED) ||\
572 (defined GPT_EMIOS_2_CH_10_ISR_USED) ||\
573 (defined GPT_EMIOS_2_CH_11_ISR_USED) ||\
574 (defined GPT_EMIOS_2_CH_12_ISR_USED) ||\
575 (defined GPT_EMIOS_2_CH_13_ISR_USED) ||\
576 (defined GPT_EMIOS_2_CH_14_ISR_USED) ||\
577 (defined GPT_EMIOS_2_CH_15_ISR_USED) ||\
578 (defined GPT_EMIOS_2_CH_16_ISR_USED) ||\
579 (defined GPT_EMIOS_2_CH_17_ISR_USED) ||\
580 (defined GPT_EMIOS_2_CH_18_ISR_USED) ||\
581 (defined GPT_EMIOS_2_CH_19_ISR_USED) ||\
582 (defined GPT_EMIOS_2_CH_20_ISR_USED) ||\
583 (defined GPT_EMIOS_2_CH_21_ISR_USED) ||\
584 (defined GPT_EMIOS_2_CH_22_ISR_USED) ||\
585 (defined GPT_EMIOS_2_CH_23_ISR_USED) ||\
586 (defined GPT_EMIOS_2_CH_24_ISR_USED) ||\
587 (defined GPT_EMIOS_2_CH_25_ISR_USED) ||\
588 (defined GPT_EMIOS_2_CH_26_ISR_USED) ||\
589 (defined GPT_EMIOS_2_CH_27_ISR_USED) ||\
590 (defined GPT_EMIOS_2_CH_28_ISR_USED) ||\
591 (defined GPT_EMIOS_2_CH_29_ISR_USED) ||\
592 (defined GPT_EMIOS_2_CH_30_ISR_USED) ||\
593 (defined GPT_EMIOS_2_CH_31_ISR_USED) \
594 )
Emios_Gpt_IrqHandler(const uint8 Instance,const uint8 Channel)595 static void Emios_Gpt_IrqHandler(const uint8 Instance, const uint8 Channel)
596 {
597 /* Check that an event occurred on Emios channel */
598 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))
599 {
600 /* Check that an event occurred on EMIOS channel */
601 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))))
602 {
603 Emios_Gpt_Ip_IrqHandler(Instance, Channel);
604 }
605 else
606 {
607 /* Do nothing - in case of spurious interrupts, return immediately */
608 }
609 }
610 }
611 #endif
612
613 #if (\
614 (defined ICU_EMIOS_0_CH_0_ISR_USED) ||\
615 (defined ICU_EMIOS_0_CH_1_ISR_USED) ||\
616 (defined ICU_EMIOS_0_CH_2_ISR_USED) ||\
617 (defined ICU_EMIOS_0_CH_3_ISR_USED) ||\
618 (defined ICU_EMIOS_0_CH_4_ISR_USED) ||\
619 (defined ICU_EMIOS_0_CH_5_ISR_USED) ||\
620 (defined ICU_EMIOS_0_CH_6_ISR_USED) ||\
621 (defined ICU_EMIOS_0_CH_7_ISR_USED) ||\
622 (defined ICU_EMIOS_0_CH_16_ISR_USED) ||\
623 (defined ICU_EMIOS_0_CH_17_ISR_USED) ||\
624 (defined ICU_EMIOS_0_CH_18_ISR_USED) ||\
625 (defined ICU_EMIOS_0_CH_19_ISR_USED) ||\
626 (defined ICU_EMIOS_0_CH_20_ISR_USED) ||\
627 (defined ICU_EMIOS_0_CH_21_ISR_USED) ||\
628 (defined ICU_EMIOS_0_CH_22_ISR_USED) ||\
629 (defined ICU_EMIOS_0_CH_23_ISR_USED) ||\
630 (defined ICU_EMIOS_0_CH_24_ISR_USED) ||\
631 (defined ICU_EMIOS_0_CH_25_ISR_USED) ||\
632 (defined ICU_EMIOS_0_CH_26_ISR_USED) ||\
633 (defined ICU_EMIOS_0_CH_27_ISR_USED) ||\
634 (defined ICU_EMIOS_0_CH_28_ISR_USED) ||\
635 (defined ICU_EMIOS_0_CH_29_ISR_USED) ||\
636 (defined ICU_EMIOS_0_CH_30_ISR_USED) ||\
637 (defined ICU_EMIOS_0_CH_31_ISR_USED) ||\
638 (defined ICU_EMIOS_1_CH_0_ISR_USED) ||\
639 (defined ICU_EMIOS_1_CH_1_ISR_USED) ||\
640 (defined ICU_EMIOS_1_CH_2_ISR_USED) ||\
641 (defined ICU_EMIOS_1_CH_3_ISR_USED) ||\
642 (defined ICU_EMIOS_1_CH_4_ISR_USED) ||\
643 (defined ICU_EMIOS_1_CH_5_ISR_USED) ||\
644 (defined ICU_EMIOS_1_CH_6_ISR_USED) ||\
645 (defined ICU_EMIOS_1_CH_7_ISR_USED) ||\
646 (defined ICU_EMIOS_1_CH_16_ISR_USED) ||\
647 (defined ICU_EMIOS_1_CH_17_ISR_USED) ||\
648 (defined ICU_EMIOS_1_CH_18_ISR_USED) ||\
649 (defined ICU_EMIOS_1_CH_19_ISR_USED) ||\
650 (defined ICU_EMIOS_1_CH_20_ISR_USED) ||\
651 (defined ICU_EMIOS_1_CH_21_ISR_USED) ||\
652 (defined ICU_EMIOS_1_CH_22_ISR_USED) ||\
653 (defined ICU_EMIOS_1_CH_23_ISR_USED) ||\
654 (defined ICU_EMIOS_1_CH_24_ISR_USED) ||\
655 (defined ICU_EMIOS_1_CH_25_ISR_USED) ||\
656 (defined ICU_EMIOS_1_CH_26_ISR_USED) ||\
657 (defined ICU_EMIOS_1_CH_27_ISR_USED) ||\
658 (defined ICU_EMIOS_1_CH_28_ISR_USED) ||\
659 (defined ICU_EMIOS_1_CH_29_ISR_USED) ||\
660 (defined ICU_EMIOS_1_CH_30_ISR_USED) ||\
661 (defined ICU_EMIOS_1_CH_31_ISR_USED) ||\
662 (defined ICU_EMIOS_2_CH_0_ISR_USED) ||\
663 (defined ICU_EMIOS_2_CH_1_ISR_USED) ||\
664 (defined ICU_EMIOS_2_CH_2_ISR_USED) ||\
665 (defined ICU_EMIOS_2_CH_3_ISR_USED) ||\
666 (defined ICU_EMIOS_2_CH_4_ISR_USED) ||\
667 (defined ICU_EMIOS_2_CH_5_ISR_USED) ||\
668 (defined ICU_EMIOS_2_CH_6_ISR_USED) ||\
669 (defined ICU_EMIOS_2_CH_7_ISR_USED) ||\
670 (defined ICU_EMIOS_2_CH_8_ISR_USED) ||\
671 (defined ICU_EMIOS_2_CH_9_ISR_USED) ||\
672 (defined ICU_EMIOS_2_CH_10_ISR_USED) ||\
673 (defined ICU_EMIOS_2_CH_11_ISR_USED) ||\
674 (defined ICU_EMIOS_2_CH_12_ISR_USED) ||\
675 (defined ICU_EMIOS_2_CH_13_ISR_USED) ||\
676 (defined ICU_EMIOS_2_CH_14_ISR_USED) ||\
677 (defined ICU_EMIOS_2_CH_15_ISR_USED) ||\
678 (defined ICU_EMIOS_2_CH_16_ISR_USED) ||\
679 (defined ICU_EMIOS_2_CH_17_ISR_USED) ||\
680 (defined ICU_EMIOS_2_CH_18_ISR_USED) ||\
681 (defined ICU_EMIOS_2_CH_19_ISR_USED) ||\
682 (defined ICU_EMIOS_2_CH_20_ISR_USED) ||\
683 (defined ICU_EMIOS_2_CH_21_ISR_USED) ||\
684 (defined ICU_EMIOS_2_CH_22_ISR_USED) ||\
685 (defined ICU_EMIOS_2_CH_23_ISR_USED) ||\
686 (defined ICU_EMIOS_2_CH_24_ISR_USED) ||\
687 (defined ICU_EMIOS_2_CH_25_ISR_USED) ||\
688 (defined ICU_EMIOS_2_CH_26_ISR_USED) ||\
689 (defined ICU_EMIOS_2_CH_27_ISR_USED) ||\
690 (defined ICU_EMIOS_2_CH_28_ISR_USED) ||\
691 (defined ICU_EMIOS_2_CH_29_ISR_USED) ||\
692 (defined ICU_EMIOS_2_CH_30_ISR_USED) ||\
693 (defined ICU_EMIOS_2_CH_31_ISR_USED) \
694 )
Emios_Icu_IrqHandler(const uint8 Instance,const uint8 Channel)695 static void Emios_Icu_IrqHandler(const uint8 Instance, const uint8 Channel)
696 {
697 /* Check that an event occurred on Emios channel */
698 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))
699 {
700 /* Check that an event occurred on EMIOS channel */
701 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))))
702 {
703 Emios_Icu_Ip_IrqHandler(Instance, Channel);
704 }
705 else
706 {
707 /* Do nothing - in case of spurious interrupts, return immediately */
708 }
709 }
710 }
711 #endif
712
713 #if (\
714 (defined OCU_EMIOS_0_CH_0_ISR_USED) ||\
715 (defined OCU_EMIOS_0_CH_1_ISR_USED) ||\
716 (defined OCU_EMIOS_0_CH_2_ISR_USED) ||\
717 (defined OCU_EMIOS_0_CH_3_ISR_USED) ||\
718 (defined OCU_EMIOS_0_CH_4_ISR_USED) ||\
719 (defined OCU_EMIOS_0_CH_5_ISR_USED) ||\
720 (defined OCU_EMIOS_0_CH_6_ISR_USED) ||\
721 (defined OCU_EMIOS_0_CH_7_ISR_USED) ||\
722 (defined OCU_EMIOS_0_CH_16_ISR_USED) ||\
723 (defined OCU_EMIOS_0_CH_17_ISR_USED) ||\
724 (defined OCU_EMIOS_0_CH_18_ISR_USED) ||\
725 (defined OCU_EMIOS_0_CH_19_ISR_USED) ||\
726 (defined OCU_EMIOS_0_CH_20_ISR_USED) ||\
727 (defined OCU_EMIOS_0_CH_21_ISR_USED) ||\
728 (defined OCU_EMIOS_0_CH_22_ISR_USED) ||\
729 (defined OCU_EMIOS_0_CH_23_ISR_USED) ||\
730 (defined OCU_EMIOS_0_CH_24_ISR_USED) ||\
731 (defined OCU_EMIOS_0_CH_25_ISR_USED) ||\
732 (defined OCU_EMIOS_0_CH_26_ISR_USED) ||\
733 (defined OCU_EMIOS_0_CH_27_ISR_USED) ||\
734 (defined OCU_EMIOS_0_CH_28_ISR_USED) ||\
735 (defined OCU_EMIOS_0_CH_29_ISR_USED) ||\
736 (defined OCU_EMIOS_0_CH_30_ISR_USED) ||\
737 (defined OCU_EMIOS_0_CH_31_ISR_USED) ||\
738 (defined OCU_EMIOS_1_CH_0_ISR_USED) ||\
739 (defined OCU_EMIOS_1_CH_1_ISR_USED) ||\
740 (defined OCU_EMIOS_1_CH_2_ISR_USED) ||\
741 (defined OCU_EMIOS_1_CH_3_ISR_USED) ||\
742 (defined OCU_EMIOS_1_CH_4_ISR_USED) ||\
743 (defined OCU_EMIOS_1_CH_5_ISR_USED) ||\
744 (defined OCU_EMIOS_1_CH_6_ISR_USED) ||\
745 (defined OCU_EMIOS_1_CH_7_ISR_USED) ||\
746 (defined OCU_EMIOS_1_CH_16_ISR_USED) ||\
747 (defined OCU_EMIOS_1_CH_17_ISR_USED) ||\
748 (defined OCU_EMIOS_1_CH_18_ISR_USED) ||\
749 (defined OCU_EMIOS_1_CH_19_ISR_USED) ||\
750 (defined OCU_EMIOS_1_CH_20_ISR_USED) ||\
751 (defined OCU_EMIOS_1_CH_21_ISR_USED) ||\
752 (defined OCU_EMIOS_1_CH_22_ISR_USED) ||\
753 (defined OCU_EMIOS_1_CH_23_ISR_USED) ||\
754 (defined OCU_EMIOS_1_CH_24_ISR_USED) ||\
755 (defined OCU_EMIOS_1_CH_25_ISR_USED) ||\
756 (defined OCU_EMIOS_1_CH_26_ISR_USED) ||\
757 (defined OCU_EMIOS_1_CH_27_ISR_USED) ||\
758 (defined OCU_EMIOS_1_CH_28_ISR_USED) ||\
759 (defined OCU_EMIOS_1_CH_29_ISR_USED) ||\
760 (defined OCU_EMIOS_1_CH_30_ISR_USED) ||\
761 (defined OCU_EMIOS_1_CH_31_ISR_USED) ||\
762 (defined OCU_EMIOS_2_CH_0_ISR_USED) ||\
763 (defined OCU_EMIOS_2_CH_1_ISR_USED) ||\
764 (defined OCU_EMIOS_2_CH_2_ISR_USED) ||\
765 (defined OCU_EMIOS_2_CH_3_ISR_USED) ||\
766 (defined OCU_EMIOS_2_CH_4_ISR_USED) ||\
767 (defined OCU_EMIOS_2_CH_5_ISR_USED) ||\
768 (defined OCU_EMIOS_2_CH_6_ISR_USED) ||\
769 (defined OCU_EMIOS_2_CH_7_ISR_USED) ||\
770 (defined OCU_EMIOS_2_CH_8_ISR_USED) ||\
771 (defined OCU_EMIOS_2_CH_9_ISR_USED) ||\
772 (defined OCU_EMIOS_2_CH_10_ISR_USED) ||\
773 (defined OCU_EMIOS_2_CH_11_ISR_USED) ||\
774 (defined OCU_EMIOS_2_CH_12_ISR_USED) ||\
775 (defined OCU_EMIOS_2_CH_13_ISR_USED) ||\
776 (defined OCU_EMIOS_2_CH_14_ISR_USED) ||\
777 (defined OCU_EMIOS_2_CH_15_ISR_USED) ||\
778 (defined OCU_EMIOS_2_CH_16_ISR_USED) ||\
779 (defined OCU_EMIOS_2_CH_17_ISR_USED) ||\
780 (defined OCU_EMIOS_2_CH_18_ISR_USED) ||\
781 (defined OCU_EMIOS_2_CH_19_ISR_USED) ||\
782 (defined OCU_EMIOS_2_CH_20_ISR_USED) ||\
783 (defined OCU_EMIOS_2_CH_21_ISR_USED) ||\
784 (defined OCU_EMIOS_2_CH_22_ISR_USED) ||\
785 (defined OCU_EMIOS_2_CH_23_ISR_USED) ||\
786 (defined OCU_EMIOS_2_CH_24_ISR_USED) ||\
787 (defined OCU_EMIOS_2_CH_25_ISR_USED) ||\
788 (defined OCU_EMIOS_2_CH_26_ISR_USED) ||\
789 (defined OCU_EMIOS_2_CH_27_ISR_USED) ||\
790 (defined OCU_EMIOS_2_CH_28_ISR_USED) ||\
791 (defined OCU_EMIOS_2_CH_29_ISR_USED) ||\
792 (defined OCU_EMIOS_2_CH_30_ISR_USED) ||\
793 (defined OCU_EMIOS_2_CH_31_ISR_USED) \
794 )
Emios_Ocu_IrqHandler(const uint8 Instance,const uint8 Channel)795 static void Emios_Ocu_IrqHandler(const uint8 Instance, const uint8 Channel)
796 {
797 /* Check that an event occurred on Emios channel */
798 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))
799 {
800 /* Check that an event occurred on EMIOS channel */
801 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))))
802 {
803 Emios_Ocu_Ip_IrqHandler(Instance, Channel);
804 }
805 else
806 {
807 /* Do nothing - in case of spurious interrupts, return immediately */
808 }
809 }
810 }
811 #endif
812
813 #if (\
814 (defined PWM_EMIOS_0_CH_0_ISR_USED) ||\
815 (defined PWM_EMIOS_0_CH_1_ISR_USED) ||\
816 (defined PWM_EMIOS_0_CH_2_ISR_USED) ||\
817 (defined PWM_EMIOS_0_CH_3_ISR_USED) ||\
818 (defined PWM_EMIOS_0_CH_4_ISR_USED) ||\
819 (defined PWM_EMIOS_0_CH_5_ISR_USED) ||\
820 (defined PWM_EMIOS_0_CH_6_ISR_USED) ||\
821 (defined PWM_EMIOS_0_CH_7_ISR_USED) ||\
822 (defined PWM_EMIOS_0_CH_16_ISR_USED) ||\
823 (defined PWM_EMIOS_0_CH_17_ISR_USED) ||\
824 (defined PWM_EMIOS_0_CH_18_ISR_USED) ||\
825 (defined PWM_EMIOS_0_CH_19_ISR_USED) ||\
826 (defined PWM_EMIOS_0_CH_20_ISR_USED) ||\
827 (defined PWM_EMIOS_0_CH_21_ISR_USED) ||\
828 (defined PWM_EMIOS_0_CH_22_ISR_USED) ||\
829 (defined PWM_EMIOS_0_CH_23_ISR_USED) ||\
830 (defined PWM_EMIOS_0_CH_24_ISR_USED) ||\
831 (defined PWM_EMIOS_0_CH_25_ISR_USED) ||\
832 (defined PWM_EMIOS_0_CH_26_ISR_USED) ||\
833 (defined PWM_EMIOS_0_CH_27_ISR_USED) ||\
834 (defined PWM_EMIOS_0_CH_28_ISR_USED) ||\
835 (defined PWM_EMIOS_0_CH_29_ISR_USED) ||\
836 (defined PWM_EMIOS_0_CH_30_ISR_USED) ||\
837 (defined PWM_EMIOS_0_CH_31_ISR_USED) ||\
838 (defined PWM_EMIOS_1_CH_0_ISR_USED) ||\
839 (defined PWM_EMIOS_1_CH_1_ISR_USED) ||\
840 (defined PWM_EMIOS_1_CH_2_ISR_USED) ||\
841 (defined PWM_EMIOS_1_CH_3_ISR_USED) ||\
842 (defined PWM_EMIOS_1_CH_4_ISR_USED) ||\
843 (defined PWM_EMIOS_1_CH_5_ISR_USED) ||\
844 (defined PWM_EMIOS_1_CH_6_ISR_USED) ||\
845 (defined PWM_EMIOS_1_CH_7_ISR_USED) ||\
846 (defined PWM_EMIOS_1_CH_16_ISR_USED) ||\
847 (defined PWM_EMIOS_1_CH_17_ISR_USED) ||\
848 (defined PWM_EMIOS_1_CH_18_ISR_USED) ||\
849 (defined PWM_EMIOS_1_CH_19_ISR_USED) ||\
850 (defined PWM_EMIOS_1_CH_20_ISR_USED) ||\
851 (defined PWM_EMIOS_1_CH_21_ISR_USED) ||\
852 (defined PWM_EMIOS_1_CH_22_ISR_USED) ||\
853 (defined PWM_EMIOS_1_CH_23_ISR_USED) ||\
854 (defined PWM_EMIOS_1_CH_24_ISR_USED) ||\
855 (defined PWM_EMIOS_1_CH_25_ISR_USED) ||\
856 (defined PWM_EMIOS_1_CH_26_ISR_USED) ||\
857 (defined PWM_EMIOS_1_CH_27_ISR_USED) ||\
858 (defined PWM_EMIOS_1_CH_28_ISR_USED) ||\
859 (defined PWM_EMIOS_1_CH_29_ISR_USED) ||\
860 (defined PWM_EMIOS_1_CH_30_ISR_USED) ||\
861 (defined PWM_EMIOS_1_CH_31_ISR_USED) ||\
862 (defined PWM_EMIOS_2_CH_0_ISR_USED) ||\
863 (defined PWM_EMIOS_2_CH_1_ISR_USED) ||\
864 (defined PWM_EMIOS_2_CH_2_ISR_USED) ||\
865 (defined PWM_EMIOS_2_CH_3_ISR_USED) ||\
866 (defined PWM_EMIOS_2_CH_4_ISR_USED) ||\
867 (defined PWM_EMIOS_2_CH_5_ISR_USED) ||\
868 (defined PWM_EMIOS_2_CH_6_ISR_USED) ||\
869 (defined PWM_EMIOS_2_CH_7_ISR_USED) ||\
870 (defined PWM_EMIOS_2_CH_8_ISR_USED) ||\
871 (defined PWM_EMIOS_2_CH_9_ISR_USED) ||\
872 (defined PWM_EMIOS_2_CH_10_ISR_USED) ||\
873 (defined PWM_EMIOS_2_CH_11_ISR_USED) ||\
874 (defined PWM_EMIOS_2_CH_12_ISR_USED) ||\
875 (defined PWM_EMIOS_2_CH_13_ISR_USED) ||\
876 (defined PWM_EMIOS_2_CH_14_ISR_USED) ||\
877 (defined PWM_EMIOS_2_CH_15_ISR_USED) ||\
878 (defined PWM_EMIOS_2_CH_16_ISR_USED) ||\
879 (defined PWM_EMIOS_2_CH_17_ISR_USED) ||\
880 (defined PWM_EMIOS_2_CH_18_ISR_USED) ||\
881 (defined PWM_EMIOS_2_CH_19_ISR_USED) ||\
882 (defined PWM_EMIOS_2_CH_20_ISR_USED) ||\
883 (defined PWM_EMIOS_2_CH_21_ISR_USED) ||\
884 (defined PWM_EMIOS_2_CH_22_ISR_USED) ||\
885 (defined PWM_EMIOS_2_CH_23_ISR_USED) ||\
886 (defined PWM_EMIOS_2_CH_24_ISR_USED) ||\
887 (defined PWM_EMIOS_2_CH_25_ISR_USED) ||\
888 (defined PWM_EMIOS_2_CH_26_ISR_USED) ||\
889 (defined PWM_EMIOS_2_CH_27_ISR_USED) ||\
890 (defined PWM_EMIOS_2_CH_28_ISR_USED) ||\
891 (defined PWM_EMIOS_2_CH_29_ISR_USED) ||\
892 (defined PWM_EMIOS_2_CH_30_ISR_USED) ||\
893 (defined PWM_EMIOS_2_CH_31_ISR_USED) \
894 )
Emios_Pwm_IrqHandler(const uint8 Instance,const uint8 Channel)895 static void Emios_Pwm_IrqHandler(const uint8 Instance, const uint8 Channel)
896 {
897 /* Check that an event occurred on Emios channel */
898 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))
899 {
900 /* Check that an event occurred on EMIOS channel */
901 if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))))
902 {
903 Emios_Pwm_Ip_IrqHandler(Instance, Channel);
904 }
905 else
906 {
907 /* Do nothing - in case of spurious interrupts, return immediately */
908 }
909 }
910 }
911 #endif
912 #if (\
913 (defined GPT_EMIOS_0_CH_8_ISR_USED) ||\
914 (defined GPT_EMIOS_0_CH_10_ISR_USED) ||\
915 (defined GPT_EMIOS_0_CH_12_ISR_USED) ||\
916 (defined GPT_EMIOS_0_CH_14_ISR_USED) ||\
917 (defined GPT_EMIOS_1_CH_8_ISR_USED) ||\
918 (defined GPT_EMIOS_1_CH_10_ISR_USED) ||\
919 (defined GPT_EMIOS_1_CH_12_ISR_USED) ||\
920 (defined GPT_EMIOS_1_CH_14_ISR_USED) \
921 )
Emios_Gpt_Wsc_IrqHandler(const uint8 Instance,const uint8 Channel)922 static void Emios_Gpt_Wsc_IrqHandler(const uint8 Instance, const uint8 Channel)
923 {
924 uint32 u32WsChannelFlag = eMIOS_WSS_FLAGCAP_MASK | eMIOS_WSS_FLAGCE_MASK | eMIOS_WSS_FLAGECO_MASK | eMIOS_WSS_FLAGPWO_MASK | eMIOS_WSS_FLAGPW_MASK | eMIOS_WSS_FLAGFF_MASK;
925
926 /* Check that an event occurred on Emios wheel speed channel */
927 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSS) & (uint32)u32WsChannelFlag))
928 {
929 /* Check that an event occurred on EMIOS wheel speed channel */
930 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK)))
931 {
932 Emios_Gpt_Ip_IrqHandler(Instance, Channel);
933 }
934 else
935 {
936 /* Do nothing - in case of spurious interrupts, return immediately */
937 }
938 }
939 }
940 #endif
941
942 #if (\
943 (defined ICU_EMIOS_0_CH_8_ISR_USED) ||\
944 (defined ICU_EMIOS_0_CH_10_ISR_USED) ||\
945 (defined ICU_EMIOS_0_CH_12_ISR_USED) ||\
946 (defined ICU_EMIOS_0_CH_14_ISR_USED) ||\
947 (defined ICU_EMIOS_1_CH_8_ISR_USED) ||\
948 (defined ICU_EMIOS_1_CH_10_ISR_USED) ||\
949 (defined ICU_EMIOS_1_CH_12_ISR_USED) ||\
950 (defined ICU_EMIOS_1_CH_14_ISR_USED) \
951 )
Emios_Icu_Wsc_IrqHandler(const uint8 Instance,const uint8 Channel)952 static void Emios_Icu_Wsc_IrqHandler(const uint8 Instance, const uint8 Channel)
953 {
954 uint32 u32WsChannelFlag = eMIOS_WSS_FLAGCAP_MASK | eMIOS_WSS_FLAGCE_MASK | eMIOS_WSS_FLAGECO_MASK | eMIOS_WSS_FLAGPWO_MASK | eMIOS_WSS_FLAGPW_MASK | eMIOS_WSS_FLAGFF_MASK;
955
956 /* Check that an event occurred on Emios wheel speed channel */
957 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSS) & (uint32)u32WsChannelFlag))
958 {
959 /* Check that an event occurred on EMIOS wheel speed channel */
960 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK)))
961 {
962 Emios_Icu_Ip_IrqHandler(Instance, Channel);
963 }
964 else
965 {
966 /* Do nothing - in case of spurious interrupts, return immediately */
967 }
968 }
969 }
970 #endif
971
972 #if (\
973 (defined OCU_EMIOS_0_CH_8_ISR_USED) ||\
974 (defined OCU_EMIOS_0_CH_10_ISR_USED) ||\
975 (defined OCU_EMIOS_0_CH_12_ISR_USED) ||\
976 (defined OCU_EMIOS_0_CH_14_ISR_USED) ||\
977 (defined OCU_EMIOS_1_CH_8_ISR_USED) ||\
978 (defined OCU_EMIOS_1_CH_10_ISR_USED) ||\
979 (defined OCU_EMIOS_1_CH_12_ISR_USED) ||\
980 (defined OCU_EMIOS_1_CH_14_ISR_USED) \
981 )
Emios_Ocu_Wsc_IrqHandler(const uint8 Instance,const uint8 Channel)982 static void Emios_Ocu_Wsc_IrqHandler(const uint8 Instance, const uint8 Channel)
983 {
984 uint32 u32WsChannelFlag = eMIOS_WSS_FLAGCAP_MASK | eMIOS_WSS_FLAGCE_MASK | eMIOS_WSS_FLAGECO_MASK | eMIOS_WSS_FLAGPWO_MASK | eMIOS_WSS_FLAGPW_MASK | eMIOS_WSS_FLAGFF_MASK;
985
986 /* Check that an event occurred on Emios wheel speed channel */
987 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSS) & (uint32)u32WsChannelFlag))
988 {
989 /* Check that an event occurred on EMIOS wheel speed channel */
990 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK)))
991 {
992 Emios_Ocu_Ip_IrqHandler(Instance, Channel);
993 }
994 else
995 {
996 /* Do nothing - in case of spurious interrupts, return immediately */
997 }
998 }
999 }
1000 #endif
1001
1002 #if (\
1003 (defined PWM_EMIOS_0_CH_8_ISR_USED) ||\
1004 (defined PWM_EMIOS_0_CH_10_ISR_USED) ||\
1005 (defined PWM_EMIOS_0_CH_12_ISR_USED) ||\
1006 (defined PWM_EMIOS_0_CH_14_ISR_USED) ||\
1007 (defined PWM_EMIOS_1_CH_8_ISR_USED) ||\
1008 (defined PWM_EMIOS_1_CH_10_ISR_USED) ||\
1009 (defined PWM_EMIOS_1_CH_12_ISR_USED) ||\
1010 (defined PWM_EMIOS_1_CH_14_ISR_USED) \
1011 )
Emios_Pwm_Wsc_IrqHandler(const uint8 Instance,const uint8 Channel)1012 static void Emios_Pwm_Wsc_IrqHandler(const uint8 Instance, const uint8 Channel)
1013 {
1014 uint32 u32WsChannelFlag = eMIOS_WSS_FLAGCAP_MASK | eMIOS_WSS_FLAGCE_MASK | eMIOS_WSS_FLAGECO_MASK | eMIOS_WSS_FLAGPWO_MASK | eMIOS_WSS_FLAGPW_MASK | eMIOS_WSS_FLAGFF_MASK;
1015
1016 /* Check that an event occurred on Emios wheel speed channel */
1017 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSS) & (uint32)u32WsChannelFlag))
1018 {
1019 /* Check that an event occurred on EMIOS wheel speed channel */
1020 if (0U != ((Emios_Ip_paxBase[Instance]->CH.WSC[Channel/2].WSC1) & ((uint32)eMIOS_WSC1_FEN_MASK)))
1021 {
1022 Emios_Pwm_Ip_IrqHandler(Instance, Channel);
1023 }
1024 else
1025 {
1026 /* Do nothing - in case of spurious interrupts, return immediately */
1027 }
1028 }
1029 }
1030 #endif
1031 /*==================================================================================================
1032 * GLOBAL FUNCTIONS
1033 ==================================================================================================*/
1034
1035
1036 #if (\
1037 (defined GPT_EMIOS_0_CH_0_ISR_USED) ||\
1038 (defined ICU_EMIOS_0_CH_0_ISR_USED) ||\
1039 (defined OCU_EMIOS_0_CH_0_ISR_USED) ||\
1040 (defined PWM_EMIOS_0_CH_0_ISR_USED)\
1041 )
1042 /**
1043 * @brief Interrupt handler for EMIOS channel 0 for Emios instance 0
1044 * @details Process the interrupt of EMIOS channel 0
1045 *
1046 * @note This will be defined only if EMIOS channel 0 is configured in GPT, ICU,
1047 * OCU or PWM mode.
1048 */
ISR(EMIOS0_CH0_IRQ)1049 ISR(EMIOS0_CH0_IRQ)
1050 {
1051 #if (defined EMIOS_0_CH_0_ISR_USED)
1052 #if (defined GPT_EMIOS_0_CH_0_ISR_USED)
1053 Emios_Gpt_IrqHandler(0, 0);
1054 #endif
1055
1056 #if (defined ICU_EMIOS_0_CH_0_ISR_USED)
1057 Emios_Icu_IrqHandler(0, 0);
1058 #endif
1059
1060 #if (defined OCU_EMIOS_0_CH_0_ISR_USED)
1061 Emios_Ocu_IrqHandler(0, 0);
1062 #endif
1063
1064 #if (defined PWM_EMIOS_0_CH_0_ISR_USED)
1065 Emios_Pwm_IrqHandler(0, 0);
1066 #endif
1067 #endif
1068 }
1069 #endif
1070
1071 #if (\
1072 (defined GPT_EMIOS_0_CH_1_ISR_USED) ||\
1073 (defined ICU_EMIOS_0_CH_1_ISR_USED) ||\
1074 (defined OCU_EMIOS_0_CH_1_ISR_USED) ||\
1075 (defined PWM_EMIOS_0_CH_1_ISR_USED)\
1076 )
1077 /**
1078 * @brief Interrupt handler for EMIOS channel 1 for Emios instance 0
1079 * @details Process the interrupt of EMIOS channel 1
1080 *
1081 * @note This will be defined only if EMIOS channel 1 is configured in GPT, ICU,
1082 * OCU or PWM mode.
1083 */
ISR(EMIOS0_CH1_IRQ)1084 ISR(EMIOS0_CH1_IRQ)
1085 {
1086 #if (defined EMIOS_0_CH_1_ISR_USED)
1087 #if (defined GPT_EMIOS_0_CH_1_ISR_USED)
1088 Emios_Gpt_IrqHandler(0, 1);
1089 #endif
1090
1091 #if (defined ICU_EMIOS_0_CH_1_ISR_USED)
1092 Emios_Icu_IrqHandler(0, 1);
1093 #endif
1094
1095 #if (defined OCU_EMIOS_0_CH_1_ISR_USED)
1096 Emios_Ocu_IrqHandler(0, 1);
1097 #endif
1098
1099 #if (defined PWM_EMIOS_0_CH_1_ISR_USED)
1100 Emios_Pwm_IrqHandler(0, 1);
1101 #endif
1102 #endif
1103 }
1104 #endif
1105
1106 #if (\
1107 (defined GPT_EMIOS_0_CH_2_ISR_USED) ||\
1108 (defined ICU_EMIOS_0_CH_2_ISR_USED) ||\
1109 (defined OCU_EMIOS_0_CH_2_ISR_USED) ||\
1110 (defined PWM_EMIOS_0_CH_2_ISR_USED)\
1111 )
1112 /**
1113 * @brief Interrupt handler for EMIOS channel 2 for Emios instance 0
1114 * @details Process the interrupt of EMIOS channel 2
1115 *
1116 * @note This will be defined only if EMIOS channel 2 is configured in GPT, ICU,
1117 * OCU or PWM mode.
1118 */
ISR(EMIOS0_CH2_IRQ)1119 ISR(EMIOS0_CH2_IRQ)
1120 {
1121 #if (defined EMIOS_0_CH_2_ISR_USED)
1122 #if (defined GPT_EMIOS_0_CH_2_ISR_USED)
1123 Emios_Gpt_IrqHandler(0, 2);
1124 #endif
1125
1126 #if (defined ICU_EMIOS_0_CH_2_ISR_USED)
1127 Emios_Icu_IrqHandler(0, 2);
1128 #endif
1129
1130 #if (defined OCU_EMIOS_0_CH_2_ISR_USED)
1131 Emios_Ocu_IrqHandler(0, 2);
1132 #endif
1133
1134 #if (defined PWM_EMIOS_0_CH_2_ISR_USED)
1135 Emios_Pwm_IrqHandler(0, 2);
1136 #endif
1137 #endif
1138 }
1139 #endif
1140
1141 #if (\
1142 (defined GPT_EMIOS_0_CH_3_ISR_USED) ||\
1143 (defined ICU_EMIOS_0_CH_3_ISR_USED) ||\
1144 (defined OCU_EMIOS_0_CH_3_ISR_USED) ||\
1145 (defined PWM_EMIOS_0_CH_3_ISR_USED)\
1146 )
1147 /**
1148 * @brief Interrupt handler for EMIOS channel 3 for Emios instance 0
1149 * @details Process the interrupt of EMIOS channel 3
1150 *
1151 * @note This will be defined only if EMIOS channel 3 is configured in GPT, ICU,
1152 * OCU or PWM mode.
1153 */
ISR(EMIOS0_CH3_IRQ)1154 ISR(EMIOS0_CH3_IRQ)
1155 {
1156 #if (defined EMIOS_0_CH_3_ISR_USED)
1157 #if (defined GPT_EMIOS_0_CH_3_ISR_USED)
1158 Emios_Gpt_IrqHandler(0, 3);
1159 #endif
1160
1161 #if (defined ICU_EMIOS_0_CH_3_ISR_USED)
1162 Emios_Icu_IrqHandler(0, 3);
1163 #endif
1164
1165 #if (defined OCU_EMIOS_0_CH_3_ISR_USED)
1166 Emios_Ocu_IrqHandler(0, 3);
1167 #endif
1168
1169 #if (defined PWM_EMIOS_0_CH_3_ISR_USED)
1170 Emios_Pwm_IrqHandler(0, 3);
1171 #endif
1172 #endif
1173 }
1174 #endif
1175
1176 #if (\
1177 (defined GPT_EMIOS_0_CH_4_ISR_USED) ||\
1178 (defined ICU_EMIOS_0_CH_4_ISR_USED) ||\
1179 (defined OCU_EMIOS_0_CH_4_ISR_USED) ||\
1180 (defined PWM_EMIOS_0_CH_4_ISR_USED)\
1181 )
1182 /**
1183 * @brief Interrupt handler for EMIOS channel 4 for Emios instance 0
1184 * @details Process the interrupt of EMIOS channel 4
1185 *
1186 * @note This will be defined only if EMIOS channel 4 is configured in GPT, ICU,
1187 * OCU or PWM mode.
1188 */
ISR(EMIOS0_CH4_IRQ)1189 ISR(EMIOS0_CH4_IRQ)
1190 {
1191 #if (defined EMIOS_0_CH_4_ISR_USED)
1192 #if (defined GPT_EMIOS_0_CH_4_ISR_USED)
1193 Emios_Gpt_IrqHandler(0, 4);
1194 #endif
1195
1196 #if (defined ICU_EMIOS_0_CH_4_ISR_USED)
1197 Emios_Icu_IrqHandler(0, 4);
1198 #endif
1199
1200 #if (defined OCU_EMIOS_0_CH_4_ISR_USED)
1201 Emios_Ocu_IrqHandler(0, 4);
1202 #endif
1203
1204 #if (defined PWM_EMIOS_0_CH_4_ISR_USED)
1205 Emios_Pwm_IrqHandler(0, 4);
1206 #endif
1207 #endif
1208 }
1209 #endif
1210
1211 #if (\
1212 (defined GPT_EMIOS_0_CH_5_ISR_USED) ||\
1213 (defined ICU_EMIOS_0_CH_5_ISR_USED) ||\
1214 (defined OCU_EMIOS_0_CH_5_ISR_USED) ||\
1215 (defined PWM_EMIOS_0_CH_5_ISR_USED)\
1216 )
1217 /**
1218 * @brief Interrupt handler for EMIOS channel 5 for Emios instance 0
1219 * @details Process the interrupt of EMIOS channel 5
1220 *
1221 * @note This will be defined only if EMIOS channel 5 is configured in GPT, ICU,
1222 * OCU or PWM mode.
1223 */
ISR(EMIOS0_CH5_IRQ)1224 ISR(EMIOS0_CH5_IRQ)
1225 {
1226 #if (defined EMIOS_0_CH_5_ISR_USED)
1227 #if (defined GPT_EMIOS_0_CH_5_ISR_USED)
1228 Emios_Gpt_IrqHandler(0, 5);
1229 #endif
1230
1231 #if (defined ICU_EMIOS_0_CH_5_ISR_USED)
1232 Emios_Icu_IrqHandler(0, 5);
1233 #endif
1234
1235 #if (defined OCU_EMIOS_0_CH_5_ISR_USED)
1236 Emios_Ocu_IrqHandler(0, 5);
1237 #endif
1238
1239 #if (defined PWM_EMIOS_0_CH_5_ISR_USED)
1240 Emios_Pwm_IrqHandler(0, 5);
1241 #endif
1242 #endif
1243 }
1244 #endif
1245
1246 #if (\
1247 (defined GPT_EMIOS_0_CH_6_ISR_USED) ||\
1248 (defined ICU_EMIOS_0_CH_6_ISR_USED) ||\
1249 (defined OCU_EMIOS_0_CH_6_ISR_USED) ||\
1250 (defined PWM_EMIOS_0_CH_6_ISR_USED)\
1251 )
1252 /**
1253 * @brief Interrupt handler for EMIOS channel 6 for Emios instance 0
1254 * @details Process the interrupt of EMIOS channel 6
1255 *
1256 * @note This will be defined only if EMIOS channel 6 is configured in GPT, ICU,
1257 * OCU or PWM mode.
1258 */
ISR(EMIOS0_CH6_IRQ)1259 ISR(EMIOS0_CH6_IRQ)
1260 {
1261 #if (defined EMIOS_0_CH_6_ISR_USED)
1262 #if (defined GPT_EMIOS_0_CH_6_ISR_USED)
1263 Emios_Gpt_IrqHandler(0, 6);
1264 #endif
1265
1266 #if (defined ICU_EMIOS_0_CH_6_ISR_USED)
1267 Emios_Icu_IrqHandler(0, 6);
1268 #endif
1269
1270 #if (defined OCU_EMIOS_0_CH_6_ISR_USED)
1271 Emios_Ocu_IrqHandler(0, 6);
1272 #endif
1273
1274 #if (defined PWM_EMIOS_0_CH_6_ISR_USED)
1275 Emios_Pwm_IrqHandler(0, 6);
1276 #endif
1277 #endif
1278 }
1279 #endif
1280
1281 #if (\
1282 (defined GPT_EMIOS_0_CH_7_ISR_USED) ||\
1283 (defined ICU_EMIOS_0_CH_7_ISR_USED) ||\
1284 (defined OCU_EMIOS_0_CH_7_ISR_USED) ||\
1285 (defined PWM_EMIOS_0_CH_7_ISR_USED)\
1286 )
1287 /**
1288 * @brief Interrupt handler for EMIOS channel 7 for Emios instance 0
1289 * @details Process the interrupt of EMIOS channel 7
1290 *
1291 * @note This will be defined only if EMIOS channel 7 is configured in GPT, ICU,
1292 * OCU or PWM mode.
1293 */
ISR(EMIOS0_CH7_IRQ)1294 ISR(EMIOS0_CH7_IRQ)
1295 {
1296 #if (defined EMIOS_0_CH_7_ISR_USED)
1297 #if (defined GPT_EMIOS_0_CH_7_ISR_USED)
1298 Emios_Gpt_IrqHandler(0, 7);
1299 #endif
1300
1301 #if (defined ICU_EMIOS_0_CH_7_ISR_USED)
1302 Emios_Icu_IrqHandler(0, 7);
1303 #endif
1304
1305 #if (defined OCU_EMIOS_0_CH_7_ISR_USED)
1306 Emios_Ocu_IrqHandler(0, 7);
1307 #endif
1308
1309 #if (defined PWM_EMIOS_0_CH_7_ISR_USED)
1310 Emios_Pwm_IrqHandler(0, 7);
1311 #endif
1312 #endif
1313 }
1314 #endif
1315
1316 #if (\
1317 (defined GPT_EMIOS_0_CH_8_ISR_USED) ||\
1318 (defined ICU_EMIOS_0_CH_8_ISR_USED) ||\
1319 (defined OCU_EMIOS_0_CH_8_ISR_USED) ||\
1320 (defined PWM_EMIOS_0_CH_8_ISR_USED)\
1321 )
1322 /**
1323 * @brief Interrupt handler for EMIOS channel 8 for Emios instance 0
1324 * @details Process the interrupt of EMIOS channel 8
1325 *
1326 * @note This will be defined only if EMIOS channel 8 is configured in GPT, ICU,
1327 * OCU or PWM mode.
1328 */
ISR(EMIOS0_CH8_IRQ)1329 ISR(EMIOS0_CH8_IRQ)
1330 {
1331 #if (defined EMIOS_0_CH_8_ISR_USED)
1332 #if (defined GPT_EMIOS_0_CH_8_ISR_USED)
1333 Emios_Gpt_Wsc_IrqHandler(0, 8);
1334 #endif
1335
1336 #if (defined ICU_EMIOS_0_CH_8_ISR_USED)
1337 Emios_Icu_Wsc_IrqHandler(0, 8);
1338 #endif
1339
1340 #if (defined OCU_EMIOS_0_CH_8_ISR_USED)
1341 Emios_Ocu_Wsc_IrqHandler(0, 8);
1342 #endif
1343
1344 #if (defined PWM_EMIOS_0_CH_8_ISR_USED)
1345 Emios_Pwm_Wsc_IrqHandler(0, 8);
1346 #endif
1347 #endif
1348 }
1349 #endif
1350
1351 #if (\
1352 (defined GPT_EMIOS_0_CH_9_ISR_USED) ||\
1353 (defined ICU_EMIOS_0_CH_9_ISR_USED) ||\
1354 (defined OCU_EMIOS_0_CH_9_ISR_USED) ||\
1355 (defined PWM_EMIOS_0_CH_9_ISR_USED)\
1356 )
1357 /**
1358 * @brief Interrupt handler for EMIOS channel 9 for Emios instance 0
1359 * @details Process the interrupt of EMIOS channel 9
1360 *
1361 * @note This will be defined only if EMIOS channel 9 is configured in GPT, ICU,
1362 * OCU or PWM mode.
1363 */
ISR(EMIOS0_CH9_IRQ)1364 ISR(EMIOS0_CH9_IRQ)
1365 {
1366 #if (defined EMIOS_0_CH_9_ISR_USED)
1367 #if (defined GPT_EMIOS_0_CH_9_ISR_USED)
1368 Emios_Gpt_IrqHandler(0, 9);
1369 #endif
1370
1371 #if (defined ICU_EMIOS_0_CH_9_ISR_USED)
1372 Emios_Icu_IrqHandler(0, 9);
1373 #endif
1374
1375 #if (defined OCU_EMIOS_0_CH_9_ISR_USED)
1376 Emios_Ocu_IrqHandler(0, 9);
1377 #endif
1378
1379 #if (defined PWM_EMIOS_0_CH_9_ISR_USED)
1380 Emios_Pwm_IrqHandler(0, 9);
1381 #endif
1382 #endif
1383 }
1384 #endif
1385
1386 #if (\
1387 (defined GPT_EMIOS_0_CH_10_ISR_USED) ||\
1388 (defined ICU_EMIOS_0_CH_10_ISR_USED) ||\
1389 (defined OCU_EMIOS_0_CH_10_ISR_USED) ||\
1390 (defined PWM_EMIOS_0_CH_10_ISR_USED)\
1391 )
1392 /**
1393 * @brief Interrupt handler for EMIOS channel 10 for Emios instance 0
1394 * @details Process the interrupt of EMIOS channel 10
1395 *
1396 * @note This will be defined only if EMIOS channel 10 is configured in GPT, ICU,
1397 * OCU or PWM mode.
1398 */
ISR(EMIOS0_CH10_IRQ)1399 ISR(EMIOS0_CH10_IRQ)
1400 {
1401 #if (defined EMIOS_0_CH_10_ISR_USED)
1402 #if (defined GPT_EMIOS_0_CH_10_ISR_USED)
1403 Emios_Gpt_Wsc_IrqHandler(0, 10);
1404 #endif
1405
1406 #if (defined ICU_EMIOS_0_CH_10_ISR_USED)
1407 Emios_Icu_Wsc_IrqHandler(0, 10);
1408 #endif
1409
1410 #if (defined OCU_EMIOS_0_CH_10_ISR_USED)
1411 Emios_Ocu_Wsc_IrqHandler(0, 10);
1412 #endif
1413
1414 #if (defined PWM_EMIOS_0_CH_10_ISR_USED)
1415 Emios_Pwm_Wsc_IrqHandler(0, 10);
1416 #endif
1417 #endif
1418 }
1419 #endif
1420
1421 #if (\
1422 (defined GPT_EMIOS_0_CH_11_ISR_USED) ||\
1423 (defined ICU_EMIOS_0_CH_11_ISR_USED) ||\
1424 (defined OCU_EMIOS_0_CH_11_ISR_USED) ||\
1425 (defined PWM_EMIOS_0_CH_11_ISR_USED)\
1426 )
1427 /**
1428 * @brief Interrupt handler for EMIOS channel 11 for Emios instance 0
1429 * @details Process the interrupt of EMIOS channel 11
1430 *
1431 * @note This will be defined only if EMIOS channel 11 is configured in GPT, ICU,
1432 * OCU or PWM mode.
1433 */
ISR(EMIOS0_CH11_IRQ)1434 ISR(EMIOS0_CH11_IRQ)
1435 {
1436 #if (defined EMIOS_0_CH_11_ISR_USED)
1437 #if (defined GPT_EMIOS_0_CH_11_ISR_USED)
1438 Emios_Gpt_IrqHandler(0, 11);
1439 #endif
1440
1441 #if (defined ICU_EMIOS_0_CH_11_ISR_USED)
1442 Emios_Icu_IrqHandler(0, 11);
1443 #endif
1444
1445 #if (defined OCU_EMIOS_0_CH_11_ISR_USED)
1446 Emios_Ocu_IrqHandler(0, 11);
1447 #endif
1448
1449 #if (defined PWM_EMIOS_0_CH_11_ISR_USED)
1450 Emios_Pwm_IrqHandler(0, 11);
1451 #endif
1452 #endif
1453 }
1454 #endif
1455
1456 #if (\
1457 (defined GPT_EMIOS_0_CH_12_ISR_USED) ||\
1458 (defined ICU_EMIOS_0_CH_12_ISR_USED) ||\
1459 (defined OCU_EMIOS_0_CH_12_ISR_USED) ||\
1460 (defined PWM_EMIOS_0_CH_12_ISR_USED)\
1461 )
1462 /**
1463 * @brief Interrupt handler for EMIOS channel 12 for Emios instance 0
1464 * @details Process the interrupt of EMIOS channel 12
1465 *
1466 * @note This will be defined only if EMIOS channel 12 is configured in GPT, ICU,
1467 * OCU or PWM mode.
1468 */
ISR(EMIOS0_CH12_IRQ)1469 ISR(EMIOS0_CH12_IRQ)
1470 {
1471 #if (defined EMIOS_0_CH_12_ISR_USED)
1472 #if (defined GPT_EMIOS_0_CH_12_ISR_USED)
1473 Emios_Gpt_Wsc_IrqHandler(0, 12);
1474 #endif
1475
1476 #if (defined ICU_EMIOS_0_CH_12_ISR_USED)
1477 Emios_Icu_Wsc_IrqHandler(0, 12);
1478 #endif
1479
1480 #if (defined OCU_EMIOS_0_CH_12_ISR_USED)
1481 Emios_Ocu_Wsc_IrqHandler(0, 12);
1482 #endif
1483
1484 #if (defined PWM_EMIOS_0_CH_12_ISR_USED)
1485 Emios_Pwm_Wsc_IrqHandler(0, 12);
1486 #endif
1487 #endif
1488 }
1489 #endif
1490
1491 #if (\
1492 (defined GPT_EMIOS_0_CH_13_ISR_USED) ||\
1493 (defined ICU_EMIOS_0_CH_13_ISR_USED) ||\
1494 (defined OCU_EMIOS_0_CH_13_ISR_USED) ||\
1495 (defined PWM_EMIOS_0_CH_13_ISR_USED)\
1496 )
1497 /**
1498 * @brief Interrupt handler for EMIOS channel 13 for Emios instance 0
1499 * @details Process the interrupt of EMIOS channel 13
1500 *
1501 * @note This will be defined only if EMIOS channel 13 is configured in GPT, ICU,
1502 * OCU or PWM mode.
1503 */
ISR(EMIOS0_CH13_IRQ)1504 ISR(EMIOS0_CH13_IRQ)
1505 {
1506 #if (defined EMIOS_0_CH_13_ISR_USED)
1507 #if (defined GPT_EMIOS_0_CH_13_ISR_USED)
1508 Emios_Gpt_IrqHandler(0, 13);
1509 #endif
1510
1511 #if (defined ICU_EMIOS_0_CH_13_ISR_USED)
1512 Emios_Icu_IrqHandler(0, 13);
1513 #endif
1514
1515 #if (defined OCU_EMIOS_0_CH_13_ISR_USED)
1516 Emios_Ocu_IrqHandler(0, 13);
1517 #endif
1518
1519 #if (defined PWM_EMIOS_0_CH_13_ISR_USED)
1520 Emios_Pwm_IrqHandler(0, 13);
1521 #endif
1522 #endif
1523 }
1524 #endif
1525
1526 #if (\
1527 (defined GPT_EMIOS_0_CH_14_ISR_USED) ||\
1528 (defined ICU_EMIOS_0_CH_14_ISR_USED) ||\
1529 (defined OCU_EMIOS_0_CH_14_ISR_USED) ||\
1530 (defined PWM_EMIOS_0_CH_14_ISR_USED)\
1531 )
1532 /**
1533 * @brief Interrupt handler for EMIOS channel 14 for Emios instance 0
1534 * @details Process the interrupt of EMIOS channel 14
1535 *
1536 * @note This will be defined only if EMIOS channel 14 is configured in GPT, ICU,
1537 * OCU or PWM mode.
1538 */
ISR(EMIOS0_CH14_IRQ)1539 ISR(EMIOS0_CH14_IRQ)
1540 {
1541 #if (defined EMIOS_0_CH_14_ISR_USED)
1542 #if (defined GPT_EMIOS_0_CH_14_ISR_USED)
1543 Emios_Gpt_Wsc_IrqHandler(0, 14);
1544 #endif
1545
1546 #if (defined ICU_EMIOS_0_CH_14_ISR_USED)
1547 Emios_Icu_Wsc_IrqHandler(0, 14);
1548 #endif
1549
1550 #if (defined OCU_EMIOS_0_CH_14_ISR_USED)
1551 Emios_Ocu_Wsc_IrqHandler(0, 14);
1552 #endif
1553
1554 #if (defined PWM_EMIOS_0_CH_14_ISR_USED)
1555 Emios_Pwm_Wsc_IrqHandler(0, 14);
1556 #endif
1557 #endif
1558 }
1559 #endif
1560
1561 #if (\
1562 (defined GPT_EMIOS_0_CH_15_ISR_USED) ||\
1563 (defined ICU_EMIOS_0_CH_15_ISR_USED) ||\
1564 (defined OCU_EMIOS_0_CH_15_ISR_USED) ||\
1565 (defined PWM_EMIOS_0_CH_15_ISR_USED)\
1566 )
1567 /**
1568 * @brief Interrupt handler for EMIOS channel 15 for Emios instance 0
1569 * @details Process the interrupt of EMIOS channel 15
1570 *
1571 * @note This will be defined only if EMIOS channel 15 is configured in GPT, ICU,
1572 * OCU or PWM mode.
1573 */
ISR(EMIOS0_CH15_IRQ)1574 ISR(EMIOS0_CH15_IRQ)
1575 {
1576 #if (defined EMIOS_0_CH_15_ISR_USED)
1577 #if (defined GPT_EMIOS_0_CH_15_ISR_USED)
1578 Emios_Gpt_IrqHandler(0, 15);
1579 #endif
1580
1581 #if (defined ICU_EMIOS_0_CH_15_ISR_USED)
1582 Emios_Icu_IrqHandler(0, 15);
1583 #endif
1584
1585 #if (defined OCU_EMIOS_0_CH_15_ISR_USED)
1586 Emios_Ocu_IrqHandler(0, 15);
1587 #endif
1588
1589 #if (defined PWM_EMIOS_0_CH_15_ISR_USED)
1590 Emios_Pwm_IrqHandler(0, 15);
1591 #endif
1592 #endif
1593 }
1594 #endif
1595
1596 #if (\
1597 (defined GPT_EMIOS_0_CH_16_ISR_USED) ||\
1598 (defined ICU_EMIOS_0_CH_16_ISR_USED) ||\
1599 (defined OCU_EMIOS_0_CH_16_ISR_USED) ||\
1600 (defined PWM_EMIOS_0_CH_16_ISR_USED)\
1601 )
1602 /**
1603 * @brief Interrupt handler for EMIOS channel 16 for Emios instance 0
1604 * @details Process the interrupt of EMIOS channel 16
1605 *
1606 * @note This will be defined only if EMIOS channel 16 is configured in GPT, ICU,
1607 * OCU or PWM mode.
1608 */
ISR(EMIOS0_CH16_IRQ)1609 ISR(EMIOS0_CH16_IRQ)
1610 {
1611 #if (defined EMIOS_0_CH_16_ISR_USED)
1612 #if (defined GPT_EMIOS_0_CH_16_ISR_USED)
1613 Emios_Gpt_IrqHandler(0, 16);
1614 #endif
1615
1616 #if (defined ICU_EMIOS_0_CH_16_ISR_USED)
1617 Emios_Icu_IrqHandler(0, 16);
1618 #endif
1619
1620 #if (defined OCU_EMIOS_0_CH_16_ISR_USED)
1621 Emios_Ocu_IrqHandler(0, 16);
1622 #endif
1623
1624 #if (defined PWM_EMIOS_0_CH_16_ISR_USED)
1625 Emios_Pwm_IrqHandler(0, 16);
1626 #endif
1627 #endif
1628 }
1629 #endif
1630
1631 #if (\
1632 (defined GPT_EMIOS_0_CH_17_ISR_USED) ||\
1633 (defined ICU_EMIOS_0_CH_17_ISR_USED) ||\
1634 (defined OCU_EMIOS_0_CH_17_ISR_USED) ||\
1635 (defined PWM_EMIOS_0_CH_17_ISR_USED)\
1636 )
1637 /**
1638 * @brief Interrupt handler for EMIOS channel 17 for Emios instance 0
1639 * @details Process the interrupt of EMIOS channel 17
1640 *
1641 * @note This will be defined only if EMIOS channel 17 is configured in GPT, ICU,
1642 * OCU or PWM mode.
1643 */
ISR(EMIOS0_CH17_IRQ)1644 ISR(EMIOS0_CH17_IRQ)
1645 {
1646 #if (defined EMIOS_0_CH_17_ISR_USED)
1647 #if (defined GPT_EMIOS_0_CH_17_ISR_USED)
1648 Emios_Gpt_IrqHandler(0, 17);
1649 #endif
1650
1651 #if (defined ICU_EMIOS_0_CH_17_ISR_USED)
1652 Emios_Icu_IrqHandler(0, 17);
1653 #endif
1654
1655 #if (defined OCU_EMIOS_0_CH_17_ISR_USED)
1656 Emios_Ocu_IrqHandler(0, 17);
1657 #endif
1658
1659 #if (defined PWM_EMIOS_0_CH_17_ISR_USED)
1660 Emios_Pwm_IrqHandler(0, 17);
1661 #endif
1662 #endif
1663 }
1664 #endif
1665
1666 #if (\
1667 (defined GPT_EMIOS_0_CH_18_ISR_USED) ||\
1668 (defined ICU_EMIOS_0_CH_18_ISR_USED) ||\
1669 (defined OCU_EMIOS_0_CH_18_ISR_USED) ||\
1670 (defined PWM_EMIOS_0_CH_18_ISR_USED)\
1671 )
1672 /**
1673 * @brief Interrupt handler for EMIOS channel 18 for Emios instance 0
1674 * @details Process the interrupt of EMIOS channel 18
1675 *
1676 * @note This will be defined only if EMIOS channel 18 is configured in GPT, ICU,
1677 * OCU or PWM mode.
1678 */
ISR(EMIOS0_CH18_IRQ)1679 ISR(EMIOS0_CH18_IRQ)
1680 {
1681 #if (defined EMIOS_0_CH_18_ISR_USED)
1682 #if (defined GPT_EMIOS_0_CH_18_ISR_USED)
1683 Emios_Gpt_IrqHandler(0, 18);
1684 #endif
1685
1686 #if (defined ICU_EMIOS_0_CH_18_ISR_USED)
1687 Emios_Icu_IrqHandler(0, 18);
1688 #endif
1689
1690 #if (defined OCU_EMIOS_0_CH_18_ISR_USED)
1691 Emios_Ocu_IrqHandler(0, 18);
1692 #endif
1693
1694 #if (defined PWM_EMIOS_0_CH_18_ISR_USED)
1695 Emios_Pwm_IrqHandler(0, 18);
1696 #endif
1697 #endif
1698 }
1699 #endif
1700
1701 #if (\
1702 (defined GPT_EMIOS_0_CH_19_ISR_USED) ||\
1703 (defined ICU_EMIOS_0_CH_19_ISR_USED) ||\
1704 (defined OCU_EMIOS_0_CH_19_ISR_USED) ||\
1705 (defined PWM_EMIOS_0_CH_19_ISR_USED)\
1706 )
1707 /**
1708 * @brief Interrupt handler for EMIOS channel 19 for Emios instance 0
1709 * @details Process the interrupt of EMIOS channel 19
1710 *
1711 * @note This will be defined only if EMIOS channel 19 is configured in GPT, ICU,
1712 * OCU or PWM mode.
1713 */
ISR(EMIOS0_CH19_IRQ)1714 ISR(EMIOS0_CH19_IRQ)
1715 {
1716 #if (defined EMIOS_0_CH_19_ISR_USED)
1717 #if (defined GPT_EMIOS_0_CH_19_ISR_USED)
1718 Emios_Gpt_IrqHandler(0, 19);
1719 #endif
1720
1721 #if (defined ICU_EMIOS_0_CH_19_ISR_USED)
1722 Emios_Icu_IrqHandler(0, 19);
1723 #endif
1724
1725 #if (defined OCU_EMIOS_0_CH_19_ISR_USED)
1726 Emios_Ocu_IrqHandler(0, 19);
1727 #endif
1728
1729 #if (defined PWM_EMIOS_0_CH_19_ISR_USED)
1730 Emios_Pwm_IrqHandler(0, 19);
1731 #endif
1732 #endif
1733 }
1734 #endif
1735
1736 #if (\
1737 (defined GPT_EMIOS_0_CH_20_ISR_USED) ||\
1738 (defined ICU_EMIOS_0_CH_20_ISR_USED) ||\
1739 (defined OCU_EMIOS_0_CH_20_ISR_USED) ||\
1740 (defined PWM_EMIOS_0_CH_20_ISR_USED)\
1741 )
1742 /**
1743 * @brief Interrupt handler for EMIOS channel 20 for Emios instance 0
1744 * @details Process the interrupt of EMIOS channel 20
1745 *
1746 * @note This will be defined only if EMIOS channel 20 is configured in GPT, ICU,
1747 * OCU or PWM mode.
1748 */
ISR(EMIOS0_CH20_IRQ)1749 ISR(EMIOS0_CH20_IRQ)
1750 {
1751 #if (defined EMIOS_0_CH_20_ISR_USED)
1752 #if (defined GPT_EMIOS_0_CH_20_ISR_USED)
1753 Emios_Gpt_IrqHandler(0, 20);
1754 #endif
1755
1756 #if (defined ICU_EMIOS_0_CH_20_ISR_USED)
1757 Emios_Icu_IrqHandler(0, 20);
1758 #endif
1759
1760 #if (defined OCU_EMIOS_0_CH_20_ISR_USED)
1761 Emios_Ocu_IrqHandler(0, 20);
1762 #endif
1763
1764 #if (defined PWM_EMIOS_0_CH_20_ISR_USED)
1765 Emios_Pwm_IrqHandler(0, 20);
1766 #endif
1767 #endif
1768 }
1769 #endif
1770
1771 #if (\
1772 (defined GPT_EMIOS_0_CH_21_ISR_USED) ||\
1773 (defined ICU_EMIOS_0_CH_21_ISR_USED) ||\
1774 (defined OCU_EMIOS_0_CH_21_ISR_USED) ||\
1775 (defined PWM_EMIOS_0_CH_21_ISR_USED)\
1776 )
1777 /**
1778 * @brief Interrupt handler for EMIOS channel 21 for Emios instance 0
1779 * @details Process the interrupt of EMIOS channel 21
1780 *
1781 * @note This will be defined only if EMIOS channel 21 is configured in GPT, ICU,
1782 * OCU or PWM mode.
1783 */
ISR(EMIOS0_CH21_IRQ)1784 ISR(EMIOS0_CH21_IRQ)
1785 {
1786 #if (defined EMIOS_0_CH_21_ISR_USED)
1787 #if (defined GPT_EMIOS_0_CH_21_ISR_USED)
1788 Emios_Gpt_IrqHandler(0, 21);
1789 #endif
1790
1791 #if (defined ICU_EMIOS_0_CH_21_ISR_USED)
1792 Emios_Icu_IrqHandler(0, 21);
1793 #endif
1794
1795 #if (defined OCU_EMIOS_0_CH_21_ISR_USED)
1796 Emios_Ocu_IrqHandler(0, 21);
1797 #endif
1798
1799 #if (defined PWM_EMIOS_0_CH_21_ISR_USED)
1800 Emios_Pwm_IrqHandler(0, 21);
1801 #endif
1802 #endif
1803 }
1804 #endif
1805
1806 #if (\
1807 (defined GPT_EMIOS_0_CH_22_ISR_USED) ||\
1808 (defined ICU_EMIOS_0_CH_22_ISR_USED) ||\
1809 (defined OCU_EMIOS_0_CH_22_ISR_USED) ||\
1810 (defined PWM_EMIOS_0_CH_22_ISR_USED)\
1811 )
1812 /**
1813 * @brief Interrupt handler for EMIOS channel 22 for Emios instance 0
1814 * @details Process the interrupt of EMIOS channel 22
1815 *
1816 * @note This will be defined only if EMIOS channel 22 is configured in GPT, ICU,
1817 * OCU or PWM mode.
1818 */
ISR(EMIOS0_CH22_IRQ)1819 ISR(EMIOS0_CH22_IRQ)
1820 {
1821 #if (defined EMIOS_0_CH_22_ISR_USED)
1822 #if (defined GPT_EMIOS_0_CH_22_ISR_USED)
1823 Emios_Gpt_IrqHandler(0, 22);
1824 #endif
1825
1826 #if (defined ICU_EMIOS_0_CH_22_ISR_USED)
1827 Emios_Icu_IrqHandler(0, 22);
1828 #endif
1829
1830 #if (defined OCU_EMIOS_0_CH_22_ISR_USED)
1831 Emios_Ocu_IrqHandler(0, 22);
1832 #endif
1833
1834 #if (defined PWM_EMIOS_0_CH_22_ISR_USED)
1835 Emios_Pwm_IrqHandler(0, 22);
1836 #endif
1837 #endif
1838 }
1839 #endif
1840
1841 #if (\
1842 (defined GPT_EMIOS_0_CH_23_ISR_USED) ||\
1843 (defined ICU_EMIOS_0_CH_23_ISR_USED) ||\
1844 (defined OCU_EMIOS_0_CH_23_ISR_USED) ||\
1845 (defined PWM_EMIOS_0_CH_23_ISR_USED)\
1846 )
1847 /**
1848 * @brief Interrupt handler for EMIOS channel 23 for Emios instance 0
1849 * @details Process the interrupt of EMIOS channel 23
1850 *
1851 * @note This will be defined only if EMIOS channel 23 is configured in GPT, ICU,
1852 * OCU or PWM mode.
1853 */
ISR(EMIOS0_CH23_IRQ)1854 ISR(EMIOS0_CH23_IRQ)
1855 {
1856 #if (defined EMIOS_0_CH_23_ISR_USED)
1857 #if (defined GPT_EMIOS_0_CH_23_ISR_USED)
1858 Emios_Gpt_IrqHandler(0, 23);
1859 #endif
1860
1861 #if (defined ICU_EMIOS_0_CH_23_ISR_USED)
1862 Emios_Icu_IrqHandler(0, 23);
1863 #endif
1864
1865 #if (defined OCU_EMIOS_0_CH_23_ISR_USED)
1866 Emios_Ocu_IrqHandler(0, 23);
1867 #endif
1868
1869 #if (defined PWM_EMIOS_0_CH_23_ISR_USED)
1870 Emios_Pwm_IrqHandler(0, 23);
1871 #endif
1872 #endif
1873 }
1874 #endif
1875
1876 #if (\
1877 (defined GPT_EMIOS_0_CH_24_ISR_USED) ||\
1878 (defined ICU_EMIOS_0_CH_24_ISR_USED) ||\
1879 (defined OCU_EMIOS_0_CH_24_ISR_USED) ||\
1880 (defined PWM_EMIOS_0_CH_24_ISR_USED)\
1881 )
1882 /**
1883 * @brief Interrupt handler for EMIOS channel 24 for Emios instance 0
1884 * @details Process the interrupt of EMIOS channel 24
1885 *
1886 * @note This will be defined only if EMIOS channel 24 is configured in GPT, ICU,
1887 * OCU or PWM mode.
1888 */
ISR(EMIOS0_CH24_IRQ)1889 ISR(EMIOS0_CH24_IRQ)
1890 {
1891 #if (defined EMIOS_0_CH_24_ISR_USED)
1892 #if (defined GPT_EMIOS_0_CH_24_ISR_USED)
1893 Emios_Gpt_IrqHandler(0, 24);
1894 #endif
1895
1896 #if (defined ICU_EMIOS_0_CH_24_ISR_USED)
1897 Emios_Icu_IrqHandler(0, 24);
1898 #endif
1899
1900 #if (defined OCU_EMIOS_0_CH_24_ISR_USED)
1901 Emios_Ocu_IrqHandler(0, 24);
1902 #endif
1903
1904 #if (defined PWM_EMIOS_0_CH_24_ISR_USED)
1905 Emios_Pwm_IrqHandler(0, 24);
1906 #endif
1907 #endif
1908 }
1909 #endif
1910
1911 #if (\
1912 (defined GPT_EMIOS_0_CH_25_ISR_USED) ||\
1913 (defined ICU_EMIOS_0_CH_25_ISR_USED) ||\
1914 (defined OCU_EMIOS_0_CH_25_ISR_USED) ||\
1915 (defined PWM_EMIOS_0_CH_25_ISR_USED)\
1916 )
1917 /**
1918 * @brief Interrupt handler for EMIOS channel 25 for Emios instance 0
1919 * @details Process the interrupt of EMIOS channel 25
1920 *
1921 * @note This will be defined only if EMIOS channel 25 is configured in GPT, ICU,
1922 * OCU or PWM mode.
1923 */
ISR(EMIOS0_CH25_IRQ)1924 ISR(EMIOS0_CH25_IRQ)
1925 {
1926 #if (defined EMIOS_0_CH_25_ISR_USED)
1927 #if (defined GPT_EMIOS_0_CH_25_ISR_USED)
1928 Emios_Gpt_IrqHandler(0, 25);
1929 #endif
1930
1931 #if (defined ICU_EMIOS_0_CH_25_ISR_USED)
1932 Emios_Icu_IrqHandler(0, 25);
1933 #endif
1934
1935 #if (defined OCU_EMIOS_0_CH_25_ISR_USED)
1936 Emios_Ocu_IrqHandler(0, 25);
1937 #endif
1938
1939 #if (defined PWM_EMIOS_0_CH_25_ISR_USED)
1940 Emios_Pwm_IrqHandler(0, 25);
1941 #endif
1942 #endif
1943 }
1944 #endif
1945
1946 #if (\
1947 (defined GPT_EMIOS_0_CH_26_ISR_USED) ||\
1948 (defined ICU_EMIOS_0_CH_26_ISR_USED) ||\
1949 (defined OCU_EMIOS_0_CH_26_ISR_USED) ||\
1950 (defined PWM_EMIOS_0_CH_26_ISR_USED)\
1951 )
1952 /**
1953 * @brief Interrupt handler for EMIOS channel 26 for Emios instance 0
1954 * @details Process the interrupt of EMIOS channel 26
1955 *
1956 * @note This will be defined only if EMIOS channel 26 is configured in GPT, ICU,
1957 * OCU or PWM mode.
1958 */
ISR(EMIOS0_CH26_IRQ)1959 ISR(EMIOS0_CH26_IRQ)
1960 {
1961 #if (defined EMIOS_0_CH_26_ISR_USED)
1962 #if (defined GPT_EMIOS_0_CH_26_ISR_USED)
1963 Emios_Gpt_IrqHandler(0, 26);
1964 #endif
1965
1966 #if (defined ICU_EMIOS_0_CH_26_ISR_USED)
1967 Emios_Icu_IrqHandler(0, 26);
1968 #endif
1969
1970 #if (defined OCU_EMIOS_0_CH_26_ISR_USED)
1971 Emios_Ocu_IrqHandler(0, 26);
1972 #endif
1973
1974 #if (defined PWM_EMIOS_0_CH_26_ISR_USED)
1975 Emios_Pwm_IrqHandler(0, 26);
1976 #endif
1977 #endif
1978 }
1979 #endif
1980
1981 #if (\
1982 (defined GPT_EMIOS_0_CH_27_ISR_USED) ||\
1983 (defined ICU_EMIOS_0_CH_27_ISR_USED) ||\
1984 (defined OCU_EMIOS_0_CH_27_ISR_USED) ||\
1985 (defined PWM_EMIOS_0_CH_27_ISR_USED)\
1986 )
1987 /**
1988 * @brief Interrupt handler for EMIOS channel 27 for Emios instance 0
1989 * @details Process the interrupt of EMIOS channel 27
1990 *
1991 * @note This will be defined only if EMIOS channel 27 is configured in GPT, ICU,
1992 * OCU or PWM mode.
1993 */
ISR(EMIOS0_CH27_IRQ)1994 ISR(EMIOS0_CH27_IRQ)
1995 {
1996 #if (defined EMIOS_0_CH_27_ISR_USED)
1997 #if (defined GPT_EMIOS_0_CH_27_ISR_USED)
1998 Emios_Gpt_IrqHandler(0, 27);
1999 #endif
2000
2001 #if (defined ICU_EMIOS_0_CH_27_ISR_USED)
2002 Emios_Icu_IrqHandler(0, 27);
2003 #endif
2004
2005 #if (defined OCU_EMIOS_0_CH_27_ISR_USED)
2006 Emios_Ocu_IrqHandler(0, 27);
2007 #endif
2008
2009 #if (defined PWM_EMIOS_0_CH_27_ISR_USED)
2010 Emios_Pwm_IrqHandler(0, 27);
2011 #endif
2012 #endif
2013 }
2014 #endif
2015
2016 #if (\
2017 (defined GPT_EMIOS_0_CH_28_ISR_USED) ||\
2018 (defined ICU_EMIOS_0_CH_28_ISR_USED) ||\
2019 (defined OCU_EMIOS_0_CH_28_ISR_USED) ||\
2020 (defined PWM_EMIOS_0_CH_28_ISR_USED)\
2021 )
2022 /**
2023 * @brief Interrupt handler for EMIOS channel 28 for Emios instance 0
2024 * @details Process the interrupt of EMIOS channel 28
2025 *
2026 * @note This will be defined only if EMIOS channel 28 is configured in GPT, ICU,
2027 * OCU or PWM mode.
2028 */
ISR(EMIOS0_CH28_IRQ)2029 ISR(EMIOS0_CH28_IRQ)
2030 {
2031 #if (defined EMIOS_0_CH_28_ISR_USED)
2032 #if (defined GPT_EMIOS_0_CH_28_ISR_USED)
2033 Emios_Gpt_IrqHandler(0, 28);
2034 #endif
2035
2036 #if (defined ICU_EMIOS_0_CH_28_ISR_USED)
2037 Emios_Icu_IrqHandler(0, 28);
2038 #endif
2039
2040 #if (defined OCU_EMIOS_0_CH_28_ISR_USED)
2041 Emios_Ocu_IrqHandler(0, 28);
2042 #endif
2043
2044 #if (defined PWM_EMIOS_0_CH_28_ISR_USED)
2045 Emios_Pwm_IrqHandler(0, 28);
2046 #endif
2047 #endif
2048 }
2049 #endif
2050
2051 #if (\
2052 (defined GPT_EMIOS_0_CH_29_ISR_USED) ||\
2053 (defined ICU_EMIOS_0_CH_29_ISR_USED) ||\
2054 (defined OCU_EMIOS_0_CH_29_ISR_USED) ||\
2055 (defined PWM_EMIOS_0_CH_29_ISR_USED)\
2056 )
2057 /**
2058 * @brief Interrupt handler for EMIOS channel 29 for Emios instance 0
2059 * @details Process the interrupt of EMIOS channel 29
2060 *
2061 * @note This will be defined only if EMIOS channel 29 is configured in GPT, ICU,
2062 * OCU or PWM mode.
2063 */
ISR(EMIOS0_CH29_IRQ)2064 ISR(EMIOS0_CH29_IRQ)
2065 {
2066 #if (defined EMIOS_0_CH_29_ISR_USED)
2067 #if (defined GPT_EMIOS_0_CH_29_ISR_USED)
2068 Emios_Gpt_IrqHandler(0, 29);
2069 #endif
2070
2071 #if (defined ICU_EMIOS_0_CH_29_ISR_USED)
2072 Emios_Icu_IrqHandler(0, 29);
2073 #endif
2074
2075 #if (defined OCU_EMIOS_0_CH_29_ISR_USED)
2076 Emios_Ocu_IrqHandler(0, 29);
2077 #endif
2078
2079 #if (defined PWM_EMIOS_0_CH_29_ISR_USED)
2080 Emios_Pwm_IrqHandler(0, 29);
2081 #endif
2082 #endif
2083 }
2084 #endif
2085
2086 #if (\
2087 (defined GPT_EMIOS_0_CH_30_ISR_USED) ||\
2088 (defined ICU_EMIOS_0_CH_30_ISR_USED) ||\
2089 (defined OCU_EMIOS_0_CH_30_ISR_USED) ||\
2090 (defined PWM_EMIOS_0_CH_30_ISR_USED)\
2091 )
2092 /**
2093 * @brief Interrupt handler for EMIOS channel 30 for Emios instance 0
2094 * @details Process the interrupt of EMIOS channel 30
2095 *
2096 * @note This will be defined only if EMIOS channel 30 is configured in GPT, ICU,
2097 * OCU or PWM mode.
2098 */
ISR(EMIOS0_CH30_IRQ)2099 ISR(EMIOS0_CH30_IRQ)
2100 {
2101 #if (defined EMIOS_0_CH_30_ISR_USED)
2102 #if (defined GPT_EMIOS_0_CH_30_ISR_USED)
2103 Emios_Gpt_IrqHandler(0, 30);
2104 #endif
2105
2106 #if (defined ICU_EMIOS_0_CH_30_ISR_USED)
2107 Emios_Icu_IrqHandler(0, 30);
2108 #endif
2109
2110 #if (defined OCU_EMIOS_0_CH_30_ISR_USED)
2111 Emios_Ocu_IrqHandler(0, 30);
2112 #endif
2113
2114 #if (defined PWM_EMIOS_0_CH_30_ISR_USED)
2115 Emios_Pwm_IrqHandler(0, 30);
2116 #endif
2117 #endif
2118 }
2119 #endif
2120
2121 #if (\
2122 (defined GPT_EMIOS_0_CH_31_ISR_USED) ||\
2123 (defined ICU_EMIOS_0_CH_31_ISR_USED) ||\
2124 (defined OCU_EMIOS_0_CH_31_ISR_USED) ||\
2125 (defined PWM_EMIOS_0_CH_31_ISR_USED)\
2126 )
2127 /**
2128 * @brief Interrupt handler for EMIOS channel 31 for Emios instance 0
2129 * @details Process the interrupt of EMIOS channel 31
2130 *
2131 * @note This will be defined only if EMIOS channel 31 is configured in GPT, ICU,
2132 * OCU or PWM mode.
2133 */
ISR(EMIOS0_CH31_IRQ)2134 ISR(EMIOS0_CH31_IRQ)
2135 {
2136 #if (defined EMIOS_0_CH_31_ISR_USED)
2137 #if (defined GPT_EMIOS_0_CH_31_ISR_USED)
2138 Emios_Gpt_IrqHandler(0, 31);
2139 #endif
2140
2141 #if (defined ICU_EMIOS_0_CH_31_ISR_USED)
2142 Emios_Icu_IrqHandler(0, 31);
2143 #endif
2144
2145 #if (defined OCU_EMIOS_0_CH_31_ISR_USED)
2146 Emios_Ocu_IrqHandler(0, 31);
2147 #endif
2148
2149 #if (defined PWM_EMIOS_0_CH_31_ISR_USED)
2150 Emios_Pwm_IrqHandler(0, 31);
2151 #endif
2152 #endif
2153 }
2154 #endif
2155
2156 #if (\
2157 (defined GPT_EMIOS_1_CH_0_ISR_USED) ||\
2158 (defined ICU_EMIOS_1_CH_0_ISR_USED) ||\
2159 (defined OCU_EMIOS_1_CH_0_ISR_USED) ||\
2160 (defined PWM_EMIOS_1_CH_0_ISR_USED)\
2161 )
2162 /**
2163 * @brief Interrupt handler for EMIOS channel 0 for Emios instance 1
2164 * @details Process the interrupt of EMIOS channel 0
2165 *
2166 * @note This will be defined only if EMIOS channel 0 is configured in GPT, ICU,
2167 * OCU or PWM mode.
2168 */
ISR(EMIOS1_CH0_IRQ)2169 ISR(EMIOS1_CH0_IRQ)
2170 {
2171 #if (defined EMIOS_1_CH_0_ISR_USED)
2172 #if (defined GPT_EMIOS_1_CH_0_ISR_USED)
2173 Emios_Gpt_IrqHandler(1, 0);
2174 #endif
2175
2176 #if (defined ICU_EMIOS_1_CH_0_ISR_USED)
2177 Emios_Icu_IrqHandler(1, 0);
2178 #endif
2179
2180 #if (defined OCU_EMIOS_1_CH_0_ISR_USED)
2181 Emios_Ocu_IrqHandler(1, 0);
2182 #endif
2183
2184 #if (defined PWM_EMIOS_1_CH_0_ISR_USED)
2185 Emios_Pwm_IrqHandler(1, 0);
2186 #endif
2187 #endif
2188 }
2189 #endif
2190
2191 #if (\
2192 (defined GPT_EMIOS_1_CH_1_ISR_USED) ||\
2193 (defined ICU_EMIOS_1_CH_1_ISR_USED) ||\
2194 (defined OCU_EMIOS_1_CH_1_ISR_USED) ||\
2195 (defined PWM_EMIOS_1_CH_1_ISR_USED)\
2196 )
2197 /**
2198 * @brief Interrupt handler for EMIOS channel 1 for Emios instance 1
2199 * @details Process the interrupt of EMIOS channel 1
2200 *
2201 * @note This will be defined only if EMIOS channel 1 is configured in GPT, ICU,
2202 * OCU or PWM mode.
2203 */
ISR(EMIOS1_CH1_IRQ)2204 ISR(EMIOS1_CH1_IRQ)
2205 {
2206 #if (defined EMIOS_1_CH_1_ISR_USED)
2207 #if (defined GPT_EMIOS_1_CH_1_ISR_USED)
2208 Emios_Gpt_IrqHandler(1, 1);
2209 #endif
2210
2211 #if (defined ICU_EMIOS_1_CH_1_ISR_USED)
2212 Emios_Icu_IrqHandler(1, 1);
2213 #endif
2214
2215 #if (defined OCU_EMIOS_1_CH_1_ISR_USED)
2216 Emios_Ocu_IrqHandler(1, 1);
2217 #endif
2218
2219 #if (defined PWM_EMIOS_1_CH_1_ISR_USED)
2220 Emios_Pwm_IrqHandler(1, 1);
2221 #endif
2222 #endif
2223 }
2224 #endif
2225
2226 #if (\
2227 (defined GPT_EMIOS_1_CH_2_ISR_USED) ||\
2228 (defined ICU_EMIOS_1_CH_2_ISR_USED) ||\
2229 (defined OCU_EMIOS_1_CH_2_ISR_USED) ||\
2230 (defined PWM_EMIOS_1_CH_2_ISR_USED)\
2231 )
2232 /**
2233 * @brief Interrupt handler for EMIOS channel 2 for Emios instance 1
2234 * @details Process the interrupt of EMIOS channel 2
2235 *
2236 * @note This will be defined only if EMIOS channel 2 is configured in GPT, ICU,
2237 * OCU or PWM mode.
2238 */
ISR(EMIOS1_CH2_IRQ)2239 ISR(EMIOS1_CH2_IRQ)
2240 {
2241 #if (defined EMIOS_1_CH_2_ISR_USED)
2242 #if (defined GPT_EMIOS_1_CH_2_ISR_USED)
2243 Emios_Gpt_IrqHandler(1, 2);
2244 #endif
2245
2246 #if (defined ICU_EMIOS_1_CH_2_ISR_USED)
2247 Emios_Icu_IrqHandler(1, 2);
2248 #endif
2249
2250 #if (defined OCU_EMIOS_1_CH_2_ISR_USED)
2251 Emios_Ocu_IrqHandler(1, 2);
2252 #endif
2253
2254 #if (defined PWM_EMIOS_1_CH_2_ISR_USED)
2255 Emios_Pwm_IrqHandler(1, 2);
2256 #endif
2257 #endif
2258 }
2259 #endif
2260
2261 #if (\
2262 (defined GPT_EMIOS_1_CH_3_ISR_USED) ||\
2263 (defined ICU_EMIOS_1_CH_3_ISR_USED) ||\
2264 (defined OCU_EMIOS_1_CH_3_ISR_USED) ||\
2265 (defined PWM_EMIOS_1_CH_3_ISR_USED)\
2266 )
2267 /**
2268 * @brief Interrupt handler for EMIOS channel 3 for Emios instance 1
2269 * @details Process the interrupt of EMIOS channel 3
2270 *
2271 * @note This will be defined only if EMIOS channel 3 is configured in GPT, ICU,
2272 * OCU or PWM mode.
2273 */
ISR(EMIOS1_CH3_IRQ)2274 ISR(EMIOS1_CH3_IRQ)
2275 {
2276 #if (defined EMIOS_1_CH_3_ISR_USED)
2277 #if (defined GPT_EMIOS_1_CH_3_ISR_USED)
2278 Emios_Gpt_IrqHandler(1, 3);
2279 #endif
2280
2281 #if (defined ICU_EMIOS_1_CH_3_ISR_USED)
2282 Emios_Icu_IrqHandler(1, 3);
2283 #endif
2284
2285 #if (defined OCU_EMIOS_1_CH_3_ISR_USED)
2286 Emios_Ocu_IrqHandler(1, 3);
2287 #endif
2288
2289 #if (defined PWM_EMIOS_1_CH_3_ISR_USED)
2290 Emios_Pwm_IrqHandler(1, 3);
2291 #endif
2292 #endif
2293 }
2294 #endif
2295
2296 #if (\
2297 (defined GPT_EMIOS_1_CH_4_ISR_USED) ||\
2298 (defined ICU_EMIOS_1_CH_4_ISR_USED) ||\
2299 (defined OCU_EMIOS_1_CH_4_ISR_USED) ||\
2300 (defined PWM_EMIOS_1_CH_4_ISR_USED)\
2301 )
2302 /**
2303 * @brief Interrupt handler for EMIOS channel 4 for Emios instance 1
2304 * @details Process the interrupt of EMIOS channel 4
2305 *
2306 * @note This will be defined only if EMIOS channel 4 is configured in GPT, ICU,
2307 * OCU or PWM mode.
2308 */
ISR(EMIOS1_CH4_IRQ)2309 ISR(EMIOS1_CH4_IRQ)
2310 {
2311 #if (defined EMIOS_1_CH_4_ISR_USED)
2312 #if (defined GPT_EMIOS_1_CH_4_ISR_USED)
2313 Emios_Gpt_IrqHandler(1, 4);
2314 #endif
2315
2316 #if (defined ICU_EMIOS_1_CH_4_ISR_USED)
2317 Emios_Icu_IrqHandler(1, 4);
2318 #endif
2319
2320 #if (defined OCU_EMIOS_1_CH_4_ISR_USED)
2321 Emios_Ocu_IrqHandler(1, 4);
2322 #endif
2323
2324 #if (defined PWM_EMIOS_1_CH_4_ISR_USED)
2325 Emios_Pwm_IrqHandler(1, 4);
2326 #endif
2327 #endif
2328 }
2329 #endif
2330
2331 #if (\
2332 (defined GPT_EMIOS_1_CH_5_ISR_USED) ||\
2333 (defined ICU_EMIOS_1_CH_5_ISR_USED) ||\
2334 (defined OCU_EMIOS_1_CH_5_ISR_USED) ||\
2335 (defined PWM_EMIOS_1_CH_5_ISR_USED)\
2336 )
2337 /**
2338 * @brief Interrupt handler for EMIOS channel 5 for Emios instance 1
2339 * @details Process the interrupt of EMIOS channel 5
2340 *
2341 * @note This will be defined only if EMIOS channel 5 is configured in GPT, ICU,
2342 * OCU or PWM mode.
2343 */
ISR(EMIOS1_CH5_IRQ)2344 ISR(EMIOS1_CH5_IRQ)
2345 {
2346 #if (defined EMIOS_1_CH_5_ISR_USED)
2347 #if (defined GPT_EMIOS_1_CH_5_ISR_USED)
2348 Emios_Gpt_IrqHandler(1, 5);
2349 #endif
2350
2351 #if (defined ICU_EMIOS_1_CH_5_ISR_USED)
2352 Emios_Icu_IrqHandler(1, 5);
2353 #endif
2354
2355 #if (defined OCU_EMIOS_1_CH_5_ISR_USED)
2356 Emios_Ocu_IrqHandler(1, 5);
2357 #endif
2358
2359 #if (defined PWM_EMIOS_1_CH_5_ISR_USED)
2360 Emios_Pwm_IrqHandler(1, 5);
2361 #endif
2362 #endif
2363 }
2364 #endif
2365
2366 #if (\
2367 (defined GPT_EMIOS_1_CH_6_ISR_USED) ||\
2368 (defined ICU_EMIOS_1_CH_6_ISR_USED) ||\
2369 (defined OCU_EMIOS_1_CH_6_ISR_USED) ||\
2370 (defined PWM_EMIOS_1_CH_6_ISR_USED)\
2371 )
2372 /**
2373 * @brief Interrupt handler for EMIOS channel 6 for Emios instance 1
2374 * @details Process the interrupt of EMIOS channel 6
2375 *
2376 * @note This will be defined only if EMIOS channel 6 is configured in GPT, ICU,
2377 * OCU or PWM mode.
2378 */
ISR(EMIOS1_CH6_IRQ)2379 ISR(EMIOS1_CH6_IRQ)
2380 {
2381 #if (defined EMIOS_1_CH_6_ISR_USED)
2382 #if (defined GPT_EMIOS_1_CH_6_ISR_USED)
2383 Emios_Gpt_IrqHandler(1, 6);
2384 #endif
2385
2386 #if (defined ICU_EMIOS_1_CH_6_ISR_USED)
2387 Emios_Icu_IrqHandler(1, 6);
2388 #endif
2389
2390 #if (defined OCU_EMIOS_1_CH_6_ISR_USED)
2391 Emios_Ocu_IrqHandler(1, 6);
2392 #endif
2393
2394 #if (defined PWM_EMIOS_1_CH_6_ISR_USED)
2395 Emios_Pwm_IrqHandler(1, 6);
2396 #endif
2397 #endif
2398 }
2399 #endif
2400
2401 #if (\
2402 (defined GPT_EMIOS_1_CH_7_ISR_USED) ||\
2403 (defined ICU_EMIOS_1_CH_7_ISR_USED) ||\
2404 (defined OCU_EMIOS_1_CH_7_ISR_USED) ||\
2405 (defined PWM_EMIOS_1_CH_7_ISR_USED)\
2406 )
2407 /**
2408 * @brief Interrupt handler for EMIOS channel 7 for Emios instance 1
2409 * @details Process the interrupt of EMIOS channel 7
2410 *
2411 * @note This will be defined only if EMIOS channel 7 is configured in GPT, ICU,
2412 * OCU or PWM mode.
2413 */
ISR(EMIOS1_CH7_IRQ)2414 ISR(EMIOS1_CH7_IRQ)
2415 {
2416 #if (defined EMIOS_1_CH_7_ISR_USED)
2417 #if (defined GPT_EMIOS_1_CH_7_ISR_USED)
2418 Emios_Gpt_IrqHandler(1, 7);
2419 #endif
2420
2421 #if (defined ICU_EMIOS_1_CH_7_ISR_USED)
2422 Emios_Icu_IrqHandler(1, 7);
2423 #endif
2424
2425 #if (defined OCU_EMIOS_1_CH_7_ISR_USED)
2426 Emios_Ocu_IrqHandler(1, 7);
2427 #endif
2428
2429 #if (defined PWM_EMIOS_1_CH_7_ISR_USED)
2430 Emios_Pwm_IrqHandler(1, 7);
2431 #endif
2432 #endif
2433 }
2434 #endif
2435
2436 #if (\
2437 (defined GPT_EMIOS_1_CH_8_ISR_USED) ||\
2438 (defined ICU_EMIOS_1_CH_8_ISR_USED) ||\
2439 (defined OCU_EMIOS_1_CH_8_ISR_USED) ||\
2440 (defined PWM_EMIOS_1_CH_8_ISR_USED)\
2441 )
2442 /**
2443 * @brief Interrupt handler for EMIOS channel 8 for Emios instance 1
2444 * @details Process the interrupt of EMIOS channel 8
2445 *
2446 * @note This will be defined only if EMIOS channel 8 is configured in GPT, ICU,
2447 * OCU or PWM mode.
2448 */
ISR(EMIOS1_CH8_IRQ)2449 ISR(EMIOS1_CH8_IRQ)
2450 {
2451 #if (defined EMIOS_1_CH_8_ISR_USED)
2452 #if (defined GPT_EMIOS_1_CH_8_ISR_USED)
2453 Emios_Gpt_Wsc_IrqHandler(1, 8);
2454 #endif
2455
2456 #if (defined ICU_EMIOS_1_CH_8_ISR_USED)
2457 Emios_Icu_Wsc_IrqHandler(1, 8);
2458 #endif
2459
2460 #if (defined OCU_EMIOS_1_CH_8_ISR_USED)
2461 Emios_Ocu_Wsc_IrqHandler(1, 8);
2462 #endif
2463
2464 #if (defined PWM_EMIOS_1_CH_8_ISR_USED)
2465 Emios_Pwm_Wsc_IrqHandler(1, 8);
2466 #endif
2467 #endif
2468 }
2469 #endif
2470
2471 #if (\
2472 (defined GPT_EMIOS_1_CH_9_ISR_USED) ||\
2473 (defined ICU_EMIOS_1_CH_9_ISR_USED) ||\
2474 (defined OCU_EMIOS_1_CH_9_ISR_USED) ||\
2475 (defined PWM_EMIOS_1_CH_9_ISR_USED)\
2476 )
2477 /**
2478 * @brief Interrupt handler for EMIOS channel 9 for Emios instance 1
2479 * @details Process the interrupt of EMIOS channel 9
2480 *
2481 * @note This will be defined only if EMIOS channel 9 is configured in GPT, ICU,
2482 * OCU or PWM mode.
2483 */
ISR(EMIOS1_CH9_IRQ)2484 ISR(EMIOS1_CH9_IRQ)
2485 {
2486 #if (defined EMIOS_1_CH_9_ISR_USED)
2487 #if (defined GPT_EMIOS_1_CH_9_ISR_USED)
2488 Emios_Gpt_IrqHandler(1, 9);
2489 #endif
2490
2491 #if (defined ICU_EMIOS_1_CH_9_ISR_USED)
2492 Emios_Icu_IrqHandler(1, 9);
2493 #endif
2494
2495 #if (defined OCU_EMIOS_1_CH_9_ISR_USED)
2496 Emios_Ocu_IrqHandler(1, 9);
2497 #endif
2498
2499 #if (defined PWM_EMIOS_1_CH_9_ISR_USED)
2500 Emios_Pwm_IrqHandler(1, 9);
2501 #endif
2502 #endif
2503 }
2504 #endif
2505
2506 #if (\
2507 (defined GPT_EMIOS_1_CH_10_ISR_USED) ||\
2508 (defined ICU_EMIOS_1_CH_10_ISR_USED) ||\
2509 (defined OCU_EMIOS_1_CH_10_ISR_USED) ||\
2510 (defined PWM_EMIOS_1_CH_10_ISR_USED)\
2511 )
2512 /**
2513 * @brief Interrupt handler for EMIOS channel 10 for Emios instance 1
2514 * @details Process the interrupt of EMIOS channel 10
2515 *
2516 * @note This will be defined only if EMIOS channel 10 is configured in GPT, ICU,
2517 * OCU or PWM mode.
2518 */
ISR(EMIOS1_CH10_IRQ)2519 ISR(EMIOS1_CH10_IRQ)
2520 {
2521 #if (defined EMIOS_1_CH_10_ISR_USED)
2522 #if (defined GPT_EMIOS_1_CH_10_ISR_USED)
2523 Emios_Gpt_Wsc_IrqHandler(1, 10);
2524 #endif
2525
2526 #if (defined ICU_EMIOS_1_CH_10_ISR_USED)
2527 Emios_Icu_Wsc_IrqHandler(1, 10);
2528 #endif
2529
2530 #if (defined OCU_EMIOS_1_CH_10_ISR_USED)
2531 Emios_Ocu_Wsc_IrqHandler(1, 10);
2532 #endif
2533
2534 #if (defined PWM_EMIOS_1_CH_10_ISR_USED)
2535 Emios_Pwm_Wsc_IrqHandler(1, 10);
2536 #endif
2537 #endif
2538 }
2539 #endif
2540
2541 #if (\
2542 (defined GPT_EMIOS_1_CH_11_ISR_USED) ||\
2543 (defined ICU_EMIOS_1_CH_11_ISR_USED) ||\
2544 (defined OCU_EMIOS_1_CH_11_ISR_USED) ||\
2545 (defined PWM_EMIOS_1_CH_11_ISR_USED)\
2546 )
2547 /**
2548 * @brief Interrupt handler for EMIOS channel 11 for Emios instance 1
2549 * @details Process the interrupt of EMIOS channel 11
2550 *
2551 * @note This will be defined only if EMIOS channel 11 is configured in GPT, ICU,
2552 * OCU or PWM mode.
2553 */
ISR(EMIOS1_CH11_IRQ)2554 ISR(EMIOS1_CH11_IRQ)
2555 {
2556 #if (defined EMIOS_1_CH_11_ISR_USED)
2557 #if (defined GPT_EMIOS_1_CH_11_ISR_USED)
2558 Emios_Gpt_IrqHandler(1, 11);
2559 #endif
2560
2561 #if (defined ICU_EMIOS_1_CH_11_ISR_USED)
2562 Emios_Icu_IrqHandler(1, 11);
2563 #endif
2564
2565 #if (defined OCU_EMIOS_1_CH_11_ISR_USED)
2566 Emios_Ocu_IrqHandler(1, 11);
2567 #endif
2568
2569 #if (defined PWM_EMIOS_1_CH_11_ISR_USED)
2570 Emios_Pwm_IrqHandler(1, 11);
2571 #endif
2572 #endif
2573 }
2574 #endif
2575
2576 #if (\
2577 (defined GPT_EMIOS_1_CH_12_ISR_USED) ||\
2578 (defined ICU_EMIOS_1_CH_12_ISR_USED) ||\
2579 (defined OCU_EMIOS_1_CH_12_ISR_USED) ||\
2580 (defined PWM_EMIOS_1_CH_12_ISR_USED)\
2581 )
2582 /**
2583 * @brief Interrupt handler for EMIOS channel 12 for Emios instance 1
2584 * @details Process the interrupt of EMIOS channel 12
2585 *
2586 * @note This will be defined only if EMIOS channel 12 is configured in GPT, ICU,
2587 * OCU or PWM mode.
2588 */
ISR(EMIOS1_CH12_IRQ)2589 ISR(EMIOS1_CH12_IRQ)
2590 {
2591 #if (defined EMIOS_1_CH_12_ISR_USED)
2592 #if (defined GPT_EMIOS_1_CH_12_ISR_USED)
2593 Emios_Gpt_Wsc_IrqHandler(1, 12);
2594 #endif
2595
2596 #if (defined ICU_EMIOS_1_CH_12_ISR_USED)
2597 Emios_Icu_Wsc_IrqHandler(1, 12);
2598 #endif
2599
2600 #if (defined OCU_EMIOS_1_CH_12_ISR_USED)
2601 Emios_Ocu_Wsc_IrqHandler(1, 12);
2602 #endif
2603
2604 #if (defined PWM_EMIOS_1_CH_12_ISR_USED)
2605 Emios_Pwm_Wsc_IrqHandler(1, 12);
2606 #endif
2607 #endif
2608 }
2609 #endif
2610
2611 #if (\
2612 (defined GPT_EMIOS_1_CH_13_ISR_USED) ||\
2613 (defined ICU_EMIOS_1_CH_13_ISR_USED) ||\
2614 (defined OCU_EMIOS_1_CH_13_ISR_USED) ||\
2615 (defined PWM_EMIOS_1_CH_13_ISR_USED)\
2616 )
2617 /**
2618 * @brief Interrupt handler for EMIOS channel 13 for Emios instance 1
2619 * @details Process the interrupt of EMIOS channel 13
2620 *
2621 * @note This will be defined only if EMIOS channel 13 is configured in GPT, ICU,
2622 * OCU or PWM mode.
2623 */
ISR(EMIOS1_CH13_IRQ)2624 ISR(EMIOS1_CH13_IRQ)
2625 {
2626 #if (defined EMIOS_1_CH_13_ISR_USED)
2627 #if (defined GPT_EMIOS_1_CH_13_ISR_USED)
2628 Emios_Gpt_IrqHandler(1, 13);
2629 #endif
2630
2631 #if (defined ICU_EMIOS_1_CH_13_ISR_USED)
2632 Emios_Icu_IrqHandler(1, 13);
2633 #endif
2634
2635 #if (defined OCU_EMIOS_1_CH_13_ISR_USED)
2636 Emios_Ocu_IrqHandler(1, 13);
2637 #endif
2638
2639 #if (defined PWM_EMIOS_1_CH_13_ISR_USED)
2640 Emios_Pwm_IrqHandler(1, 13);
2641 #endif
2642 #endif
2643 }
2644 #endif
2645
2646 #if (\
2647 (defined GPT_EMIOS_1_CH_14_ISR_USED) ||\
2648 (defined ICU_EMIOS_1_CH_14_ISR_USED) ||\
2649 (defined OCU_EMIOS_1_CH_14_ISR_USED) ||\
2650 (defined PWM_EMIOS_1_CH_14_ISR_USED)\
2651 )
2652 /**
2653 * @brief Interrupt handler for EMIOS channel 14 for Emios instance 1
2654 * @details Process the interrupt of EMIOS channel 14
2655 *
2656 * @note This will be defined only if EMIOS channel 14 is configured in GPT, ICU,
2657 * OCU or PWM mode.
2658 */
ISR(EMIOS1_CH14_IRQ)2659 ISR(EMIOS1_CH14_IRQ)
2660 {
2661 #if (defined EMIOS_1_CH_14_ISR_USED)
2662 #if (defined GPT_EMIOS_1_CH_14_ISR_USED)
2663 Emios_Gpt_Wsc_IrqHandler(1, 14);
2664 #endif
2665
2666 #if (defined ICU_EMIOS_1_CH_14_ISR_USED)
2667 Emios_Icu_Wsc_IrqHandler(1, 14);
2668 #endif
2669
2670 #if (defined OCU_EMIOS_1_CH_14_ISR_USED)
2671 Emios_Ocu_Wsc_IrqHandler(1, 14);
2672 #endif
2673
2674 #if (defined PWM_EMIOS_1_CH_14_ISR_USED)
2675 Emios_Pwm_Wsc_IrqHandler(1, 14);
2676 #endif
2677 #endif
2678 }
2679 #endif
2680
2681 #if (\
2682 (defined GPT_EMIOS_1_CH_15_ISR_USED) ||\
2683 (defined ICU_EMIOS_1_CH_15_ISR_USED) ||\
2684 (defined OCU_EMIOS_1_CH_15_ISR_USED) ||\
2685 (defined PWM_EMIOS_1_CH_15_ISR_USED)\
2686 )
2687 /**
2688 * @brief Interrupt handler for EMIOS channel 15 for Emios instance 1
2689 * @details Process the interrupt of EMIOS channel 15
2690 *
2691 * @note This will be defined only if EMIOS channel 15 is configured in GPT, ICU,
2692 * OCU or PWM mode.
2693 */
ISR(EMIOS1_CH15_IRQ)2694 ISR(EMIOS1_CH15_IRQ)
2695 {
2696 #if (defined EMIOS_1_CH_15_ISR_USED)
2697 #if (defined GPT_EMIOS_1_CH_15_ISR_USED)
2698 Emios_Gpt_IrqHandler(1, 15);
2699 #endif
2700
2701 #if (defined ICU_EMIOS_1_CH_15_ISR_USED)
2702 Emios_Icu_IrqHandler(1, 15);
2703 #endif
2704
2705 #if (defined OCU_EMIOS_1_CH_15_ISR_USED)
2706 Emios_Ocu_IrqHandler(1, 15);
2707 #endif
2708
2709 #if (defined PWM_EMIOS_1_CH_15_ISR_USED)
2710 Emios_Pwm_IrqHandler(1, 15);
2711 #endif
2712 #endif
2713 }
2714 #endif
2715
2716 #if (\
2717 (defined GPT_EMIOS_1_CH_16_ISR_USED) ||\
2718 (defined ICU_EMIOS_1_CH_16_ISR_USED) ||\
2719 (defined OCU_EMIOS_1_CH_16_ISR_USED) ||\
2720 (defined PWM_EMIOS_1_CH_16_ISR_USED)\
2721 )
2722 /**
2723 * @brief Interrupt handler for EMIOS channel 16 for Emios instance 1
2724 * @details Process the interrupt of EMIOS channel 16
2725 *
2726 * @note This will be defined only if EMIOS channel 16 is configured in GPT, ICU,
2727 * OCU or PWM mode.
2728 */
ISR(EMIOS1_CH16_IRQ)2729 ISR(EMIOS1_CH16_IRQ)
2730 {
2731 #if (defined EMIOS_1_CH_16_ISR_USED)
2732 #if (defined GPT_EMIOS_1_CH_16_ISR_USED)
2733 Emios_Gpt_IrqHandler(1, 16);
2734 #endif
2735
2736 #if (defined ICU_EMIOS_1_CH_16_ISR_USED)
2737 Emios_Icu_IrqHandler(1, 16);
2738 #endif
2739
2740 #if (defined OCU_EMIOS_1_CH_16_ISR_USED)
2741 Emios_Ocu_IrqHandler(1, 16);
2742 #endif
2743
2744 #if (defined PWM_EMIOS_1_CH_16_ISR_USED)
2745 Emios_Pwm_IrqHandler(1, 16);
2746 #endif
2747 #endif
2748 }
2749 #endif
2750
2751 #if (\
2752 (defined GPT_EMIOS_1_CH_17_ISR_USED) ||\
2753 (defined ICU_EMIOS_1_CH_17_ISR_USED) ||\
2754 (defined OCU_EMIOS_1_CH_17_ISR_USED) ||\
2755 (defined PWM_EMIOS_1_CH_17_ISR_USED)\
2756 )
2757 /**
2758 * @brief Interrupt handler for EMIOS channel 17 for Emios instance 1
2759 * @details Process the interrupt of EMIOS channel 17
2760 *
2761 * @note This will be defined only if EMIOS channel 17 is configured in GPT, ICU,
2762 * OCU or PWM mode.
2763 */
ISR(EMIOS1_CH17_IRQ)2764 ISR(EMIOS1_CH17_IRQ)
2765 {
2766 #if (defined EMIOS_1_CH_17_ISR_USED)
2767 #if (defined GPT_EMIOS_1_CH_17_ISR_USED)
2768 Emios_Gpt_IrqHandler(1, 17);
2769 #endif
2770
2771 #if (defined ICU_EMIOS_1_CH_17_ISR_USED)
2772 Emios_Icu_IrqHandler(1, 17);
2773 #endif
2774
2775 #if (defined OCU_EMIOS_1_CH_17_ISR_USED)
2776 Emios_Ocu_IrqHandler(1, 17);
2777 #endif
2778
2779 #if (defined PWM_EMIOS_1_CH_17_ISR_USED)
2780 Emios_Pwm_IrqHandler(1, 17);
2781 #endif
2782 #endif
2783 }
2784 #endif
2785
2786 #if (\
2787 (defined GPT_EMIOS_1_CH_18_ISR_USED) ||\
2788 (defined ICU_EMIOS_1_CH_18_ISR_USED) ||\
2789 (defined OCU_EMIOS_1_CH_18_ISR_USED) ||\
2790 (defined PWM_EMIOS_1_CH_18_ISR_USED)\
2791 )
2792 /**
2793 * @brief Interrupt handler for EMIOS channel 18 for Emios instance 1
2794 * @details Process the interrupt of EMIOS channel 18
2795 *
2796 * @note This will be defined only if EMIOS channel 18 is configured in GPT, ICU,
2797 * OCU or PWM mode.
2798 */
ISR(EMIOS1_CH18_IRQ)2799 ISR(EMIOS1_CH18_IRQ)
2800 {
2801 #if (defined EMIOS_1_CH_18_ISR_USED)
2802 #if (defined GPT_EMIOS_1_CH_18_ISR_USED)
2803 Emios_Gpt_IrqHandler(1, 18);
2804 #endif
2805
2806 #if (defined ICU_EMIOS_1_CH_18_ISR_USED)
2807 Emios_Icu_IrqHandler(1, 18);
2808 #endif
2809
2810 #if (defined OCU_EMIOS_1_CH_18_ISR_USED)
2811 Emios_Ocu_IrqHandler(1, 18);
2812 #endif
2813
2814 #if (defined PWM_EMIOS_1_CH_18_ISR_USED)
2815 Emios_Pwm_IrqHandler(1, 18);
2816 #endif
2817 #endif
2818 }
2819 #endif
2820
2821 #if (\
2822 (defined GPT_EMIOS_1_CH_19_ISR_USED) ||\
2823 (defined ICU_EMIOS_1_CH_19_ISR_USED) ||\
2824 (defined OCU_EMIOS_1_CH_19_ISR_USED) ||\
2825 (defined PWM_EMIOS_1_CH_19_ISR_USED)\
2826 )
2827 /**
2828 * @brief Interrupt handler for EMIOS channel 19 for Emios instance 1
2829 * @details Process the interrupt of EMIOS channel 19
2830 *
2831 * @note This will be defined only if EMIOS channel 19 is configured in GPT, ICU,
2832 * OCU or PWM mode.
2833 */
ISR(EMIOS1_CH19_IRQ)2834 ISR(EMIOS1_CH19_IRQ)
2835 {
2836 #if (defined EMIOS_1_CH_19_ISR_USED)
2837 #if (defined GPT_EMIOS_1_CH_19_ISR_USED)
2838 Emios_Gpt_IrqHandler(1, 19);
2839 #endif
2840
2841 #if (defined ICU_EMIOS_1_CH_19_ISR_USED)
2842 Emios_Icu_IrqHandler(1, 19);
2843 #endif
2844
2845 #if (defined OCU_EMIOS_1_CH_19_ISR_USED)
2846 Emios_Ocu_IrqHandler(1, 19);
2847 #endif
2848
2849 #if (defined PWM_EMIOS_1_CH_19_ISR_USED)
2850 Emios_Pwm_IrqHandler(1, 19);
2851 #endif
2852 #endif
2853 }
2854 #endif
2855
2856 #if (\
2857 (defined GPT_EMIOS_1_CH_20_ISR_USED) ||\
2858 (defined ICU_EMIOS_1_CH_20_ISR_USED) ||\
2859 (defined OCU_EMIOS_1_CH_20_ISR_USED) ||\
2860 (defined PWM_EMIOS_1_CH_20_ISR_USED)\
2861 )
2862 /**
2863 * @brief Interrupt handler for EMIOS channel 20 for Emios instance 1
2864 * @details Process the interrupt of EMIOS channel 20
2865 *
2866 * @note This will be defined only if EMIOS channel 20 is configured in GPT, ICU,
2867 * OCU or PWM mode.
2868 */
ISR(EMIOS1_CH20_IRQ)2869 ISR(EMIOS1_CH20_IRQ)
2870 {
2871 #if (defined EMIOS_1_CH_20_ISR_USED)
2872 #if (defined GPT_EMIOS_1_CH_20_ISR_USED)
2873 Emios_Gpt_IrqHandler(1, 20);
2874 #endif
2875
2876 #if (defined ICU_EMIOS_1_CH_20_ISR_USED)
2877 Emios_Icu_IrqHandler(1, 20);
2878 #endif
2879
2880 #if (defined OCU_EMIOS_1_CH_20_ISR_USED)
2881 Emios_Ocu_IrqHandler(1, 20);
2882 #endif
2883
2884 #if (defined PWM_EMIOS_1_CH_20_ISR_USED)
2885 Emios_Pwm_IrqHandler(1, 20);
2886 #endif
2887 #endif
2888 }
2889 #endif
2890
2891 #if (\
2892 (defined GPT_EMIOS_1_CH_21_ISR_USED) ||\
2893 (defined ICU_EMIOS_1_CH_21_ISR_USED) ||\
2894 (defined OCU_EMIOS_1_CH_21_ISR_USED) ||\
2895 (defined PWM_EMIOS_1_CH_21_ISR_USED)\
2896 )
2897 /**
2898 * @brief Interrupt handler for EMIOS channel 21 for Emios instance 1
2899 * @details Process the interrupt of EMIOS channel 21
2900 *
2901 * @note This will be defined only if EMIOS channel 21 is configured in GPT, ICU,
2902 * OCU or PWM mode.
2903 */
ISR(EMIOS1_CH21_IRQ)2904 ISR(EMIOS1_CH21_IRQ)
2905 {
2906 #if (defined EMIOS_1_CH_21_ISR_USED)
2907 #if (defined GPT_EMIOS_1_CH_21_ISR_USED)
2908 Emios_Gpt_IrqHandler(1, 21);
2909 #endif
2910
2911 #if (defined ICU_EMIOS_1_CH_21_ISR_USED)
2912 Emios_Icu_IrqHandler(1, 21);
2913 #endif
2914
2915 #if (defined OCU_EMIOS_1_CH_21_ISR_USED)
2916 Emios_Ocu_IrqHandler(1, 21);
2917 #endif
2918
2919 #if (defined PWM_EMIOS_1_CH_21_ISR_USED)
2920 Emios_Pwm_IrqHandler(1, 21);
2921 #endif
2922 #endif
2923 }
2924 #endif
2925
2926 #if (\
2927 (defined GPT_EMIOS_1_CH_22_ISR_USED) ||\
2928 (defined ICU_EMIOS_1_CH_22_ISR_USED) ||\
2929 (defined OCU_EMIOS_1_CH_22_ISR_USED) ||\
2930 (defined PWM_EMIOS_1_CH_22_ISR_USED)\
2931 )
2932 /**
2933 * @brief Interrupt handler for EMIOS channel 22 for Emios instance 1
2934 * @details Process the interrupt of EMIOS channel 22
2935 *
2936 * @note This will be defined only if EMIOS channel 22 is configured in GPT, ICU,
2937 * OCU or PWM mode.
2938 */
ISR(EMIOS1_CH22_IRQ)2939 ISR(EMIOS1_CH22_IRQ)
2940 {
2941 #if (defined EMIOS_1_CH_22_ISR_USED)
2942 #if (defined GPT_EMIOS_1_CH_22_ISR_USED)
2943 Emios_Gpt_IrqHandler(1, 22);
2944 #endif
2945
2946 #if (defined ICU_EMIOS_1_CH_22_ISR_USED)
2947 Emios_Icu_IrqHandler(1, 22);
2948 #endif
2949
2950 #if (defined OCU_EMIOS_1_CH_22_ISR_USED)
2951 Emios_Ocu_IrqHandler(1, 22);
2952 #endif
2953
2954 #if (defined PWM_EMIOS_1_CH_22_ISR_USED)
2955 Emios_Pwm_IrqHandler(1, 22);
2956 #endif
2957 #endif
2958 }
2959 #endif
2960
2961 #if (\
2962 (defined GPT_EMIOS_1_CH_23_ISR_USED) ||\
2963 (defined ICU_EMIOS_1_CH_23_ISR_USED) ||\
2964 (defined OCU_EMIOS_1_CH_23_ISR_USED) ||\
2965 (defined PWM_EMIOS_1_CH_23_ISR_USED)\
2966 )
2967 /**
2968 * @brief Interrupt handler for EMIOS channel 23 for Emios instance 1
2969 * @details Process the interrupt of EMIOS channel 23
2970 *
2971 * @note This will be defined only if EMIOS channel 23 is configured in GPT, ICU,
2972 * OCU or PWM mode.
2973 */
ISR(EMIOS1_CH23_IRQ)2974 ISR(EMIOS1_CH23_IRQ)
2975 {
2976 #if (defined EMIOS_1_CH_23_ISR_USED)
2977 #if (defined GPT_EMIOS_1_CH_23_ISR_USED)
2978 Emios_Gpt_IrqHandler(1, 23);
2979 #endif
2980
2981 #if (defined ICU_EMIOS_1_CH_23_ISR_USED)
2982 Emios_Icu_IrqHandler(1, 23);
2983 #endif
2984
2985 #if (defined OCU_EMIOS_1_CH_23_ISR_USED)
2986 Emios_Ocu_IrqHandler(1, 23);
2987 #endif
2988
2989 #if (defined PWM_EMIOS_1_CH_23_ISR_USED)
2990 Emios_Pwm_IrqHandler(1, 23);
2991 #endif
2992 #endif
2993 }
2994 #endif
2995
2996 #if (\
2997 (defined GPT_EMIOS_1_CH_24_ISR_USED) ||\
2998 (defined ICU_EMIOS_1_CH_24_ISR_USED) ||\
2999 (defined OCU_EMIOS_1_CH_24_ISR_USED) ||\
3000 (defined PWM_EMIOS_1_CH_24_ISR_USED)\
3001 )
3002 /**
3003 * @brief Interrupt handler for EMIOS channel 24 for Emios instance 1
3004 * @details Process the interrupt of EMIOS channel 24
3005 *
3006 * @note This will be defined only if EMIOS channel 24 is configured in GPT, ICU,
3007 * OCU or PWM mode.
3008 */
ISR(EMIOS1_CH24_IRQ)3009 ISR(EMIOS1_CH24_IRQ)
3010 {
3011 #if (defined EMIOS_1_CH_24_ISR_USED)
3012 #if (defined GPT_EMIOS_1_CH_24_ISR_USED)
3013 Emios_Gpt_IrqHandler(1, 24);
3014 #endif
3015
3016 #if (defined ICU_EMIOS_1_CH_24_ISR_USED)
3017 Emios_Icu_IrqHandler(1, 24);
3018 #endif
3019
3020 #if (defined OCU_EMIOS_1_CH_24_ISR_USED)
3021 Emios_Ocu_IrqHandler(1, 24);
3022 #endif
3023
3024 #if (defined PWM_EMIOS_1_CH_24_ISR_USED)
3025 Emios_Pwm_IrqHandler(1, 24);
3026 #endif
3027 #endif
3028 }
3029 #endif
3030
3031 #if (\
3032 (defined GPT_EMIOS_1_CH_25_ISR_USED) ||\
3033 (defined ICU_EMIOS_1_CH_25_ISR_USED) ||\
3034 (defined OCU_EMIOS_1_CH_25_ISR_USED) ||\
3035 (defined PWM_EMIOS_1_CH_25_ISR_USED)\
3036 )
3037 /**
3038 * @brief Interrupt handler for EMIOS channel 25 for Emios instance 1
3039 * @details Process the interrupt of EMIOS channel 25
3040 *
3041 * @note This will be defined only if EMIOS channel 25 is configured in GPT, ICU,
3042 * OCU or PWM mode.
3043 */
ISR(EMIOS1_CH25_IRQ)3044 ISR(EMIOS1_CH25_IRQ)
3045 {
3046 #if (defined EMIOS_1_CH_25_ISR_USED)
3047 #if (defined GPT_EMIOS_1_CH_25_ISR_USED)
3048 Emios_Gpt_IrqHandler(1, 25);
3049 #endif
3050
3051 #if (defined ICU_EMIOS_1_CH_25_ISR_USED)
3052 Emios_Icu_IrqHandler(1, 25);
3053 #endif
3054
3055 #if (defined OCU_EMIOS_1_CH_25_ISR_USED)
3056 Emios_Ocu_IrqHandler(1, 25);
3057 #endif
3058
3059 #if (defined PWM_EMIOS_1_CH_25_ISR_USED)
3060 Emios_Pwm_IrqHandler(1, 25);
3061 #endif
3062 #endif
3063 }
3064 #endif
3065
3066 #if (\
3067 (defined GPT_EMIOS_1_CH_26_ISR_USED) ||\
3068 (defined ICU_EMIOS_1_CH_26_ISR_USED) ||\
3069 (defined OCU_EMIOS_1_CH_26_ISR_USED) ||\
3070 (defined PWM_EMIOS_1_CH_26_ISR_USED)\
3071 )
3072 /**
3073 * @brief Interrupt handler for EMIOS channel 26 for Emios instance 1
3074 * @details Process the interrupt of EMIOS channel 26
3075 *
3076 * @note This will be defined only if EMIOS channel 26 is configured in GPT, ICU,
3077 * OCU or PWM mode.
3078 */
ISR(EMIOS1_CH26_IRQ)3079 ISR(EMIOS1_CH26_IRQ)
3080 {
3081 #if (defined EMIOS_1_CH_26_ISR_USED)
3082 #if (defined GPT_EMIOS_1_CH_26_ISR_USED)
3083 Emios_Gpt_IrqHandler(1, 26);
3084 #endif
3085
3086 #if (defined ICU_EMIOS_1_CH_26_ISR_USED)
3087 Emios_Icu_IrqHandler(1, 26);
3088 #endif
3089
3090 #if (defined OCU_EMIOS_1_CH_26_ISR_USED)
3091 Emios_Ocu_IrqHandler(1, 26);
3092 #endif
3093
3094 #if (defined PWM_EMIOS_1_CH_26_ISR_USED)
3095 Emios_Pwm_IrqHandler(1, 26);
3096 #endif
3097 #endif
3098 }
3099 #endif
3100
3101 #if (\
3102 (defined GPT_EMIOS_1_CH_27_ISR_USED) ||\
3103 (defined ICU_EMIOS_1_CH_27_ISR_USED) ||\
3104 (defined OCU_EMIOS_1_CH_27_ISR_USED) ||\
3105 (defined PWM_EMIOS_1_CH_27_ISR_USED)\
3106 )
3107 /**
3108 * @brief Interrupt handler for EMIOS channel 27 for Emios instance 1
3109 * @details Process the interrupt of EMIOS channel 27
3110 *
3111 * @note This will be defined only if EMIOS channel 27 is configured in GPT, ICU,
3112 * OCU or PWM mode.
3113 */
ISR(EMIOS1_CH27_IRQ)3114 ISR(EMIOS1_CH27_IRQ)
3115 {
3116 #if (defined EMIOS_1_CH_27_ISR_USED)
3117 #if (defined GPT_EMIOS_1_CH_27_ISR_USED)
3118 Emios_Gpt_IrqHandler(1, 27);
3119 #endif
3120
3121 #if (defined ICU_EMIOS_1_CH_27_ISR_USED)
3122 Emios_Icu_IrqHandler(1, 27);
3123 #endif
3124
3125 #if (defined OCU_EMIOS_1_CH_27_ISR_USED)
3126 Emios_Ocu_IrqHandler(1, 27);
3127 #endif
3128
3129 #if (defined PWM_EMIOS_1_CH_27_ISR_USED)
3130 Emios_Pwm_IrqHandler(1, 27);
3131 #endif
3132 #endif
3133 }
3134 #endif
3135
3136 #if (\
3137 (defined GPT_EMIOS_1_CH_28_ISR_USED) ||\
3138 (defined ICU_EMIOS_1_CH_28_ISR_USED) ||\
3139 (defined OCU_EMIOS_1_CH_28_ISR_USED) ||\
3140 (defined PWM_EMIOS_1_CH_28_ISR_USED)\
3141 )
3142 /**
3143 * @brief Interrupt handler for EMIOS channel 28 for Emios instance 1
3144 * @details Process the interrupt of EMIOS channel 28
3145 *
3146 * @note This will be defined only if EMIOS channel 28 is configured in GPT, ICU,
3147 * OCU or PWM mode.
3148 */
ISR(EMIOS1_CH28_IRQ)3149 ISR(EMIOS1_CH28_IRQ)
3150 {
3151 #if (defined EMIOS_1_CH_28_ISR_USED)
3152 #if (defined GPT_EMIOS_1_CH_28_ISR_USED)
3153 Emios_Gpt_IrqHandler(1, 28);
3154 #endif
3155
3156 #if (defined ICU_EMIOS_1_CH_28_ISR_USED)
3157 Emios_Icu_IrqHandler(1, 28);
3158 #endif
3159
3160 #if (defined OCU_EMIOS_1_CH_28_ISR_USED)
3161 Emios_Ocu_IrqHandler(1, 28);
3162 #endif
3163
3164 #if (defined PWM_EMIOS_1_CH_28_ISR_USED)
3165 Emios_Pwm_IrqHandler(1, 28);
3166 #endif
3167 #endif
3168 }
3169 #endif
3170
3171 #if (\
3172 (defined GPT_EMIOS_1_CH_29_ISR_USED) ||\
3173 (defined ICU_EMIOS_1_CH_29_ISR_USED) ||\
3174 (defined OCU_EMIOS_1_CH_29_ISR_USED) ||\
3175 (defined PWM_EMIOS_1_CH_29_ISR_USED)\
3176 )
3177 /**
3178 * @brief Interrupt handler for EMIOS channel 29 for Emios instance 1
3179 * @details Process the interrupt of EMIOS channel 29
3180 *
3181 * @note This will be defined only if EMIOS channel 29 is configured in GPT, ICU,
3182 * OCU or PWM mode.
3183 */
ISR(EMIOS1_CH29_IRQ)3184 ISR(EMIOS1_CH29_IRQ)
3185 {
3186 #if (defined EMIOS_1_CH_29_ISR_USED)
3187 #if (defined GPT_EMIOS_1_CH_29_ISR_USED)
3188 Emios_Gpt_IrqHandler(1, 29);
3189 #endif
3190
3191 #if (defined ICU_EMIOS_1_CH_29_ISR_USED)
3192 Emios_Icu_IrqHandler(1, 29);
3193 #endif
3194
3195 #if (defined OCU_EMIOS_1_CH_29_ISR_USED)
3196 Emios_Ocu_IrqHandler(1, 29);
3197 #endif
3198
3199 #if (defined PWM_EMIOS_1_CH_29_ISR_USED)
3200 Emios_Pwm_IrqHandler(1, 29);
3201 #endif
3202 #endif
3203 }
3204 #endif
3205
3206 #if (\
3207 (defined GPT_EMIOS_1_CH_30_ISR_USED) ||\
3208 (defined ICU_EMIOS_1_CH_30_ISR_USED) ||\
3209 (defined OCU_EMIOS_1_CH_30_ISR_USED) ||\
3210 (defined PWM_EMIOS_1_CH_30_ISR_USED)\
3211 )
3212 /**
3213 * @brief Interrupt handler for EMIOS channel 30 for Emios instance 1
3214 * @details Process the interrupt of EMIOS channel 30
3215 *
3216 * @note This will be defined only if EMIOS channel 30 is configured in GPT, ICU,
3217 * OCU or PWM mode.
3218 */
ISR(EMIOS1_CH30_IRQ)3219 ISR(EMIOS1_CH30_IRQ)
3220 {
3221 #if (defined EMIOS_1_CH_30_ISR_USED)
3222 #if (defined GPT_EMIOS_1_CH_30_ISR_USED)
3223 Emios_Gpt_IrqHandler(1, 30);
3224 #endif
3225
3226 #if (defined ICU_EMIOS_1_CH_30_ISR_USED)
3227 Emios_Icu_IrqHandler(1, 30);
3228 #endif
3229
3230 #if (defined OCU_EMIOS_1_CH_30_ISR_USED)
3231 Emios_Ocu_IrqHandler(1, 30);
3232 #endif
3233
3234 #if (defined PWM_EMIOS_1_CH_30_ISR_USED)
3235 Emios_Pwm_IrqHandler(1, 30);
3236 #endif
3237 #endif
3238 }
3239 #endif
3240
3241 #if (\
3242 (defined GPT_EMIOS_1_CH_31_ISR_USED) ||\
3243 (defined ICU_EMIOS_1_CH_31_ISR_USED) ||\
3244 (defined OCU_EMIOS_1_CH_31_ISR_USED) ||\
3245 (defined PWM_EMIOS_1_CH_31_ISR_USED)\
3246 )
3247 /**
3248 * @brief Interrupt handler for EMIOS channel 31 for Emios instance 1
3249 * @details Process the interrupt of EMIOS channel 31
3250 *
3251 * @note This will be defined only if EMIOS channel 31 is configured in GPT, ICU,
3252 * OCU or PWM mode.
3253 */
ISR(EMIOS1_CH31_IRQ)3254 ISR(EMIOS1_CH31_IRQ)
3255 {
3256 #if (defined EMIOS_1_CH_31_ISR_USED)
3257 #if (defined GPT_EMIOS_1_CH_31_ISR_USED)
3258 Emios_Gpt_IrqHandler(1, 31);
3259 #endif
3260
3261 #if (defined ICU_EMIOS_1_CH_31_ISR_USED)
3262 Emios_Icu_IrqHandler(1, 31);
3263 #endif
3264
3265 #if (defined OCU_EMIOS_1_CH_31_ISR_USED)
3266 Emios_Ocu_IrqHandler(1, 31);
3267 #endif
3268
3269 #if (defined PWM_EMIOS_1_CH_31_ISR_USED)
3270 Emios_Pwm_IrqHandler(1, 31);
3271 #endif
3272 #endif
3273 }
3274 #endif
3275
3276 #define MCL_STOP_SEC_CODE
3277 #include "Mcl_MemMap.h"
3278
3279 #ifdef __cplusplus
3280 }
3281 #endif
3282
3283 /** @} */
3284
