1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_XBIC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_XBIC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_XBIC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_XBIC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- XBIC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup XBIC_Peripheral_Access_Layer XBIC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** XBIC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t MCR; /**< XBIC Module Control, offset: 0x0 */ 74 __IO uint32_t EIR; /**< XBIC Error Injection Attributes, offset: 0x4 */ 75 __IO uint32_t ESR; /**< XBIC Error Status Attributes, offset: 0x8 */ 76 __I uint32_t EAR; /**< XBIC Error Address, offset: 0xC */ 77 } XBIC_Type, *XBIC_MemMapPtr; 78 79 /** Number of instances of the XBIC module. */ 80 #define XBIC_INSTANCE_COUNT (4u) 81 82 /* XBIC - Peripheral instance base addresses */ 83 /** Peripheral CE_XBIC base address */ 84 #define IP_CE_XBIC_BASE (0x44850000u) 85 /** Peripheral CE_XBIC base pointer */ 86 #define IP_CE_XBIC ((XBIC_Type *)IP_CE_XBIC_BASE) 87 /** Peripheral AES__FEED_XBIC_AHB base address */ 88 #define IP_AES__FEED_XBIC_AHB_BASE (0x472C0000u) 89 /** Peripheral AES__FEED_XBIC_AHB base pointer */ 90 #define IP_AES__FEED_XBIC_AHB ((XBIC_Type *)IP_AES__FEED_XBIC_AHB_BASE) 91 /** Peripheral AES__RESULT_XBIC_AHB base address */ 92 #define IP_AES__RESULT_XBIC_AHB_BASE (0x472D0000u) 93 /** Peripheral AES__RESULT_XBIC_AHB base pointer */ 94 #define IP_AES__RESULT_XBIC_AHB ((XBIC_Type *)IP_AES__RESULT_XBIC_AHB_BASE) 95 /** Peripheral SMU__XBIC base address */ 96 #define IP_SMU__XBIC_BASE (0x45050000u) 97 /** Peripheral SMU__XBIC base pointer */ 98 #define IP_SMU__XBIC ((XBIC_Type *)IP_SMU__XBIC_BASE) 99 /** Array initializer of XBIC peripheral base addresses */ 100 #define IP_XBIC_BASE_ADDRS { IP_CE_XBIC_BASE, IP_AES__FEED_XBIC_AHB_BASE, IP_AES__RESULT_XBIC_AHB_BASE, IP_SMU__XBIC_BASE } 101 /** Array initializer of XBIC peripheral base pointers */ 102 #define IP_XBIC_BASE_PTRS { IP_CE_XBIC, IP_AES__FEED_XBIC_AHB, IP_AES__RESULT_XBIC_AHB, IP_SMU__XBIC } 103 104 /* ---------------------------------------------------------------------------- 105 -- XBIC Register Masks 106 ---------------------------------------------------------------------------- */ 107 108 /*! 109 * @addtogroup XBIC_Register_Masks XBIC Register Masks 110 * @{ 111 */ 112 113 /*! @name MCR - XBIC Module Control */ 114 /*! @{ */ 115 116 #define XBIC_MCR_ME5_MASK (0x40000U) 117 #define XBIC_MCR_ME5_SHIFT (18U) 118 #define XBIC_MCR_ME5_WIDTH (1U) 119 #define XBIC_MCR_ME5(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_ME5_SHIFT)) & XBIC_MCR_ME5_MASK) 120 121 #define XBIC_MCR_ME4_MASK (0x80000U) 122 #define XBIC_MCR_ME4_SHIFT (19U) 123 #define XBIC_MCR_ME4_WIDTH (1U) 124 #define XBIC_MCR_ME4(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_ME4_SHIFT)) & XBIC_MCR_ME4_MASK) 125 126 #define XBIC_MCR_ME3_MASK (0x100000U) 127 #define XBIC_MCR_ME3_SHIFT (20U) 128 #define XBIC_MCR_ME3_WIDTH (1U) 129 #define XBIC_MCR_ME3(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_ME3_SHIFT)) & XBIC_MCR_ME3_MASK) 130 131 #define XBIC_MCR_ME2_MASK (0x200000U) 132 #define XBIC_MCR_ME2_SHIFT (21U) 133 #define XBIC_MCR_ME2_WIDTH (1U) 134 #define XBIC_MCR_ME2(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_ME2_SHIFT)) & XBIC_MCR_ME2_MASK) 135 136 #define XBIC_MCR_ME1_MASK (0x400000U) 137 #define XBIC_MCR_ME1_SHIFT (22U) 138 #define XBIC_MCR_ME1_WIDTH (1U) 139 #define XBIC_MCR_ME1(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_ME1_SHIFT)) & XBIC_MCR_ME1_MASK) 140 141 #define XBIC_MCR_ME0_MASK (0x800000U) 142 #define XBIC_MCR_ME0_SHIFT (23U) 143 #define XBIC_MCR_ME0_WIDTH (1U) 144 #define XBIC_MCR_ME0(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_ME0_SHIFT)) & XBIC_MCR_ME0_MASK) 145 146 #define XBIC_MCR_SE7_MASK (0x1000000U) 147 #define XBIC_MCR_SE7_SHIFT (24U) 148 #define XBIC_MCR_SE7_WIDTH (1U) 149 #define XBIC_MCR_SE7(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE7_SHIFT)) & XBIC_MCR_SE7_MASK) 150 151 #define XBIC_MCR_SE6_MASK (0x2000000U) 152 #define XBIC_MCR_SE6_SHIFT (25U) 153 #define XBIC_MCR_SE6_WIDTH (1U) 154 #define XBIC_MCR_SE6(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE6_SHIFT)) & XBIC_MCR_SE6_MASK) 155 156 #define XBIC_MCR_SE5_MASK (0x4000000U) 157 #define XBIC_MCR_SE5_SHIFT (26U) 158 #define XBIC_MCR_SE5_WIDTH (1U) 159 #define XBIC_MCR_SE5(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE5_SHIFT)) & XBIC_MCR_SE5_MASK) 160 161 #define XBIC_MCR_SE4_MASK (0x8000000U) 162 #define XBIC_MCR_SE4_SHIFT (27U) 163 #define XBIC_MCR_SE4_WIDTH (1U) 164 #define XBIC_MCR_SE4(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE4_SHIFT)) & XBIC_MCR_SE4_MASK) 165 166 #define XBIC_MCR_SE3_MASK (0x10000000U) 167 #define XBIC_MCR_SE3_SHIFT (28U) 168 #define XBIC_MCR_SE3_WIDTH (1U) 169 #define XBIC_MCR_SE3(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE3_SHIFT)) & XBIC_MCR_SE3_MASK) 170 171 #define XBIC_MCR_SE2_MASK (0x20000000U) 172 #define XBIC_MCR_SE2_SHIFT (29U) 173 #define XBIC_MCR_SE2_WIDTH (1U) 174 #define XBIC_MCR_SE2(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE2_SHIFT)) & XBIC_MCR_SE2_MASK) 175 176 #define XBIC_MCR_SE1_MASK (0x40000000U) 177 #define XBIC_MCR_SE1_SHIFT (30U) 178 #define XBIC_MCR_SE1_WIDTH (1U) 179 #define XBIC_MCR_SE1(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE1_SHIFT)) & XBIC_MCR_SE1_MASK) 180 181 #define XBIC_MCR_SE0_MASK (0x80000000U) 182 #define XBIC_MCR_SE0_SHIFT (31U) 183 #define XBIC_MCR_SE0_WIDTH (1U) 184 #define XBIC_MCR_SE0(x) (((uint32_t)(((uint32_t)(x)) << XBIC_MCR_SE0_SHIFT)) & XBIC_MCR_SE0_MASK) 185 /*! @} */ 186 187 /*! @name EIR - XBIC Error Injection Attributes */ 188 /*! @{ */ 189 190 #define XBIC_EIR_SYN_MASK (0xFFU) 191 #define XBIC_EIR_SYN_SHIFT (0U) 192 #define XBIC_EIR_SYN_WIDTH (8U) 193 #define XBIC_EIR_SYN(x) (((uint32_t)(((uint32_t)(x)) << XBIC_EIR_SYN_SHIFT)) & XBIC_EIR_SYN_MASK) 194 195 #define XBIC_EIR_MST_MASK (0xF00U) 196 #define XBIC_EIR_MST_SHIFT (8U) 197 #define XBIC_EIR_MST_WIDTH (4U) 198 #define XBIC_EIR_MST(x) (((uint32_t)(((uint32_t)(x)) << XBIC_EIR_MST_SHIFT)) & XBIC_EIR_MST_MASK) 199 200 #define XBIC_EIR_SLV_MASK (0x7000U) 201 #define XBIC_EIR_SLV_SHIFT (12U) 202 #define XBIC_EIR_SLV_WIDTH (3U) 203 #define XBIC_EIR_SLV(x) (((uint32_t)(((uint32_t)(x)) << XBIC_EIR_SLV_SHIFT)) & XBIC_EIR_SLV_MASK) 204 205 #define XBIC_EIR_EIE_MASK (0x80000000U) 206 #define XBIC_EIR_EIE_SHIFT (31U) 207 #define XBIC_EIR_EIE_WIDTH (1U) 208 #define XBIC_EIR_EIE(x) (((uint32_t)(((uint32_t)(x)) << XBIC_EIR_EIE_SHIFT)) & XBIC_EIR_EIE_MASK) 209 /*! @} */ 210 211 /*! @name ESR - XBIC Error Status Attributes */ 212 /*! @{ */ 213 214 #define XBIC_ESR_SYN_MASK (0xFFU) 215 #define XBIC_ESR_SYN_SHIFT (0U) 216 #define XBIC_ESR_SYN_WIDTH (8U) 217 #define XBIC_ESR_SYN(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_SYN_SHIFT)) & XBIC_ESR_SYN_MASK) 218 219 #define XBIC_ESR_MST_MASK (0xF00U) 220 #define XBIC_ESR_MST_SHIFT (8U) 221 #define XBIC_ESR_MST_WIDTH (4U) 222 #define XBIC_ESR_MST(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_MST_SHIFT)) & XBIC_ESR_MST_MASK) 223 224 #define XBIC_ESR_SLV_MASK (0x7000U) 225 #define XBIC_ESR_SLV_SHIFT (12U) 226 #define XBIC_ESR_SLV_WIDTH (3U) 227 #define XBIC_ESR_SLV(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_SLV_SHIFT)) & XBIC_ESR_SLV_MASK) 228 229 #define XBIC_ESR_DPME7_MASK (0x8000U) 230 #define XBIC_ESR_DPME7_SHIFT (15U) 231 #define XBIC_ESR_DPME7_WIDTH (1U) 232 #define XBIC_ESR_DPME7(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME7_SHIFT)) & XBIC_ESR_DPME7_MASK) 233 234 #define XBIC_ESR_DPME6_MASK (0x10000U) 235 #define XBIC_ESR_DPME6_SHIFT (16U) 236 #define XBIC_ESR_DPME6_WIDTH (1U) 237 #define XBIC_ESR_DPME6(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME6_SHIFT)) & XBIC_ESR_DPME6_MASK) 238 239 #define XBIC_ESR_DPME5_MASK (0x20000U) 240 #define XBIC_ESR_DPME5_SHIFT (17U) 241 #define XBIC_ESR_DPME5_WIDTH (1U) 242 #define XBIC_ESR_DPME5(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME5_SHIFT)) & XBIC_ESR_DPME5_MASK) 243 244 #define XBIC_ESR_DPME4_MASK (0x40000U) 245 #define XBIC_ESR_DPME4_SHIFT (18U) 246 #define XBIC_ESR_DPME4_WIDTH (1U) 247 #define XBIC_ESR_DPME4(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME4_SHIFT)) & XBIC_ESR_DPME4_MASK) 248 249 #define XBIC_ESR_DPME3_MASK (0x80000U) 250 #define XBIC_ESR_DPME3_SHIFT (19U) 251 #define XBIC_ESR_DPME3_WIDTH (1U) 252 #define XBIC_ESR_DPME3(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME3_SHIFT)) & XBIC_ESR_DPME3_MASK) 253 254 #define XBIC_ESR_DPME2_MASK (0x100000U) 255 #define XBIC_ESR_DPME2_SHIFT (20U) 256 #define XBIC_ESR_DPME2_WIDTH (1U) 257 #define XBIC_ESR_DPME2(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME2_SHIFT)) & XBIC_ESR_DPME2_MASK) 258 259 #define XBIC_ESR_DPME1_MASK (0x200000U) 260 #define XBIC_ESR_DPME1_SHIFT (21U) 261 #define XBIC_ESR_DPME1_WIDTH (1U) 262 #define XBIC_ESR_DPME1(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME1_SHIFT)) & XBIC_ESR_DPME1_MASK) 263 264 #define XBIC_ESR_DPME0_MASK (0x400000U) 265 #define XBIC_ESR_DPME0_SHIFT (22U) 266 #define XBIC_ESR_DPME0_WIDTH (1U) 267 #define XBIC_ESR_DPME0(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPME0_SHIFT)) & XBIC_ESR_DPME0_MASK) 268 269 #define XBIC_ESR_DPSE7_MASK (0x800000U) 270 #define XBIC_ESR_DPSE7_SHIFT (23U) 271 #define XBIC_ESR_DPSE7_WIDTH (1U) 272 #define XBIC_ESR_DPSE7(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE7_SHIFT)) & XBIC_ESR_DPSE7_MASK) 273 274 #define XBIC_ESR_DPSE6_MASK (0x1000000U) 275 #define XBIC_ESR_DPSE6_SHIFT (24U) 276 #define XBIC_ESR_DPSE6_WIDTH (1U) 277 #define XBIC_ESR_DPSE6(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE6_SHIFT)) & XBIC_ESR_DPSE6_MASK) 278 279 #define XBIC_ESR_DPSE5_MASK (0x2000000U) 280 #define XBIC_ESR_DPSE5_SHIFT (25U) 281 #define XBIC_ESR_DPSE5_WIDTH (1U) 282 #define XBIC_ESR_DPSE5(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE5_SHIFT)) & XBIC_ESR_DPSE5_MASK) 283 284 #define XBIC_ESR_DPSE4_MASK (0x4000000U) 285 #define XBIC_ESR_DPSE4_SHIFT (26U) 286 #define XBIC_ESR_DPSE4_WIDTH (1U) 287 #define XBIC_ESR_DPSE4(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE4_SHIFT)) & XBIC_ESR_DPSE4_MASK) 288 289 #define XBIC_ESR_DPSE3_MASK (0x8000000U) 290 #define XBIC_ESR_DPSE3_SHIFT (27U) 291 #define XBIC_ESR_DPSE3_WIDTH (1U) 292 #define XBIC_ESR_DPSE3(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE3_SHIFT)) & XBIC_ESR_DPSE3_MASK) 293 294 #define XBIC_ESR_DPSE2_MASK (0x10000000U) 295 #define XBIC_ESR_DPSE2_SHIFT (28U) 296 #define XBIC_ESR_DPSE2_WIDTH (1U) 297 #define XBIC_ESR_DPSE2(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE2_SHIFT)) & XBIC_ESR_DPSE2_MASK) 298 299 #define XBIC_ESR_DPSE1_MASK (0x20000000U) 300 #define XBIC_ESR_DPSE1_SHIFT (29U) 301 #define XBIC_ESR_DPSE1_WIDTH (1U) 302 #define XBIC_ESR_DPSE1(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE1_SHIFT)) & XBIC_ESR_DPSE1_MASK) 303 304 #define XBIC_ESR_DPSE0_MASK (0x40000000U) 305 #define XBIC_ESR_DPSE0_SHIFT (30U) 306 #define XBIC_ESR_DPSE0_WIDTH (1U) 307 #define XBIC_ESR_DPSE0(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_DPSE0_SHIFT)) & XBIC_ESR_DPSE0_MASK) 308 309 #define XBIC_ESR_VLD_MASK (0x80000000U) 310 #define XBIC_ESR_VLD_SHIFT (31U) 311 #define XBIC_ESR_VLD_WIDTH (1U) 312 #define XBIC_ESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << XBIC_ESR_VLD_SHIFT)) & XBIC_ESR_VLD_MASK) 313 /*! @} */ 314 315 /*! @name EAR - XBIC Error Address */ 316 /*! @{ */ 317 318 #define XBIC_EAR_ADDR_MASK (0xFFFFFFFFU) 319 #define XBIC_EAR_ADDR_SHIFT (0U) 320 #define XBIC_EAR_ADDR_WIDTH (32U) 321 #define XBIC_EAR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XBIC_EAR_ADDR_SHIFT)) & XBIC_EAR_ADDR_MASK) 322 /*! @} */ 323 324 /*! 325 * @} 326 */ /* end of group XBIC_Register_Masks */ 327 328 /*! 329 * @} 330 */ /* end of group XBIC_Peripheral_Access_Layer */ 331 332 #endif /* #if !defined(S32Z2_XBIC_H_) */ 333
