1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_VIRT_WRAP.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_VIRT_WRAP
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_VIRT_WRAP_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_VIRT_WRAP_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- VIRT_WRAP Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup VIRT_WRAP_Peripheral_Access_Layer VIRT_WRAP Peripheral Access Layer
68  * @{
69  */
70 
71 /** VIRT_WRAP - Size of Registers Arrays */
72 #define VIRT_WRAP_REG_A_COUNT                     32u
73 #define VIRT_WRAP_REG_B_COUNT                     32u
74 #define VIRT_WRAP_REG_C_COUNT                     1u
75 
76 /** VIRT_WRAP - Register Layout Typedef */
77 typedef struct {
78   __IO uint32_t REG_A[VIRT_WRAP_REG_A_COUNT];      /**< Parameter_n Register, array offset: 0x0, array step: 0x4 */
79   __IO uint32_t REG_B[VIRT_WRAP_REG_B_COUNT];      /**< Parameter_n Register, array offset: 0x80, array step: 0x4 */
80   __IO uint32_t REG_C[VIRT_WRAP_REG_C_COUNT];      /**< Parameter_n Register, array offset: 0x100, array step: 0x4 */
81 } VIRT_WRAP_Type, *VIRT_WRAP_MemMapPtr;
82 
83 /** Number of instances of the VIRT_WRAP module. */
84 #define VIRT_WRAP_INSTANCE_COUNT                 (5u)
85 
86 /* VIRT_WRAP - Peripheral instance base addresses */
87 /** Peripheral VIRT_WRAP_0 base address */
88 #define IP_VIRT_WRAP_0_BASE                      (0x40560000u)
89 /** Peripheral VIRT_WRAP_0 base pointer */
90 #define IP_VIRT_WRAP_0                           ((VIRT_WRAP_Type *)IP_VIRT_WRAP_0_BASE)
91 /** Peripheral VIRT_WRAP_1 base address */
92 #define IP_VIRT_WRAP_1_BASE                      (0x40D60000u)
93 /** Peripheral VIRT_WRAP_1 base pointer */
94 #define IP_VIRT_WRAP_1                           ((VIRT_WRAP_Type *)IP_VIRT_WRAP_1_BASE)
95 /** Peripheral VIRT_WRAP_3 base address */
96 #define IP_VIRT_WRAP_3_BASE                      (0x41D60000u)
97 /** Peripheral VIRT_WRAP_3 base pointer */
98 #define IP_VIRT_WRAP_3                           ((VIRT_WRAP_Type *)IP_VIRT_WRAP_3_BASE)
99 /** Peripheral VIRT_WRAP_4 base address */
100 #define IP_VIRT_WRAP_4_BASE                      (0x42560000u)
101 /** Peripheral VIRT_WRAP_4 base pointer */
102 #define IP_VIRT_WRAP_4                           ((VIRT_WRAP_Type *)IP_VIRT_WRAP_4_BASE)
103 /** Peripheral VIRT_WRAP_5 base address */
104 #define IP_VIRT_WRAP_5_BASE                      (0x42D60000u)
105 /** Peripheral VIRT_WRAP_5 base pointer */
106 #define IP_VIRT_WRAP_5                           ((VIRT_WRAP_Type *)IP_VIRT_WRAP_5_BASE)
107 /** Array initializer of VIRT_WRAP peripheral base addresses */
108 #define IP_VIRT_WRAP_BASE_ADDRS                  { IP_VIRT_WRAP_0_BASE, IP_VIRT_WRAP_1_BASE, IP_VIRT_WRAP_3_BASE, IP_VIRT_WRAP_4_BASE, IP_VIRT_WRAP_5_BASE }
109 /** Array initializer of VIRT_WRAP peripheral base pointers */
110 #define IP_VIRT_WRAP_BASE_PTRS                   { IP_VIRT_WRAP_0, IP_VIRT_WRAP_1, IP_VIRT_WRAP_3, IP_VIRT_WRAP_4, IP_VIRT_WRAP_5 }
111 
112 /* ----------------------------------------------------------------------------
113    -- VIRT_WRAP Register Masks
114    ---------------------------------------------------------------------------- */
115 
116 /*!
117  * @addtogroup VIRT_WRAP_Register_Masks VIRT_WRAP Register Masks
118  * @{
119  */
120 
121 /*! @name REG_A - Parameter_n Register */
122 /*! @{ */
123 
124 #define VIRT_WRAP_REG_A_PAD_0_MASK               (0x3U)
125 #define VIRT_WRAP_REG_A_PAD_0_SHIFT              (0U)
126 #define VIRT_WRAP_REG_A_PAD_0_WIDTH              (2U)
127 #define VIRT_WRAP_REG_A_PAD_0(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_0_SHIFT)) & VIRT_WRAP_REG_A_PAD_0_MASK)
128 
129 #define VIRT_WRAP_REG_A_PAD_1_MASK               (0xCU)
130 #define VIRT_WRAP_REG_A_PAD_1_SHIFT              (2U)
131 #define VIRT_WRAP_REG_A_PAD_1_WIDTH              (2U)
132 #define VIRT_WRAP_REG_A_PAD_1(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_1_SHIFT)) & VIRT_WRAP_REG_A_PAD_1_MASK)
133 
134 #define VIRT_WRAP_REG_A_PAD_2_MASK               (0x30U)
135 #define VIRT_WRAP_REG_A_PAD_2_SHIFT              (4U)
136 #define VIRT_WRAP_REG_A_PAD_2_WIDTH              (2U)
137 #define VIRT_WRAP_REG_A_PAD_2(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_2_SHIFT)) & VIRT_WRAP_REG_A_PAD_2_MASK)
138 
139 #define VIRT_WRAP_REG_A_PAD_3_MASK               (0xC0U)
140 #define VIRT_WRAP_REG_A_PAD_3_SHIFT              (6U)
141 #define VIRT_WRAP_REG_A_PAD_3_WIDTH              (2U)
142 #define VIRT_WRAP_REG_A_PAD_3(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_3_SHIFT)) & VIRT_WRAP_REG_A_PAD_3_MASK)
143 
144 #define VIRT_WRAP_REG_A_PAD_4_MASK               (0x300U)
145 #define VIRT_WRAP_REG_A_PAD_4_SHIFT              (8U)
146 #define VIRT_WRAP_REG_A_PAD_4_WIDTH              (2U)
147 #define VIRT_WRAP_REG_A_PAD_4(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_4_SHIFT)) & VIRT_WRAP_REG_A_PAD_4_MASK)
148 
149 #define VIRT_WRAP_REG_A_PAD_5_MASK               (0xC00U)
150 #define VIRT_WRAP_REG_A_PAD_5_SHIFT              (10U)
151 #define VIRT_WRAP_REG_A_PAD_5_WIDTH              (2U)
152 #define VIRT_WRAP_REG_A_PAD_5(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_5_SHIFT)) & VIRT_WRAP_REG_A_PAD_5_MASK)
153 
154 #define VIRT_WRAP_REG_A_PAD_6_MASK               (0x3000U)
155 #define VIRT_WRAP_REG_A_PAD_6_SHIFT              (12U)
156 #define VIRT_WRAP_REG_A_PAD_6_WIDTH              (2U)
157 #define VIRT_WRAP_REG_A_PAD_6(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_6_SHIFT)) & VIRT_WRAP_REG_A_PAD_6_MASK)
158 
159 #define VIRT_WRAP_REG_A_PAD_7_MASK               (0xC000U)
160 #define VIRT_WRAP_REG_A_PAD_7_SHIFT              (14U)
161 #define VIRT_WRAP_REG_A_PAD_7_WIDTH              (2U)
162 #define VIRT_WRAP_REG_A_PAD_7(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_7_SHIFT)) & VIRT_WRAP_REG_A_PAD_7_MASK)
163 
164 #define VIRT_WRAP_REG_A_PAD_8_MASK               (0x30000U)
165 #define VIRT_WRAP_REG_A_PAD_8_SHIFT              (16U)
166 #define VIRT_WRAP_REG_A_PAD_8_WIDTH              (2U)
167 #define VIRT_WRAP_REG_A_PAD_8(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_8_SHIFT)) & VIRT_WRAP_REG_A_PAD_8_MASK)
168 
169 #define VIRT_WRAP_REG_A_PAD_9_MASK               (0xC0000U)
170 #define VIRT_WRAP_REG_A_PAD_9_SHIFT              (18U)
171 #define VIRT_WRAP_REG_A_PAD_9_WIDTH              (2U)
172 #define VIRT_WRAP_REG_A_PAD_9(x)                 (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_9_SHIFT)) & VIRT_WRAP_REG_A_PAD_9_MASK)
173 
174 #define VIRT_WRAP_REG_A_PAD_10_MASK              (0x300000U)
175 #define VIRT_WRAP_REG_A_PAD_10_SHIFT             (20U)
176 #define VIRT_WRAP_REG_A_PAD_10_WIDTH             (2U)
177 #define VIRT_WRAP_REG_A_PAD_10(x)                (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_10_SHIFT)) & VIRT_WRAP_REG_A_PAD_10_MASK)
178 
179 #define VIRT_WRAP_REG_A_PAD_11_MASK              (0xC00000U)
180 #define VIRT_WRAP_REG_A_PAD_11_SHIFT             (22U)
181 #define VIRT_WRAP_REG_A_PAD_11_WIDTH             (2U)
182 #define VIRT_WRAP_REG_A_PAD_11(x)                (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_11_SHIFT)) & VIRT_WRAP_REG_A_PAD_11_MASK)
183 
184 #define VIRT_WRAP_REG_A_PAD_12_MASK              (0x3000000U)
185 #define VIRT_WRAP_REG_A_PAD_12_SHIFT             (24U)
186 #define VIRT_WRAP_REG_A_PAD_12_WIDTH             (2U)
187 #define VIRT_WRAP_REG_A_PAD_12(x)                (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_12_SHIFT)) & VIRT_WRAP_REG_A_PAD_12_MASK)
188 
189 #define VIRT_WRAP_REG_A_PAD_13_MASK              (0xC000000U)
190 #define VIRT_WRAP_REG_A_PAD_13_SHIFT             (26U)
191 #define VIRT_WRAP_REG_A_PAD_13_WIDTH             (2U)
192 #define VIRT_WRAP_REG_A_PAD_13(x)                (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_13_SHIFT)) & VIRT_WRAP_REG_A_PAD_13_MASK)
193 
194 #define VIRT_WRAP_REG_A_PAD_14_MASK              (0x30000000U)
195 #define VIRT_WRAP_REG_A_PAD_14_SHIFT             (28U)
196 #define VIRT_WRAP_REG_A_PAD_14_WIDTH             (2U)
197 #define VIRT_WRAP_REG_A_PAD_14(x)                (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_14_SHIFT)) & VIRT_WRAP_REG_A_PAD_14_MASK)
198 
199 #define VIRT_WRAP_REG_A_PAD_15_MASK              (0xC0000000U)
200 #define VIRT_WRAP_REG_A_PAD_15_SHIFT             (30U)
201 #define VIRT_WRAP_REG_A_PAD_15_WIDTH             (2U)
202 #define VIRT_WRAP_REG_A_PAD_15(x)                (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_A_PAD_15_SHIFT)) & VIRT_WRAP_REG_A_PAD_15_MASK)
203 /*! @} */
204 
205 /*! @name REG_B - Parameter_n Register */
206 /*! @{ */
207 
208 #define VIRT_WRAP_REG_B_INMUX_0_MASK             (0x3U)
209 #define VIRT_WRAP_REG_B_INMUX_0_SHIFT            (0U)
210 #define VIRT_WRAP_REG_B_INMUX_0_WIDTH            (2U)
211 #define VIRT_WRAP_REG_B_INMUX_0(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_0_SHIFT)) & VIRT_WRAP_REG_B_INMUX_0_MASK)
212 
213 #define VIRT_WRAP_REG_B_INMUX_1_MASK             (0xCU)
214 #define VIRT_WRAP_REG_B_INMUX_1_SHIFT            (2U)
215 #define VIRT_WRAP_REG_B_INMUX_1_WIDTH            (2U)
216 #define VIRT_WRAP_REG_B_INMUX_1(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_1_SHIFT)) & VIRT_WRAP_REG_B_INMUX_1_MASK)
217 
218 #define VIRT_WRAP_REG_B_INMUX_2_MASK             (0x30U)
219 #define VIRT_WRAP_REG_B_INMUX_2_SHIFT            (4U)
220 #define VIRT_WRAP_REG_B_INMUX_2_WIDTH            (2U)
221 #define VIRT_WRAP_REG_B_INMUX_2(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_2_SHIFT)) & VIRT_WRAP_REG_B_INMUX_2_MASK)
222 
223 #define VIRT_WRAP_REG_B_INMUX_3_MASK             (0xC0U)
224 #define VIRT_WRAP_REG_B_INMUX_3_SHIFT            (6U)
225 #define VIRT_WRAP_REG_B_INMUX_3_WIDTH            (2U)
226 #define VIRT_WRAP_REG_B_INMUX_3(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_3_SHIFT)) & VIRT_WRAP_REG_B_INMUX_3_MASK)
227 
228 #define VIRT_WRAP_REG_B_INMUX_4_MASK             (0x300U)
229 #define VIRT_WRAP_REG_B_INMUX_4_SHIFT            (8U)
230 #define VIRT_WRAP_REG_B_INMUX_4_WIDTH            (2U)
231 #define VIRT_WRAP_REG_B_INMUX_4(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_4_SHIFT)) & VIRT_WRAP_REG_B_INMUX_4_MASK)
232 
233 #define VIRT_WRAP_REG_B_INMUX_5_MASK             (0xC00U)
234 #define VIRT_WRAP_REG_B_INMUX_5_SHIFT            (10U)
235 #define VIRT_WRAP_REG_B_INMUX_5_WIDTH            (2U)
236 #define VIRT_WRAP_REG_B_INMUX_5(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_5_SHIFT)) & VIRT_WRAP_REG_B_INMUX_5_MASK)
237 
238 #define VIRT_WRAP_REG_B_INMUX_6_MASK             (0x3000U)
239 #define VIRT_WRAP_REG_B_INMUX_6_SHIFT            (12U)
240 #define VIRT_WRAP_REG_B_INMUX_6_WIDTH            (2U)
241 #define VIRT_WRAP_REG_B_INMUX_6(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_6_SHIFT)) & VIRT_WRAP_REG_B_INMUX_6_MASK)
242 
243 #define VIRT_WRAP_REG_B_INMUX_7_MASK             (0xC000U)
244 #define VIRT_WRAP_REG_B_INMUX_7_SHIFT            (14U)
245 #define VIRT_WRAP_REG_B_INMUX_7_WIDTH            (2U)
246 #define VIRT_WRAP_REG_B_INMUX_7(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_7_SHIFT)) & VIRT_WRAP_REG_B_INMUX_7_MASK)
247 
248 #define VIRT_WRAP_REG_B_INMUX_8_MASK             (0x30000U)
249 #define VIRT_WRAP_REG_B_INMUX_8_SHIFT            (16U)
250 #define VIRT_WRAP_REG_B_INMUX_8_WIDTH            (2U)
251 #define VIRT_WRAP_REG_B_INMUX_8(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_8_SHIFT)) & VIRT_WRAP_REG_B_INMUX_8_MASK)
252 
253 #define VIRT_WRAP_REG_B_INMUX_9_MASK             (0xC0000U)
254 #define VIRT_WRAP_REG_B_INMUX_9_SHIFT            (18U)
255 #define VIRT_WRAP_REG_B_INMUX_9_WIDTH            (2U)
256 #define VIRT_WRAP_REG_B_INMUX_9(x)               (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_9_SHIFT)) & VIRT_WRAP_REG_B_INMUX_9_MASK)
257 
258 #define VIRT_WRAP_REG_B_INMUX_10_MASK            (0x300000U)
259 #define VIRT_WRAP_REG_B_INMUX_10_SHIFT           (20U)
260 #define VIRT_WRAP_REG_B_INMUX_10_WIDTH           (2U)
261 #define VIRT_WRAP_REG_B_INMUX_10(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_10_SHIFT)) & VIRT_WRAP_REG_B_INMUX_10_MASK)
262 
263 #define VIRT_WRAP_REG_B_INMUX_11_MASK            (0xC00000U)
264 #define VIRT_WRAP_REG_B_INMUX_11_SHIFT           (22U)
265 #define VIRT_WRAP_REG_B_INMUX_11_WIDTH           (2U)
266 #define VIRT_WRAP_REG_B_INMUX_11(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_11_SHIFT)) & VIRT_WRAP_REG_B_INMUX_11_MASK)
267 
268 #define VIRT_WRAP_REG_B_INMUX_12_MASK            (0x3000000U)
269 #define VIRT_WRAP_REG_B_INMUX_12_SHIFT           (24U)
270 #define VIRT_WRAP_REG_B_INMUX_12_WIDTH           (2U)
271 #define VIRT_WRAP_REG_B_INMUX_12(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_12_SHIFT)) & VIRT_WRAP_REG_B_INMUX_12_MASK)
272 
273 #define VIRT_WRAP_REG_B_INMUX_13_MASK            (0xC000000U)
274 #define VIRT_WRAP_REG_B_INMUX_13_SHIFT           (26U)
275 #define VIRT_WRAP_REG_B_INMUX_13_WIDTH           (2U)
276 #define VIRT_WRAP_REG_B_INMUX_13(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_13_SHIFT)) & VIRT_WRAP_REG_B_INMUX_13_MASK)
277 
278 #define VIRT_WRAP_REG_B_INMUX_14_MASK            (0x30000000U)
279 #define VIRT_WRAP_REG_B_INMUX_14_SHIFT           (28U)
280 #define VIRT_WRAP_REG_B_INMUX_14_WIDTH           (2U)
281 #define VIRT_WRAP_REG_B_INMUX_14(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_14_SHIFT)) & VIRT_WRAP_REG_B_INMUX_14_MASK)
282 
283 #define VIRT_WRAP_REG_B_INMUX_15_MASK            (0xC0000000U)
284 #define VIRT_WRAP_REG_B_INMUX_15_SHIFT           (30U)
285 #define VIRT_WRAP_REG_B_INMUX_15_WIDTH           (2U)
286 #define VIRT_WRAP_REG_B_INMUX_15(x)              (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_B_INMUX_15_SHIFT)) & VIRT_WRAP_REG_B_INMUX_15_MASK)
287 /*! @} */
288 
289 /*! @name REG_C - Parameter_n Register */
290 /*! @{ */
291 
292 #define VIRT_WRAP_REG_C_INTC_CTRL_MASK           (0x3U)
293 #define VIRT_WRAP_REG_C_INTC_CTRL_SHIFT          (0U)
294 #define VIRT_WRAP_REG_C_INTC_CTRL_WIDTH          (2U)
295 #define VIRT_WRAP_REG_C_INTC_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << VIRT_WRAP_REG_C_INTC_CTRL_SHIFT)) & VIRT_WRAP_REG_C_INTC_CTRL_MASK)
296 /*! @} */
297 
298 /*!
299  * @}
300  */ /* end of group VIRT_WRAP_Register_Masks */
301 
302 /*!
303  * @}
304  */ /* end of group VIRT_WRAP_Peripheral_Access_Layer */
305 
306 #endif  /* #if !defined(S32Z2_VIRT_WRAP_H_) */
307